JPH01251619A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01251619A JPH01251619A JP7946088A JP7946088A JPH01251619A JP H01251619 A JPH01251619 A JP H01251619A JP 7946088 A JP7946088 A JP 7946088A JP 7946088 A JP7946088 A JP 7946088A JP H01251619 A JPH01251619 A JP H01251619A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- type semiconductor
- layer
- substrate
- interconnections
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000005530 etching Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 230000007423 decrease Effects 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000010408 film Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a method of manufacturing a semiconductor device.
近年、半導体装置の加工方法の中で、電気化学現象を用
いたエツチング方法が注目をあびている。In recent years, among methods for processing semiconductor devices, etching methods using electrochemical phenomena have been attracting attention.
その技術は通常、初めに、P型の半導体基板の片面に、
拡散法、またはエピタキシー成長法などを用いて、N型
半導体層を設け、PN接合を形成した構造の基板を用意
する。ついで、N型半導体をエツチング溶液中において
、陽極酸化反応によってこれに酸化シリコンの膜が生成
する程度に正の電圧を加え4、エツチングがP型半導体
面からN型半導体に到った時に、そのPN接合の界面近
傍に酸化膜を形成せしめ、エツチングをその界面で停止
させるという方法により行われている。しかし、そのた
めには外部から電圧を供給する必要が生じる。第2図に
従来用いられてきた基板を示す。図において、従来は、
半導体ウェファ−11における主回路部分12を設けた
片面周辺部を収り巻くように、円形に高濃度拡散領域1
3、つまり、低抵抗層を設けることにより、外部配線と
の接触抵抗を小さく保ったまま、導通がとれる様にし、
そこに外から所望の電圧および電流を定電圧電源より供
給できるように工夫していた。The technology usually involves first depositing on one side of a P-type semiconductor substrate.
A substrate having a structure in which an N-type semiconductor layer is provided and a PN junction is formed using a diffusion method, an epitaxy growth method, or the like is prepared. Next, a positive voltage is applied to the N-type semiconductor in an etching solution to the extent that a silicon oxide film is formed on it by an anodic oxidation reaction4, and when the etching reaches the N-type semiconductor from the P-type semiconductor surface, the This is done by forming an oxide film near the PN junction interface and stopping etching at that interface. However, this requires an external voltage supply. FIG. 2 shows a conventionally used substrate. In the figure, conventionally,
A circular high-concentration diffusion region 1 is formed around the periphery of one side of the semiconductor wafer 11 where the main circuit portion 12 is provided.
3. In other words, by providing a low-resistance layer, we can maintain continuity while keeping the contact resistance with external wiring low.
It was devised so that the desired voltage and current could be supplied from outside using a constant voltage power supply.
ところで、エツチング溶液中でのシリコン酸化膜の生成
は、半導体にかかる電位によって制御されるので、以上
述べた構造においては、円周部分以外のシリコン部分の
電気抵抗は、円周部に比べてかなり高いため、円周部か
ら中心部に向うにしたがって、外部から供給される電圧
とは異なった電圧となり、かつ、エツチングの進行とと
もにシリコンの膜厚は減少して行くために、さらに抵抗
値は大きな値に増加し、外部電源による設定電圧値と各
チップ部分における電圧値の差異は顕著となり、中心部
分はエツチングがPN接合界面に到達する以前に、酸化
j摸が形成され始め、本来ならエツチングされるべきシ
リコンの部分がエツチングされずに残ってしまい、結局
正確なエツチングが行えないという、深刻な問題点があ
った。By the way, the formation of a silicon oxide film in an etching solution is controlled by the potential applied to the semiconductor, so in the structure described above, the electrical resistance of the silicon portion other than the circumferential portion is considerably lower than that of the circumferential portion. Because of this, the voltage becomes different from the voltage supplied from the outside as you move from the circumference to the center, and as the silicon film thickness decreases as etching progresses, the resistance value becomes even higher. As the value increases, the difference between the set voltage value by the external power supply and the voltage value at each chip portion becomes significant, and before the etching reaches the PN junction interface, an oxide layer begins to form in the central portion, which would otherwise be etched. There was a serious problem in that a portion of the silicon that should be etched remained unetched, making it impossible to perform accurate etching.
本発明の目的は、上記従来の問題点を完全に克服し、確
実にシリコンのエツチングが遂行できる方法を提供する
ことにある。An object of the present invention is to provide a method that completely overcomes the above-mentioned conventional problems and can reliably perform silicon etching.
上記目的を達成するため、本発明の半導体装置の製造方
法においては、電気化学エツチングを用いた半導体装置
の製造方法において、主電子回路とは別に作りたい構造
物の少なくとも近傍まで基板の両面に低抵抗層を設け、
該低抵抗層を電気化学エツチングのための電極と接続す
るものである。In order to achieve the above object, in the method of manufacturing a semiconductor device of the present invention, in a method of manufacturing a semiconductor device using electrochemical etching, etching is applied to both sides of the substrate up to at least the vicinity of the structure to be formed separately from the main electronic circuit. Provide a resistance layer,
The low resistance layer is connected to an electrode for electrochemical etching.
本発明の電気化学エツチング法は、主回路形成部分以外
の部分に電気化学エツチングに必要とされる電圧および
電流を供給するための低抵抗回路を基板の両面に形成し
、これを外部電源と接続することにより、電気化学エツ
チングによって取り除こうとする部分の電位を精密に制
御することができるようにしている。これによって、エ
ツチングが完全に行われ、必要とされる任意の形状にエ
ツチングを施すことが可能である。The electrochemical etching method of the present invention involves forming low resistance circuits on both sides of the substrate to supply the voltage and current required for electrochemical etching to parts other than the main circuit forming part, and connecting these to an external power supply. This makes it possible to precisely control the potential of the portion to be removed by electrochemical etching. This ensures that the etching is complete and that any shape required can be etched.
以下の図面に基づいて、本発明に係わる方法の1&適な
実施例を説明する。BRIEF DESCRIPTION OF THE DRAWINGS One & preferred embodiment of the method according to the invention will be explained on the basis of the following drawings.
第1図(a) 、 (b)はそれぞれ基板1の表面と、
裏面とを示している。2は表面側の主回路部分、3は裏
面側の主回路部分である。主回路部分の各チップの周辺
に1ミリメートル程度のスクライブ領域を設け、そこに
イオンインブランティジョン、もしくは、拡散法により
表面のP型半導体層面にはP+配線4、および裏面のN
型半導体層面にはN+配線5を形成する。その後に表面
に5if2などの保護層を設ける。この導電路の形成は
、各半導体チップに同じ様に電圧が加わる事を促す働き
と、外部との電気回路接続の際に起こる接触抵抗を激減
させる働きを持っている。その後、外部に設けた定電圧
電源に接続し、N型半導体層から成るエツチングによっ
て作製しようとする構造物を、その表面において陽極酸
化が起こり、5t02が生成する程度に、プラスの電位
になるようにN+配線5を通じて設定する、一方、エツ
チングによって切り取られる、P型半導体層部分を通常
シリコン基板に対して外から何も電圧を加えないときに
、Stの異方性エツチングがill!続して起こる、自
然平衡電位よりもマイナス側になるように、P+配線4
を通じて設定し、エチレンジアミン系、KOH系、およ
びヒドラジン系、等のシリコン異方性エツチングが可能
な溶液に浸し、90度付近に加温してエツチングを行う
0通常P型半導体層からエツチングは行われるが、配線
の線材としてアルミのような金属を用いると、それが異
方性エツチングの進行中にサイドエツチングされ、導体
としての働きを失う、又それらのとけた金属は、エツチ
ング液を汚染しエツチング液の寿命を著しく短くする。FIGS. 1(a) and 1(b) respectively show the surface of the substrate 1,
The back side is shown. 2 is a main circuit portion on the front side, and 3 is a main circuit portion on the back side. A scribe area of approximately 1 mm is provided around each chip in the main circuit section, and ion implantation or diffusion is applied thereto to form a P+ wiring 4 on the P-type semiconductor layer surface on the front surface, and an N
An N+ wiring 5 is formed on the surface of the type semiconductor layer. After that, a protective layer such as 5if2 is provided on the surface. The formation of this conductive path has the function of promoting the application of voltage to each semiconductor chip in the same way, and the function of drastically reducing the contact resistance that occurs when connecting an external electrical circuit. After that, it is connected to an external constant voltage power supply, and the structure to be fabricated by etching consisting of the N-type semiconductor layer is heated to a positive potential to the extent that anodic oxidation occurs on the surface and 5t02 is generated. On the other hand, when no voltage is applied from the outside to the P-type semiconductor layer portion cut out by etching to the silicon substrate, the anisotropic etching of St ill! The P+ wiring 4 is connected so that it is on the negative side of the natural equilibrium potential that occurs subsequently.
Etching is performed by immersing silicon in a solution capable of anisotropic etching such as ethylenediamine, KOH, or hydrazine, and heating it to around 90 degrees.0 Etching is usually performed from the P-type semiconductor layer. However, when metals such as aluminum are used as wiring wires, they are side-etched during anisotropic etching and lose their function as conductors, and the melted metals contaminate the etching solution and cause etching problems. Significantly shortens the life of the liquid.
ところが、拡散層を伝導層として用い、表面を3i02
にて保護しておけば、上記欠点を克服することが可能で
ある。尚、この様に、導電体層を設けると、従来の方法
では円形にシリコンウェファ−の外周部を1センチメー
トル程度N+層の形成に費やしていたために、チップの
有効作製面積が、極端に下がる事が認められたが、それ
を著しく改良することも可能である。However, when the diffusion layer is used as a conductive layer, the surface becomes 3i02
It is possible to overcome the above drawbacks by protecting the In addition, when a conductor layer is provided in this way, the effective manufacturing area of the chip is extremely reduced because in the conventional method, about 1 cm of the outer circumference of the circular silicon wafer is used to form the N+ layer. However, it is possible to improve it significantly.
図においてはスクライブ領域以外の周辺にも導電体層が
設けられているが外部電源に対して接続できる場所さえ
設ければその部分はなくても構わない。In the figure, a conductor layer is also provided around the area other than the scribe area, but that part may be omitted as long as a place that can be connected to an external power source is provided.
以上説明したように、本発明によれば、シリコンウェフ
ァ−のどの部分にも外から加えた電圧か、均−にかかる
様に制御できるので、エツチングによる薄膜形成は、非
常に微細な形であっても、すべての部分に対して極めて
良好であり、全てのチップを製品として用いることが可
能となる。As explained above, according to the present invention, the voltage applied from the outside can be controlled so as to be uniformly applied to any part of the silicon wafer, so that thin films can be formed by etching in very fine shapes. However, all parts are extremely good, and all chips can be used as products.
第1図(a)は本発明による電気化学エツチングに使用
される半導体基板の平面図、(b)は底面図、第2図は
従来電気化学エツチング使用されていた半導体基板の平
面図である。
1・・・基板 2・・・主回路部分3・・
・主回路部分 4・・・P+配線5・・・N+配
線
特許出願人 日本電気株式会社
代 理 人 弁理士 内 原 晋(αつ
(b)
第1図FIG. 1(a) is a plan view of a semiconductor substrate used for electrochemical etching according to the present invention, FIG. 1(b) is a bottom view, and FIG. 2 is a plan view of a semiconductor substrate conventionally used for electrochemical etching. 1... Board 2... Main circuit part 3...
・Main circuit part 4...P+ wiring 5...N+ wiring Patent applicant NEC Corporation Agent Patent attorney Susumu Uchihara (α(b)) Figure 1
Claims (1)
において、主電子回路とは別に作りたい構造物の少なく
とも近傍まで基板の両面に低抵抗層を設け、該低抵抗層
を電気化学エッチングのための電極と接続することを特
徴とする半導体装置の製造方法。1. In a method of manufacturing a semiconductor device using electrochemical etching, a low resistance layer is provided on both sides of the substrate up to at least the vicinity of the structure to be formed separately from the main electronic circuit, and the low resistance layer is used for electrochemical etching. A method for manufacturing a semiconductor device, characterized in that it is connected to an electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7946088A JPH01251619A (en) | 1988-03-30 | 1988-03-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7946088A JPH01251619A (en) | 1988-03-30 | 1988-03-30 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01251619A true JPH01251619A (en) | 1989-10-06 |
JPH0450737B2 JPH0450737B2 (en) | 1992-08-17 |
Family
ID=13690491
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7946088A Granted JPH01251619A (en) | 1988-03-30 | 1988-03-30 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01251619A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5508038A (en) * | 1990-04-16 | 1996-04-16 | Alza Corporation | Polyisobutylene adhesives for transdermal devices |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101873583B1 (en) * | 2011-01-12 | 2018-07-03 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
-
1988
- 1988-03-30 JP JP7946088A patent/JPH01251619A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5508038A (en) * | 1990-04-16 | 1996-04-16 | Alza Corporation | Polyisobutylene adhesives for transdermal devices |
Also Published As
Publication number | Publication date |
---|---|
JPH0450737B2 (en) | 1992-08-17 |
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