JPS58134466A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58134466A JPS58134466A JP1612782A JP1612782A JPS58134466A JP S58134466 A JPS58134466 A JP S58134466A JP 1612782 A JP1612782 A JP 1612782A JP 1612782 A JP1612782 A JP 1612782A JP S58134466 A JPS58134466 A JP S58134466A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- forming
- conductivity type
- type region
- contact window
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 239000004020 conductor Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 238000009832 plasma treatment Methods 0.000 claims description 6
- 230000005684 electric field Effects 0.000 abstract description 6
- 230000002209 hydrophobic effect Effects 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract 4
- 239000000853 adhesive Substances 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 241000283690 Bos taurus Species 0.000 description 2
- 206010011224 Cough Diseases 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に高耐圧半導
体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a high voltage semiconductor device.
従来、半導体装置の高耐圧化を図るために、半導体基板
に設けられ九素子部を囲むいわゆるガードリングが用い
られてきた。Conventionally, in order to increase the breakdown voltage of a semiconductor device, a so-called guard ring, which is provided on a semiconductor substrate and surrounds a nine-element section, has been used.
第1図は従来の半導体装置の一例の断面図である。FIG. 1 is a sectional view of an example of a conventional semiconductor device.
N型半導体基板lの素子部(図示せず)會囲むP型領域
2t−設け、半導体基板表面に生成する酸化膜3を選択
エツチングしてコンタクト用窓t−あけ、アルミニウム
あるいはポリシリコン等で電極゛4t−形成する。A P-type region 2t surrounding an element part (not shown) of an N-type semiconductor substrate 1 is provided, an oxide film 3 formed on the surface of the semiconductor substrate is selectively etched to open a contact window t, and an electrode is formed using aluminum or polysilicon.゛4t-form.
今、半導体基板lと電極4との間に逆バイアスを印加す
ると、破線5で示すように空乏層6が拡がる。空乏層6
は電極4の下の半導体基板表面下では均一に拡がる。従
って、図のA部に電界が集中しゃすくなシ耐圧が十分に
大きくならないという欠点がある。Now, when a reverse bias is applied between the semiconductor substrate l and the electrode 4, the depletion layer 6 expands as shown by the broken line 5. depletion layer 6
spreads uniformly under the surface of the semiconductor substrate below the electrode 4. Therefore, there is a drawback that the electric field is concentrated at the part A in the figure and the withstand voltage is not sufficiently large.
第2図は従来の半導体装置の他の例の断面図である。FIG. 2 is a sectional view of another example of a conventional semiconductor device.
半導体基板IKP型領域2t−設けt後、コンタクト用
窓の所に窒化膜を設けておいて熱酸化を行うと、窒化膜
の耐酸化性の九めに窒化膜の周縁が傾角t−もって酸化
され、図QBで示すようにコンタクト用窓周縁に傾斜會
有する酸化膜3が得られる。しかる後、窒化膜を除去し
、電極4を設ける。After forming the IKP type region 2t on the semiconductor substrate, a nitride film is provided at the contact window and thermal oxidation is performed. As shown in FIG. QB, an oxide film 3 having a slope at the periphery of the contact window is obtained. Thereafter, the nitride film is removed and an electrode 4 is provided.
このような構造にすると空乏層6はA部において丸味を
帯びて滑らかになり電界集中が起シにくく耐圧の向上に
寄与する。しかし、この構造を実現するためには、酸化
膜の形成後に窒化膜の成長、窒化膜のバター二/グ、窒
化膜をマスクとする熱酸化、窒化膜の除去というように
製造工程が長くなシ、窒化膜成長等の高価な工程を必要
とするのみならず、酸化膜3のB部に丸味がついている
ので十分にA部の電界集中を緩和できないという欠点が
あり几。With such a structure, the depletion layer 6 becomes rounded and smooth in the portion A, making it difficult for electric field concentration to occur, contributing to an improvement in breakdown voltage. However, in order to realize this structure, the manufacturing process is long, including growing a nitride film after forming an oxide film, buttering the nitride film, thermal oxidation using the nitride film as a mask, and removing the nitride film. However, it not only requires an expensive process such as growing a nitride film, but also has the drawback that the electric field concentration in the A part cannot be sufficiently alleviated because the B part of the oxide film 3 is rounded.
本発明は上記欠点を除去し、容易に実施できる工程を用
い、同じ抵抗率の半導体基板を用いても耐圧特性を改善
できる半導体装置の製造方法を提1′、。The present invention provides a method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks, uses an easily implemented process, and improves breakdown voltage characteristics even when semiconductor substrates having the same resistivity are used.
供するものである。This is what we provide.
本発明の半導体装置の製造方法の第1の万@は、半導体
素子部が形成ぼれている第1導電戯牛導体基板の前1e
hP導体素子部を間隔をおいて囲む第2導電截領域を形
成する工程と、前記第、2導電製領域形成工程中に前記
第2導eL微領域とその周縁の上に生成する酸化膜の表
面を親水性にする酸素プラズマ処理を行う工程と、前記
半導体基板上の酸化膜の表面にホトレジストのマスクを
形成し前記酸化膜t−選択エツチングして前記第2導電
型領域上の酸化膜にコンタクト用窓をあけると同時に該
コンタクト用窓周縁の酸化膜に傾斜をつける工程と、前
記コンタクト用窓を介して前記第2導電型領域に接続す
る電極並びに配NAt−形成する工程と金含んで構成葛
れる。The first step in the method for manufacturing a semiconductor device of the present invention is the front 1e of the first conductive conductor substrate on which the semiconductor element portion is formed.
A step of forming a second conductive cut region surrounding the hP conductor element portion at intervals, and an oxide film formed on the second conductive eL micro region and its periphery during the step of forming the second conductive region. a step of performing oxygen plasma treatment to make the surface hydrophilic; forming a photoresist mask on the surface of the oxide film on the semiconductor substrate and selectively etching the oxide film on the second conductivity type region; a step of simultaneously opening a contact window and slanting an oxide film around the contact window; a step of forming an electrode and an interconnection layer connected to the second conductivity type region through the contact window; The composition is confusing.
本発明の半導体装置の製造方法の第2の方法は、半導体
素子部が形成場れている第1導電型牛導体基板の前dピ
半導体素子部を間隔をおいて囲む第2導電型領域と該第
2導電型領域を間隔をおいて囲む第2導電屋ガードリン
グを形成する工程と、前記第2導電型領域並びに前記ガ
ードリング形成工程中に生成する酸化膜のうち前記ガー
ドリングと七の周縁上の酸化膜の表面を親水性にする酸
素プラズマ処理を行う工程と、前記半導体基板上の酸化
膜の表面にホトレジストのマスクを形成し、前記酸化膜
を選択エツチングして前記ガードリング上の酸化膜にコ
ンタクト用窓をあけると同時に咳コンタクト用窓周縁の
酸化膜に傾斜管つける工程と、前記コンタクト用窓を介
して前記ガードリングに接続する電極並びに配線を形成
する工程とを含んで構成される。A second method of manufacturing a semiconductor device according to the present invention includes forming a second conductivity type region that surrounds the front d-pi semiconductor element portion of the first conductivity type conductor substrate, on which the semiconductor element portion is formed, at intervals; forming a second conductive guard ring that surrounds the second conductive type region at intervals; A step of performing oxygen plasma treatment to make the surface of the oxide film on the periphery hydrophilic, forming a photoresist mask on the surface of the oxide film on the semiconductor substrate, selectively etching the oxide film, and etching the surface of the oxide film on the guard ring. Consisting of the steps of: opening a contact window in the oxide film and simultaneously attaching an inclined tube to the oxide film around the cough contact window; and forming electrodes and wiring connected to the guard ring via the contact window. be done.
次に本発明の実)1例について図面を用いて説明する。Next, one example of the present invention will be explained with reference to the drawings.
実1tA例の説明においては第1導電ff1tN型、第
2導電型tF製とする。In the description of the actual 1tA example, the first conductivity type is ff1tN type and the second conductivity type is tF.
第3図は本発明の第1の実施FIJt説明するための断
面図である。FIG. 3 is a sectional view for explaining the first embodiment FIJt of the present invention.
N警手導体基板lの素子部(図示せず>ttSむP型領
域2t−設ける。P型領域2の形成時にP型領域2上に
も酸化膜が生成される。P型領域2の上及びその周縁【
酸素プラズマ処理tして酸化膜表面を親水性にする。こ
れには数百ワットで数十秒の酸素プラズマ処理を行えば
良い。次に、酸化膜30表面にホトレジストを設け、)
(ターニングする。そして酸化膜3をエツチングしてコ
ンタクト用窓あけtする。ホトレジストは疎水性である
のでプラズマ処理された親水性の酸化膜への付着性が悪
くなっている。この状態で酸化膜のエツチング全行うと
ホトレジストの下にエツチング液が滲みこんでエツチン
グが進むので酸化[3はコンタクト用窓周縁で傾斜をも
つことになる。そして電極4七形成する。A P-type region 2t (not shown) of the N-type conductor substrate l (not shown) is provided on the P-type region 2. An oxide film is also generated on the P-type region 2 when the P-type region 2 is formed. and its periphery [
Oxygen plasma treatment is performed to make the oxide film surface hydrophilic. This can be achieved by performing oxygen plasma treatment at several hundred watts for several tens of seconds. Next, a photoresist is provided on the surface of the oxide film 30,
(Then, the oxide film 3 is etched to open a contact window. Since the photoresist is hydrophobic, it has poor adhesion to the plasma-treated hydrophilic oxide film. In this state, the oxide film When the etching is completed, the etching solution seeps under the photoresist and the etching progresses, resulting in oxidation [3] having a slope at the periphery of the contact window.An electrode 47 is then formed.
上記製造方法によると、酸化膜3に丸味がつかない斜面
となるので空乏層6がA部において極めて緩やかに丸味
を帯びるようになシ、電界強度が弱められ、耐圧が極め
て同上する。According to the above manufacturing method, since the oxide film 3 has an unrounded slope, the depletion layer 6 is very gently rounded at the portion A, the electric field strength is weakened, and the withstand voltage is extremely high.
第4図は本発明の#!2の実MしUt−説明するための
断面図である。Figure 4 shows #! of the present invention. FIG. 2 is a sectional view for explaining the actual M and Ut of FIG.
N型半導体基板1の素子部(図示せず)t−間隔をおい
て囲むP型領域2t−更に間隔金おいて囲むP型ガード
リ/グアt−設ける。そしてガードリング7に対して第
1の実N?!Iと同じ製造方法を適用してガードリング
7のコンタクト用窓周縁の酸化物3に傾斜面を形成し、
電極4を形成する。空乏層6は第1の実施例と同様にA
部において丸味を帯びるようになシ、高耐圧化が実現す
る。An element portion (not shown) of an N-type semiconductor substrate 1 is provided with a P-type region 2t surrounded by a spacing t and a P-type guard t surrounded by a further spacing. And the first real N for guard ring 7? ! Applying the same manufacturing method as I, forming an inclined surface on the oxide 3 around the contact window of the guard ring 7,
Electrode 4 is formed. The depletion layer 6 is A as in the first embodiment.
The parts are rounded and high pressure resistance is achieved.
以上詳細に説明し友ように、本発明によれば、容易に実
施できる方法で高耐圧化を実現する牛導体Hkの製造方
法が得られるのでその効果は大きい。As described in detail above, according to the present invention, a method for manufacturing a conductor Hk that achieves high voltage resistance by a method that can be easily carried out can be obtained, so that the effect is large.
第1図は従来鍍の牛導体装置の一例の断面図、第2図は
従来の牛導体装置の他のガの断面図、第3図は本発明の
第1の実311FIJ を説明する友めの断面図、第4
図は本発明の第2の実J1gAUt−説明するための断
面図である。
l・・・・・・N型中導体基板、2・・・・・・P型領
域、3・・・・・・酸化膜、4・・・・・・電極、6・
・・・・・空乏層、7・・・・・・ガードリング。
ニジ
A や1図 1
1
拵2図
1
第3図
A 15
第4図Fig. 1 is a sectional view of an example of a conventional cattle conductor device, Fig. 2 is a sectional view of another conventional cattle conductor device, and Fig. 3 is a friend explaining the first fruit of the present invention. cross-sectional view, 4th
The figure is a sectional view for explaining the second embodiment J1gAUt of the present invention. l...N-type medium conductor substrate, 2...P-type region, 3...oxide film, 4...electrode, 6...
... Depletion layer, 7... Guard ring. Niji A Ya1 Figure 1 1 Koshirae 2 Figure 1 Figure 3 A 15 Figure 4
Claims (2)
牛導体基板前記半導体素子部を間隔をおいて囲む第2導
電型領域を形成する工程と、前記第2導電型領域形成工
程中に前記8I2導電型領域とその周縁の上に生成する
酸化膜の表面を現水性にする酸素プラズマ処理を行う工
程と、前記半導体基板上の酸化膜の表面にホトレジスト
のマスクを形成し前記酸化膜を選択エツチングして前記
第2導電型領域上の酸化膜にコンタクト用窓t−あける
と同時に#コンタクト用窓周縁の酸化膜に傾斜をつける
工程と、前記コンタクト用窓を介して前記第2導電型領
域にW:続する電極並びに配線を形成する工程とを含む
ことを特徴とする半導体装置の製造方法。(1) A step of forming a second conductivity type region surrounding the semiconductor element portion at intervals, and a step of forming the second conductivity type region during the step of forming the second conductivity type region. A step of performing oxygen plasma treatment to make the surface of the oxide film formed on the 8I2 conductivity type region and its periphery water-soluble, and forming a photoresist mask on the surface of the oxide film on the semiconductor substrate to select the oxide film. etching to open a contact window T- in the oxide film on the second conductivity type region, and at the same time slope the oxide film at the periphery of the contact window; A method for manufacturing a semiconductor device, comprising the steps of forming subsequent electrodes and wiring.
基板の前記半導体素子部を間隔をおいて囲む第2導電型
領域と鋏第2導電製領域を間隔【おいて囲む第2導電型
ガムドll yグを形成する工程と、前記第2導電盟領
域並びに前記ガードリング形成工程中に生成する酸化膜
のうち前記ガードリングとそのM4縁上の酸化膜の表面
を親水性にする酸素プラズマ処理を行う工程と、前記半
導体基板上の酸化膜の表i1にホトレジストのマスクを
形成し、)!trie酸化膜を選択エツチングして前記
ガードリング上の酸化膜にコンタクト用窓をあけると同
時に該コンタクト用窓周縁の酸化膜に傾斜上つける工程
と、前記コンタクト用窓を介して前記ガードリングに4
i!続する電極並びに配線を形成する工程とを含むこと
t−特徴とする半導体装置の製造方法。(2) A second conductivity type region that surrounds the semiconductor element part of the first conductivity type conductor substrate on which the semiconductor element part is formed at a distance, and a second conductivity type region that surrounds the scissors second conductivity region at a distance. Oxygen that makes the surface of the oxide film on the guard ring and its M4 edge hydrophilic among the oxide films formed during the step of forming the molded gum dog and the second conductive region and the guard ring forming step. A step of performing plasma treatment and forming a photoresist mask on the surface i1 of the oxide film on the semiconductor substrate, )! A step of selectively etching the trie oxide film to form a contact window in the oxide film on the guard ring and at the same time attaching the oxide film at the periphery of the contact window upwardly;
i! A method of manufacturing a semiconductor device, comprising the step of forming subsequent electrodes and wiring.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1612782A JPS58134466A (en) | 1982-02-03 | 1982-02-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1612782A JPS58134466A (en) | 1982-02-03 | 1982-02-03 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58134466A true JPS58134466A (en) | 1983-08-10 |
Family
ID=11907829
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1612782A Pending JPS58134466A (en) | 1982-02-03 | 1982-02-03 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58134466A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0234269A2 (en) * | 1986-01-24 | 1987-09-02 | SGS MICROELETTRONICA S.p.A. | High voltage semiconductor integrated circuit |
JP2005150190A (en) * | 2003-11-12 | 2005-06-09 | Mitsubishi Electric Corp | Field effect transistor |
-
1982
- 1982-02-03 JP JP1612782A patent/JPS58134466A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0234269A2 (en) * | 1986-01-24 | 1987-09-02 | SGS MICROELETTRONICA S.p.A. | High voltage semiconductor integrated circuit |
JP2005150190A (en) * | 2003-11-12 | 2005-06-09 | Mitsubishi Electric Corp | Field effect transistor |
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