JPH0450736B2 - - Google Patents
Info
- Publication number
- JPH0450736B2 JPH0450736B2 JP7945988A JP7945988A JPH0450736B2 JP H0450736 B2 JPH0450736 B2 JP H0450736B2 JP 7945988 A JP7945988 A JP 7945988A JP 7945988 A JP7945988 A JP 7945988A JP H0450736 B2 JPH0450736 B2 JP H0450736B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- layer
- voltage
- main circuit
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005530 etching Methods 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Weting (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device.
近年、半導体装置の加工方法の中で、電気化学
現像を用いたエツチング方法が注目をあびてい
る。その技術は通常、初めに、Ｐ型の半導体基板
の片面に、拡散法、またはエピタキシー成長法な
どを用いてＮ型半導体層を設け、PN接合を形成
した構造の基板を用意する。ついで、Ｎ型半導体
をエツチング溶液中において、これに陽極酸化反
応によつて酸化シリコンの膜が生成する程度に正
の電圧を加え、エツチングがＰ型半導体面からＮ
型半導体に到つた時に、そのPN接合の界面近傍
に酸化膜を形成せしめ、エツチングをその界面で
停止させるという方法により行われている。しか
し、そのためには外部から電圧を供給する必要が
生じる。第２図に従来用いられてきた基板を示
す。図において、従来は、半導体ウエフアー１１
における主回路部分１２に設けた片面周辺部を取
り巻くように、円形に高濃度拡散領域１３、つま
り、低抵抗層を設けることにより、外部配線との
接触抵抗を小さく保つたまま、導通がとれる様に
し、そこに外から所望の電圧よよび電流を定電圧
電源より供給出来る様に工夫していた。
In recent years, among methods for processing semiconductor devices, etching methods using electrochemical development have been attracting attention. In this technique, first, an N-type semiconductor layer is provided on one side of a P-type semiconductor substrate using a diffusion method, an epitaxial growth method, or the like, thereby preparing a substrate having a structure in which a PN junction is formed. Next, the N-type semiconductor is placed in an etching solution, and a positive voltage is applied to it to the extent that a silicon oxide film is generated by an anodic oxidation reaction.
When a type semiconductor is reached, an oxide film is formed near the interface of the PN junction, and etching is stopped at that interface. However, this requires an external voltage supply. FIG. 2 shows a conventionally used substrate. In the figure, conventionally, a semiconductor wafer 11
By providing a circular high-concentration diffusion region 13, that is, a low-resistance layer, so as to surround the periphery of one side of the main circuit portion 12 in the main circuit portion 12, conduction can be maintained while keeping the contact resistance with external wiring small. It was devised so that the desired voltage and current could be supplied from the outside from a constant voltage power supply.
エツチング溶液中でのシリコン酸化膜の生成
は、半導体にかかる電位によつて制御されるの
で、以上述べた構造においては、円周部分以外の
シリコン部分の電気抵抗は、円周部に比べてかな
り高いために、円周部から中心部に向うにしたが
つて、外部から供給される電圧とは異なつた電圧
となり、かつ、エツチングの進行とともにシリコ
ンの膜厚は減少して行くために、さらに抵抗値は
大きな値に増加し、外部電源による設定電圧値と
各チツプ部分における電圧値の差異は顕著とな
り、中心部分はエツチングがPN接合界面に到達
する以前に、酸化膜が形成され始め、本来ならエ
ツチングされるべきシリコンの部分がエツチング
されずに残つてしまい、正確なエツチングが行え
ないという、深刻な問題点があつた。また主回路
形成部分１２のある面に導電体層を設けると主回
路の形成に影響を与えるなどの問題があつた。
Since the formation of a silicon oxide film in an etching solution is controlled by the potential applied to the semiconductor, in the structure described above, the electrical resistance of the silicon portion other than the circumferential portion is considerably higher than that of the circumferential portion. Because of this, the voltage becomes different from the externally supplied voltage as you move from the circumference to the center, and as the silicon film thickness decreases as etching progresses, the resistance further increases. The value increases to a large value, and the difference between the set voltage value by the external power supply and the voltage value at each chip part becomes remarkable, and in the central part, an oxide film begins to form before the etching reaches the PN junction interface, and the There was a serious problem in that the silicon portion that should be etched remained unetched, making it impossible to perform accurate etching. Further, there was a problem that if a conductive layer was provided on a certain surface of the main circuit forming portion 12, it would affect the formation of the main circuit.
本発明は、上記、従来の問題点であつた箇所を
完全に克服し、確実に、シリコンのエツチングが
遂行でき尚かつ、主回路の形成に影響を与えない
方法を提供することにある。 The object of the present invention is to provide a method that completely overcomes the above-mentioned conventional problems and can reliably perform silicon etching without affecting the formation of the main circuit.
〔課題を解決するための手段〕
上記目的を達成するため、本発明の半導体装置
の製造方法においては、電気化学エツチングを用
いた半導体装置の製造方法において、主電子回路
を形成すべき基板面とは反対の面に形成する構造
物の少なくとも近傍まで低抵抗層を設け、この低
抵抗層を電気化学エツチングのための電極に接続
するものである。[Means for Solving the Problems] In order to achieve the above object, in the method of manufacturing a semiconductor device of the present invention, in the method of manufacturing a semiconductor device using electrochemical etching, the surface of the substrate on which the main electronic circuit is to be formed and In this method, a low resistance layer is provided at least close to the structure formed on the opposite surface, and this low resistance layer is connected to an electrode for electrochemical etching.
本発明の電気化学エツチング法は、主回路形成
部分以外の部分に、電気化学エツチングに必要と
される電圧および電流を供給するための、低抵抗
回路を主回路の形成してある面とは逆の面に形成
し、これを外部電源と接続することにより、電気
化学エツチングによつて取り除こうとする部分の
電位を、精密に制御することができるようにして
いる。こうすることにより、エツチングは完全に
行われ、必要とされる任意の形状のエツチングを
施工することが可能である。また、主回路の作製
に制限を与えない。
The electrochemical etching method of the present invention involves forming a low-resistance circuit opposite to the surface on which the main circuit is formed, in order to supply the voltage and current required for electrochemical etching to parts other than the main circuit formation part. By connecting this to an external power source, it is possible to precisely control the potential of the portion to be removed by electrochemical etching. By doing this, the etching is completed and it is possible to perform etching in any desired shape. Further, there is no restriction on the production of the main circuit.
以下の図面に基づいて、本発明に係わる方法の
最適な実施例を説明する。
A preferred embodiment of the method according to the invention will be explained based on the following drawings.
第１図ａ，ｂはそれぞれ基板１の表面と、裏面
とを示している。２は主電子回路が設けられる基
板１の表面の主回路部分である。各チツプ３の周
辺に１ミリメートル程度のスクライブ領域を設
け、そこにイオンインプランテイシヨン、もしく
は、拡散法により表面のＰ型半導体層面にはP+
拡散層によるP+配線４を、裏面のＮ型半導体層
面にはN+拡散層によるN+配線５を形成する。そ
の後、基板１の表面にSiO2などの保護層を設け
る。この導電路の形成は、各半導体チツプに同じ
様に電圧が加わることを促す働きと、外部との電
気回路接続の際に起こる接触抵抗を激減させる働
きとを持つている。その後、外部に設けた定電圧
電源に接続し、Ｎ型半導体層から成るエツチング
によつて作製しようとする構造物を、その表面に
おいて陽極酸化が起こり、SiO2が生成する程度
に、プラスの電位になるようにN+配線５を通じ
て設定する、一方、エツチングによつて切り取ら
れる、Ｐ型半導体層部分が通常シリコン基板に対
して外から何も電圧を加えないときに、Siの異方
性エツチングが継続して起こる、自然平衡電位よ
りもマイナス側になるように、P+配線４を通じ
て設定し、エチレンジアミン系、KOH系、およ
びヒドラジン系等のシリコン異方性エツチングが
可能な溶液に浸し、90度付近に加温してエツチン
グを行う。通常Ｐ型半導体層からエツチングが行
われるが、配線の線材としてアルミのような金属
を用いると、それが異方性エツチングの進行中に
サイドエツチングされ、導体としての働きを失
う。又それらのとけた金属は、エツチング液を汚
染し、エツチング液の寿命を著しく短くする。と
ころが、拡散層を伝導層として用い、表面を
SiO2またはエツチング液によつて侵されない金
属にて保護しておけば、上記欠点を克服すること
が可能である。尚、この様に、導電体層を設ける
と、従来の方法では円形にシリコンウエフアーの
外周部を１センチメートル程度N+層の形成に費
やしていたため、チツプの有効作製面積が、極端
に下がることが認められたが、それを著しく改良
することも可能である。 Figures 1a and 1b show the front and back sides of the substrate 1, respectively. Reference numeral 2 denotes a main circuit portion on the surface of the substrate 1 where a main electronic circuit is provided. A scribe area of about 1 mm is provided around each chip 3, and ion implantation or diffusion is performed to form a scribe area on the surface of the P-type semiconductor layer .
A P + wiring 4 is formed by a diffusion layer, and an N + wiring 5 is formed by an N + diffusion layer on the N type semiconductor layer surface on the back side. After that, a protective layer such as SiO 2 is provided on the surface of the substrate 1. The formation of this conductive path has the function of promoting the application of voltage to each semiconductor chip in the same way, and the function of drastically reducing the contact resistance that occurs when connecting an external electrical circuit. After that, it is connected to an external constant voltage power supply, and the structure to be fabricated by etching consisting of the N-type semiconductor layer is heated to a positive potential to the extent that anodic oxidation occurs on the surface and SiO 2 is generated. On the other hand, the P - type semiconductor layer portion that is cut out by etching is normally etched by anisotropic etching of Si when no external voltage is applied to the silicon substrate. Set it through the P + wiring 4 so that it is on the negative side of the natural equilibrium potential, where the potential continues to occur, and soak it in a solution capable of silicon anisotropic etching such as ethylenediamine, KOH, and hydrazine. Etching is performed by heating the material to around 30°F. Etching is normally performed from the P-type semiconductor layer, but if a metal such as aluminum is used as a wiring wire, it will be side-etched during anisotropic etching and lose its function as a conductor. Also, those melted metals contaminate the etching solution, significantly shortening the life of the etching solution. However, when the diffusion layer is used as a conductive layer, the surface becomes
The above-mentioned drawbacks can be overcome by protecting it with SiO 2 or a metal that is not attacked by the etching solution. In addition, when a conductor layer is provided in this way, the effective manufacturing area of the chip is extremely reduced, as in the conventional method, approximately 1 cm of the outer circumference of the circular silicon wafer is used to form the N + layer. However, it is possible to improve it significantly.
図においてはスクライブ領域以外の周辺にも導
電体層が設けられているが外部電源に対して接続
できる場所さえ設ければその部分はなくても構わ
ない。 In the figure, a conductor layer is also provided around the area other than the scribe area, but that part may be omitted as long as a place that can be connected to an external power source is provided.
以上説明したように、本発明によれば、シリコ
ンウエフアーのどの部分にも外から加えた電圧
が、均一にかかる様に制御できるので、エツチン
グによる薄膜形成は、非常に微細な形であつて
も、すべての部分に対して極めて良好であり、全
てのチツプを製品として用いることが可能とな
る。またこの発明による配線の位置が主回路の配
置と干渉することもない。また、片側だけに配線
を施すので、工程の簡略化が期待できるなどの効
果もある。
As explained above, according to the present invention, the voltage applied from the outside can be controlled so as to be uniformly applied to any part of the silicon wafer, so that thin films can be formed by etching in very fine shapes. Also, all parts are extremely good, and all chips can be used as products. Further, the position of the wiring according to the present invention does not interfere with the arrangement of the main circuit. Furthermore, since wiring is applied only to one side, it is possible to expect the process to be simplified.
第１図ａは本発明による電気化学エツチングに
使用される半導体基板の平面図、ｂは同底面図、
第２図は従来電気化学エツチング使用されていた
半導体基板の平面図である。
１……基板、２……主回路部分、３……チツ
プ、４……P+配線、５……N+配線。
FIG. 1a is a plan view of a semiconductor substrate used for electrochemical etching according to the present invention, and FIG. 1b is a bottom view of the same.
FIG. 2 is a plan view of a semiconductor substrate conventionally subjected to electrochemical etching. 1... Board, 2... Main circuit part, 3... Chip, 4... P + wiring, 5... N + wiring.
Claims (1)
造方法において、主電子回路を形成すべき基板面
とは反対の面に形成する構造物の少なくとも近傍
まで低抵抗層を設け、この低抵抗層を電気化学エ
ツチングのための電極に接続することを特徴とす
る半導体装置の製造方法。1. In a method of manufacturing a semiconductor device using electrochemical etching, a low resistance layer is provided at least close to a structure to be formed on the surface opposite to the substrate surface on which the main electronic circuit is formed, and this low resistance layer is etched by electrochemical etching. A method for manufacturing a semiconductor device, which comprises connecting to an electrode for etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7945988A JPH01251618A (en) | 1988-03-30 | 1988-03-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7945988A JPH01251618A (en) | 1988-03-30 | 1988-03-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01251618A JPH01251618A (en) | 1989-10-06 |
| JPH0450736B2 true JPH0450736B2 (en) | 1992-08-17 |
Family
ID=13690465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7945988A Granted JPH01251618A (en) | 1988-03-30 | 1988-03-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01251618A (en) |
-
1988
- 1988-03-30 JP JP7945988A patent/JPH01251618A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01251618A (en) | 1989-10-06 |
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