JPH0450620B2 - - Google Patents

Info

Publication number
JPH0450620B2
JPH0450620B2 JP60258212A JP25821285A JPH0450620B2 JP H0450620 B2 JPH0450620 B2 JP H0450620B2 JP 60258212 A JP60258212 A JP 60258212A JP 25821285 A JP25821285 A JP 25821285A JP H0450620 B2 JPH0450620 B2 JP H0450620B2
Authority
JP
Japan
Prior art keywords
prefix
virtual machine
address
instruction
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60258212A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62117046A (ja
Inventor
Saburo Kaneda
Kazuaki Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60258212A priority Critical patent/JPS62117046A/ja
Publication of JPS62117046A publication Critical patent/JPS62117046A/ja
Publication of JPH0450620B2 publication Critical patent/JPH0450620B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
JP60258212A 1985-11-18 1985-11-18 プレフイクス制御方式 Granted JPS62117046A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60258212A JPS62117046A (ja) 1985-11-18 1985-11-18 プレフイクス制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60258212A JPS62117046A (ja) 1985-11-18 1985-11-18 プレフイクス制御方式

Publications (2)

Publication Number Publication Date
JPS62117046A JPS62117046A (ja) 1987-05-28
JPH0450620B2 true JPH0450620B2 (en, 2012) 1992-08-14

Family

ID=17317073

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60258212A Granted JPS62117046A (ja) 1985-11-18 1985-11-18 プレフイクス制御方式

Country Status (1)

Country Link
JP (1) JPS62117046A (en, 2012)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0690687B2 (ja) * 1987-06-19 1994-11-14 富士通株式会社 アドレス変換バッファ制御方式

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57181489A (en) * 1981-04-30 1982-11-08 Nippon Telegr & Teleph Corp <Ntt> Information processor

Also Published As

Publication number Publication date
JPS62117046A (ja) 1987-05-28

Similar Documents

Publication Publication Date Title
US4347565A (en) Address control system for software simulation
US4520441A (en) Data processing system
KR910001447B1 (ko) 가상계산기능 시스템용 주기억장치 억세스 제어시스템
JPH06231043A (ja) 仮想記憶システムにおけるデータ転送装置及びその方法
US5226132A (en) Multiple virtual addressing using/comparing translation pairs of addresses comprising a space address and an origin address (sto) while using space registers as storage devices for a data processing system
US5280592A (en) Domain interlock
US5051894A (en) Apparatus and method for address translation of non-aligned double word virtual addresses
JPH0192856A (ja) アクセス及び欠陥論理信号を用いて主メモリユニットを保護する装置及び方法
JPH0450620B2 (en, 2012)
JP2535086B2 (ja) リング削減ロジック装置
JP3328867B2 (ja) マルチプロセッサ演算装置、および該装置を有するプログラマブルコントローラ
JPS6336012B2 (en, 2012)
JP2570846B2 (ja) 先取り制御ユニット
JPH0412861B2 (en, 2012)
JPS63286944A (ja) アドレス変換バツフア無効化方式
JPS63317860A (ja) アドレス変換バッファ制御方式
JPS6269339A (ja) アドレス変換バツフア方式
JPS6010336B2 (ja) アドレス比較方式
JPH02101552A (ja) アドレス変換バッファ処理方式
EP0550290A2 (en) CPU register array
JPH0766352B2 (ja) 仮想計算機システム
JPS63311438A (ja) ストア命令不一致制御回路
JPH0157374B2 (en, 2012)
Neumann Disk-based program swapping in 8080-based microcomputers
JPH03142546A (ja) アドレス変換装置