JPH0449674B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an electronic watch equipped with a data memory capable of storing data such as telephone numbers, addresses, schedules, and the like.

[Background of the Invention] In recent years, electronic watches have become more multi-functional, and data such as telephone numbers, addresses, schedules, etc. are stored in advance in a data memory using a data input means such as a switch, and the contents of the data memory can be changed as needed. A system is known in which the images are sequentially read out and displayed.

However, this type of data is only stored in the data memory sequentially according to the input order and displayed sequentially, so when searching for desired data from among the sequentially displayed data, it is difficult to display the desired data. It is necessary to carefully check each piece of data to determine whether it is the desired data, which is troublesome and has the disadvantage that the data may be overlooked or misunderstood.

Therefore, it is conceivable to sequentially read and display the contents of the memory in a predetermined order as described in Japanese Patent Application Laid-Open No. 59-3387, but this method In such cases, it is necessary to compare all data stored in memory, detect data in a predetermined order, and display it. The disadvantage is that it takes a relatively long time to actually display the image.

However, in order to shorten the time required for the comparison operation, it is possible to perform the comparison operation using an extremely high frequency clock signal, but electronic watches usually have an oscillator for timekeeping operation. Using an oscillator with a higher oscillation frequency in addition to this oscillator has the disadvantage of not only increasing the size of the device but also increasing cost. It is also possible to increase the oscillation frequency of the oscillator for timekeeping operation and use this oscillation signal for comparison, but in that case, the above-mentioned timekeeping operation would require dividing the high oscillation frequency to obtain the timekeeping signal. First, there are drawbacks such as increased power consumption, shortened battery life, and the need to use a multistage frequency dividing circuit.

[Object of the Invention] This invention was made in view of the above-mentioned circumstances, and its purpose is to read and display desired data from a data memory that stores a large amount of input data. It is an object of the present invention to provide an electronic timepiece equipped with a data memory that can easily, reliably, and quickly carry out the work when the user wants to perform the work.

[Summary of the Invention] In order to achieve the above-mentioned object, the present invention edits the input data and the data already stored in the memory in a predetermined order when writing the input data in the memory. By storing the data in the memory, the data can be displayed in a predetermined order by simply displaying the data in the memory sequentially. By using the clock signal from the oscillation circuit for timekeeping, a dedicated oscillator is not required, and since this increases the editing time, it is clearly displayed that editing is in progress, and when editing is completed. The main point is that the above-mentioned explicit display is terminated to notify that storage of the input data has been completed.

[Example] The present invention will be specifically described below based on an example shown in the drawings. FIG. 1 is a top view of an electronic wristwatch with data memory, in which push button switches S ₁ to _{S 4} are provided on both sides of the watch case, and a liquid crystal display device 1 is provided on the top surface, and a push button switch S is provided below it. _Five ,
_S6 is provided. The functions of the switches S ₁ to S ₆ will be described later.

The liquid crystal display device 1 is constructed as shown in FIG. That is, the liquid crystal display section 1 has a matrix display section 1A having 6 digits (5 x 5 dots per digit) on the upper side, a sub digital display section 1B consisting of a 6-digit Japanese character display on the middle section, and a lower section. In addition to being provided with a main digital display section 1C consisting of a 6-digit day-shaped display, it also has an alarm ON mark 1D, etc.

Next, the circuit configuration of this electronic timepiece will be explained with reference to FIGS. 3 to 5. FIG. 3 is a circuit diagram of the entire electronic timepiece. A reference clock signal constantly outputted from the oscillation circuit 11 is sent to a frequency division/timing signal generation circuit 12. This frequency division/timing signal generation circuit 12 is 1P (pulse)/1S (second)
Counting circuit 1 by outputting a signal (time clock)
3, a display timing signal a is given to the display control section 14, and a timing signal b is given to the data memory circuit section 15 and the switch control section 16. The counting circuit 13 counts the above 1P/1S signal and outputs time data of hours, minutes, seconds, day of the week, year,
This is to obtain the date data of the month and day, and the time and date data obtained thereby are sent to the gate circuit 1.
7 to the display control unit 14 and converted into display data, and then sent to the display device 1 and displayed. Further, the time data obtained by the counting circuit 13 is also sent to the alarm circuit 18. The alarm circuit 18 outputs an alarm signal to the sound part 19 to generate a sound when detecting a match between a preset alarm time and the time data from the counting circuit 13. The alarm time data is sent to the display control unit 14 via the gate circuit 20 and converted into display data, and then sent to the display device 1 and displayed. The data memory circuit section 15 is capable of storing names and telephone numbers, and the data read from the data memory circuit section 15 is sent to the display control section 14 via the gate circuit 21 and converted into display data. Thereafter, it is sent to the display device 1 and displayed. Note that the signal 15a output from the data memory circuit section 15
is a display control signal when the data memory circuit section 15 is selected, which will be described later.
This is the signal input to 4. Switch control section 16
is used to input the switching signal output from the switch unit 22 having the above-mentioned switches S ₁ to _{S 6} corresponding to the operation switch, and in response to this, the time correction signal c and the alarm circuit are sent to the counting circuit 13. It outputs an alarm setting signal d to the data memory circuit section 18, a data setting and readout signal e to the data memory circuit section 15, and a gate control signal f to selectively open each gator circuit 17, 20, and 21. .

FIG. 4 shows the switch section 22 and the switch control section 1.
6 shows the configuration of No. 6 in detail. In the switch unit 22, the switch _S1 is a mode changeover switch, which includes a normal display mode for displaying the contents of the counting circuit 13, a telephone number display mode for displaying the contents of the data memory circuit section 15, and a display mode for displaying the contents of the alarm circuit 18. Switch the alarm time display mode.
Switch S ₂ is the switch that specifies/cancels the data correction (setting) mode in the above normal display mode, telephone number display mode, and alarm time display mode, and switch S ₃ is the switch that specifies or cancels the data correction (setting) mode in the above correction (setting) mode. A digit selection switch that selects the exponent digit, switch S ₄ is an increment switch that increments the contents of the selected digit by +1, and switches S ₅ and S ₆ are used in the above telephone number display mode.
This switch is used to sequentially call each person's phone number stored in the data memory circuit section ₁₅ along with their name.
_S6 is a -1 switch that calls the phone number of the previous person in the opposite direction. The outputs of these switches S ₁ to _{S 6} are then controlled by the switch control section 16.
A pulse signal is output from the corresponding one-shot circuits 23-28. The pulse signal output from the one shot circuit 23 is sent to the mode selection circuit 29. The mode selection circuit 29 selects the normal display mode, telephone number display mode, and alarm time display mode in accordance with the 1 to 3 bits, and selects the signals 29 _a to 2 which are the gate control signals f.
_9c is alternatively output to open the corresponding gate circuits 17, 20, and 21. Further, one output of the mode selection circuit 29 is output from the AND gates 30 to 30.
Of the 40, the 2-bit output is input to AND gates 30-32, the 2-bit output is input to AND gates 33-35, and the 3-bit output is input to AND gates 36-40, respectively. Also,
The pulse signal output from the one-shot circuit 24 is applied to the T input terminal of a trigger flip-flop (T-FF) 41 to invert its output state. The Q output of this T-FF 41 is input to AND gates 30, 33, and 36, respectively. Furthermore, the output pulse of the one-shot circuit 25 is applied to the AND gate 3.
1, 34, 37, the output pulse of the one shot circuit 26 is sent to AND gates 32, 35, 38, and the output pulse of the one shot circuit 27 is sent to AND gate 3.
At 9, the output pulses of the one-shot circuit 28 are input to AND gates 40, respectively. Here, the output of the AND gates 30 to 32 is the time correction signal c
The output _c1 of the AND gate 30 is a signal for enabling time adjustment, the output _c2 of the AND gate 31 is a digit selection signal, and the output _c3 of the AND gate 32 is a correction signal for incrementing the contents of the selected digit. . Similarly, the outputs of AND gates 33 to 35 are the above-mentioned alarm setting signals, the output _d1 of AND gate 33 is a signal to enable alarm time setting, and the output of AND gate 34 is
_d2 is a digit selection signal, and the output _d3 of the AND gate 35 is a setting signal for incrementing the content of the selected digit. The outputs of the AND gates 36 to 40 and the 2-bit output of the mode selection circuit 29 are the data setting and readout signals e, and the 2-bit output _e1 of the mode selection circuit 29 is the data readout signal in the telephone number display mode. , the output e ₂ of the AND gate 36 is a signal that enables the setting of name and telephone number data, the output e ₃ of the AND gate 37 is a digit selection signal, and the output e ₄ of the AND gate 38 is a signal that increments the contents of the selected digit. The output _e5 of the AND gate 39 is a signal for reading data from the data memory in the forward direction, and the output _e6 of the AND gate 40 is a signal for reading data from the data memory in the reverse direction.

Next, referring to FIG. 5, the data memory circuit section 1
The configuration of No. 5 will be explained in detail. A RAM (random access memory) 41 constitutes a data memory and is configured as shown in FIG. That is, each digit address area of the RAM 41 has a character data storage section that can store 6 alpha characters and a numeric data storage section that can store 12 numbers.The character data storage section stores names and numeric data. A telephone number is stored in the storage unit. This RAM41
The row address is specified according to the count value data of the address counter 42, and data writing and reading operations are executed with respect to the specified address. In addition, address counter 4
2 consists of an up/down counter,
When the signal _e5 is inputted through the OR gate 43, it is incremented by +1, and when the signal _e6 is inputted, it is incremented by -1. The data (name and telephone number) read from the RAM 41 is transferred to the buffer 45 via the AND gate 44. In this case, the AND gate 44 is opened by inputting the signals e ₅ and e ₆ via the OR gate 46, and also by inputting the signal e ₁ to the rising edge detection circuit 47, it is output in synchronization with the rising edge. It is opened by inputting a one-shot pulse to the OR gate 46. Batsuhua 45
is capable of storing names and telephone numbers, and has a 6-digit character data storage section 45a for storing names and a 12-digit numerical storage section 45b for storing telephone numbers. The data written in the buffer 45 is then sent to the display memory 1 via the gate circuit 21 and displayed.

On the other hand, the signal e ₂ opens the AND gates 48 to 50, respectively, and the signals e ₄ and
The AND gate 50 outputs the signal _e3 . The output of AND gate 48 is sent to a character data generator 51, and the output of AND gate 49 is sent to a numeric data generator 52. The character data generator 51 sequentially generates alpha alphabet characters "A" to "Z" one by one each time the signal _e4 is input from the AND gate 48, and the numeric data generator 52 receives the signal from the AND gate 49. Every time e ₄ is input, the numbers "0" to "9" are generated one character at a time.
Further, the output of the AND gate 50 is output from the digit selection circuit 53.
sent to. This digit selection circuit 53 is connected to the buffer 45.
It selects the digit of , and every time the signal _e3 is input from the AND gate 50, it sequentially outputs the digit selection signal.
Corresponding AND gates 54a ₁ to 54a ₆ , 54b ₁ to
54b ₁₂ is opened alternatively. and gate 5
_4a1 to _54a6 are provided corresponding to each digit in the character data storage section 45a of the buffer 45, and are used to transfer the character data output from the character data generator 51 to the corresponding digit of the buffer 45. It is. Moreover, the AND gates 54b ₁ to 54b ₁₂ are
It is provided corresponding to each digit in the numeric data storage section 45b of the buffer 45, and the numeric data output from the numeric data generator 52 is stored in the buffer 45.
5. The contents of the buffer 45 are supplied to a no-data detection circuit 55, an erroneous data detection circuit 56, and an AND gate 57.
It is also supplied to the comparator circuit 58 via. The data absence detection circuit 55 detects the presence or absence of data corresponding to each digit of the buffer 45, and sends out a detection signal corresponding to each digit of the buffer 45 as the display control signal 15a. In this case, when the display control signal 15a is given to the display control section 14,
The display control section 14 is configured to display a hyphen on the display digit corresponding to the digit without data in the numeric data storage section 45b of the buffer 45 in the sub digital display section 1B and the main digital display section 1C of the display device 1. . Further, the data absence detection circuit 55 outputs a signal G when it detects that there is no data in all digits of the buffer 45. This signal G is a signal that opens the AND gate 59.
A signal e ₅ is output from the AND gate 59 and applied to the clear terminal of the address counter 42 via the OR gate 60. Further, the erroneous data detection circuit 56
This is to detect whether the data written in the buffer 45 is in a predetermined format. In other words, it detects incorrect data that deviates from the specified format, such as when a Japanese phone number starts with the number "0" or not, or when all six letters of a name are "A", etc. When erroneous data is detected, the level goes high (logical value “1”).
A signal is outputted and applied to the AND gate 57 via the inverter 61. On the other hand, the signal e ₂ is also given to the falling edge detection circuit 62. This fall detection circuit 62 outputs a one shot pulse in synchronization with the fall of the signal _e2 , and the output pulse is sent to the address counter 42 via an OR gate 60.
and the S input terminal of an SR flip-flop (SR-FF) 63. The Q output of SR-FF63 is AND gate 6
4 is opened and a 15 Hz signal is output from the AND gate 64. The 16Hz signal output from this AND gate 64 is given to the AND gate counter 42 via the OR gate 43, and its contents are +
It is incremented by 1 and is given to the RAM 41 as a read command signal and to the comparator circuit 58 as an operation command signal. The comparator circuit 58 compares the data sequentially read out from the RAM 41 and the data from the buffer 45 in accordance with the 16 Hz signal, and executes the comparison operation in accordance with the 16 Hz signal. In this case, the comparison circuit 58
It compares the 6 characters of the name from buffer 41 with the 6 characters of the name from buffer 45 and rearranges the contents of RAM 41 so that the names are in alphabetical order, giving top priority to the initial letter ``A''. In addition to sorting the names in alphabetical order from names with "Z" to names with "Z", edits are performed to sort names with the same initial letter in alphabetical order from "A" to "Z" starting from the second letter. I'm starting to do that. Therefore, if the data from the buffer 45 is lower in alphabetical order than the data from the RAM 41, the comparison circuit 58 transfers the data from the RAM 41 as is to the RAM 41, but when it first detects that the data is higher than the data from the RAM 41, Batsuhua 45
The data from is transferred to RAM45. On the other hand, when the contents of the address counter 42 reach the final address, the end signal E indicating the end of editing is sent to SR.
-Given to the R input terminal of FF63. On the other hand, the 16 Hz signal output from the AND gate 64 is sent as the display control signal 15a and sent to the display control section 14. In this case, the display control unit 14
is adapted to cause the matrix display section 1A of the display device 1 to display a predetermined display indicating that the editing is in progress. Next, the operation of the above embodiment will be explained. FIG. 7 shows the display state that changes as the switch _S1 is operated. First, mode selection circuit 2
Since the gate circuit 17 is opened while the signal 29a is being outputted from the counter 9, the contents of the counting circuit 13 are sent to the display device 1 and displayed. In this way, in the normal display mode (see FIG. 7A) in which the contents of the counting circuit 13 are displayed on the display device 1, when the switch _S1 is operated once, the signal 29b is sent from the mode selection circuit 29. is output and the gate circuit 20 is opened, so that a telephone number display mode is entered in which the data read from the data memory circuit section 15 is displayed. That is, in this telephone number display mode, the signal _e1 is output from the switch control section 16 and inputted to the data memory circuit section 15.
A one-shot pulse is output from the rising edge detection circuit 47 in response to the rising edge of the signal _e1 , and the AND gate 44 is opened. As a result, the data from the RAM 41 specified by the address counter 42 is written into the buffer 45, and then sent to the display device 1 via the gate circuit 21 and displayed, for example, as shown in FIG. 7B. . in this case,
The 6-character name is displayed in alphanumeric form on the 6-digit matrix display section 1A, and the telephone number is displayed on the sub-digital display section 1B and the main digital display section 1C, totaling 12 characters.
Digitally displayed in digits. In this case, if the phone number of the person you want to know is not displayed, operate Switch _S5 or _S6 . In this case, since names are stored in the RAM 41 in alphabetical order, it is determined whether the name currently displayed is stored after or before this person, and if it is later, the switch _S5 , If it is before, operate Switch S ₆ . Therefore, in the phone number display mode, the switch
When S ₅ and S ₆ are operated, the switch control unit 16 outputs signals e ₅ and e ₆ corresponding to the operated switch, increments the contents of the address counter 42 by +1 or -1, and opens the AND gate 44. let
As a result, the next person's phone number or the previous person's phone number is read out from the RAM 41 and displayed. In this way, each time you operate switches S ₅ and S ₆ ,
The address in RAM 41 is updated by +1 or -1, and the next or previous person's phone number is displayed in sequence. Operate switches _S5 and _S6 until the desired person's name is displayed. Bye. When the next address of RAM 41 is specified by operating switch _S5 , if an address in which no data is stored (an empty address) is specified first, the no-data detection circuit 55 detects all digits of data. It detects the absence, and outputs the signal 15a as well as the signal G accordingly. As a result, in the display state in this case, as shown in FIG. 8A, all digits (12 digits in total) of the sub and main digital display sections 1B and 1C are displayed with a hyphen on. At the same time, the AND gate 59 is opened by the output of the signal G.
When switch _S5 is operated one more time in this state, the address counter 42 is cleared and its contents become "00000", and as a result, the RAM 41
The start address of is now specified. Therefore, as mentioned above, the first page is displayed after all display digits are displayed with a hyphen (empty page display), so the empty page display above becomes a separator between the first page and the last page. , the boundaries can be made clear.

Next, in the telephone number display mode, when the switch S ₁ is operated once, the mode selection circuit 29 outputs the signal 29c and the gate circuit 20 is opened, so that the alarm circuit 18 outputs the alarm time and the meaning of that time. The message data will be read out and displayed. FIG. 7C shows the display state in this alarm time display mode. Therefore, you can further switch in this alarm time display mode.
When _S1 is operated once, the normal display mode as shown in FIG. 7A is restored.

Next, the operation when newly setting or modifying a telephone number will be explained. In this case, in the telephone number display mode, the switch _S2 is operated to set the T-FF 41 of the switch control section 16. As a result, the switch control section 16 outputs the signal _e2 , so that the data memory circuit section 15
, AND gates 48-50 are opened, respectively. In this state, when the switch _S3 is first operated, the contents of the digit selection circuit ₅₃ are sequentially updated by the signal _e3 output every time the switch S3 is operated. After selecting the digit to be set in this way,
When the switch _S4 is operated, the signals output every time the switch _S4 is operated are input to the character data generator 51 and the numeric data generator 52, respectively. If the 1st to 6th digits of the buffer 45 are currently selected, the letters "A" to "Z" are written into the selected digits one by one in alphabetical order each time switch S ₄ is operated. When the 7th to 18th digits are selected, the numbers "0" to "9" are written into the selected digits one by one each time the switch _S4 is operated. In this case, the data written in the buffer 45 is displayed sequentially, so the user only needs to visually read the displayed contents and operate the switch _S4 until the desired character or numerical data is displayed. The data thus written into the buffer 45 is sent to the data absence detection circuit 55, and the presence or absence of data is detected. As a result, a signal 15a corresponding to the no-data digit is output and sent to the display control section 14. If a telephone number is currently being written and the number up to the second digit from the end has not been set, a hyphen is displayed in the display digit corresponding to the digit without data, as shown in FIG. 8B. This confirms that the remaining two digits should be set. By the way, before a telephone number is set in the buffer 45, hyphens are displayed in all the display digits of each digital display, similar to the empty page display in FIG. 8A, so the number of digits that can be set and The position of the digit becomes clear, and it is extremely useful when setting data by dividing it at a certain point like a telephone number, or when setting data by dividing it at a predetermined digit so that it can be displayed easily later. becomes.

When the data setting for the buffer 45 is completed, the switch _S2 is operated once.
Then, the output state of T-FF41 is reversed and the signal
e ₂ becomes Low level (logical value “0”). As a result, a one-shot pulse is output from the falling edge detection circuit 62, so the address counter 42 is cleared and its contents become "00000", and the RAM
41 start address is specified. At the same time, SR-FF63 is set and AND gate 6 is set.
4 will be opened. Therefore, a 16 Hz signal is output from the AND gate 64 and input to the RAM 41, address counter 42, and comparison circuit 58, respectively.
As a result, the comparison circuit 58 compares the data sequentially read from the top address of the RAM 41 with the buffer 4.
The data from No. 5 are sequentially compared, and an editing operation is executed to rearrange the contents of the RAM 41 so that the names are in alphabetical order according to the comparison results.
As a result, the contents of the RAM 41 are sorted in order from names with the initial letter "A" to names with the initial letter "Z," and even names with the same initial letter are sorted starting from the second letter. Sorted in alphabetical order. That is, RAM41
is edited every time new data is set. While such editing is being performed, the 16Hz signal output from the AND gate 64 is given to the display control section 14, so that the matrix display section 1A of the display device 1 displays the image shown in FIG. As shown, for example, "SET-A" is displayed. In this case, the alphanumeric characters after the hyphen are displayed in the order of "A" to "Z" according to the 16 Hz signal. This display makes it clear that editing is currently in progress. Therefore, during editing,
When the contents of the address counter 42 become the final address of the RAM 41 and the end signal E is output,
Since the SR-FF 63 is reset, the above-described editing operation is accordingly stopped, and the indication that editing is in progress is also stopped.

By the way, before the above-described editing operation is executed, the erroneous data detection circuit 56 determines whether the data written in the buffer 45 conforms to a predetermined format set in advance. As a result, when it is detected that the data conforms to the predetermined format, its output becomes "0", and therefore the output of the inverter 61 becomes "1", and the AND gate 57 is opened, so that the buffer 45 The data written in is input to the comparison circuit 58, and written to the RAM 41 by the above-described editing operation. On the other hand, when it is detected that the data is incorrect, the output becomes "1" and the AND gate 57 is closed. is not written and is ignored.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be modified and applied in various ways without departing from the scope of the present invention. For example, in the above embodiment, a telephone number is stored in the data memory, but the data may be an address, a schedule, etc., and the data is arbitrary. In addition, the data input means is not limited to a push button switch; for example, if you input arbitrary characters by hand while touching the touch switch formed on the surface of the watch glass with your finger, the data will be recognized and converted into input data. It's okay.

[Effects of the Invention] As explained in detail above, the present invention edits the input data and the data already stored in the memory in a predetermined order when storing the input data in the memory. When displaying data by storing it in a memory, the data can be displayed in a predetermined order by simply sequentially displaying the data in the memory, so desired data can be quickly found. In addition, since the above editing uses a signal from an oscillator to obtain time information, there is no need for a dedicated oscillator for editing. Since the data is switched and displayed to clearly indicate that it is being edited, it is not only immediately clear that editing is in progress, but also when the display ends, the input data is stored in memory and the editing is completed, and the next input data is immediately displayed. This has the effect of allowing you to start inputting information.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention, and FIG. 1 is a top view of an electronic watch equipped with a data memory;
2 is a block diagram of the display device 1 shown in FIG. 1, FIG. 3 is a block circuit diagram of this electronic timepiece, and FIG. 4 is a block diagram of the switch section 22 and switch control section 16 shown in FIG. 3. , FIG. 5 is a configuration diagram of the data memory circuit section 15 shown in FIG. 3, FIG. 6 is a configuration diagram of the RAM 41 shown in FIG. 5, and _FIGS . Display state diagram that changes accordingly, No. 8
Figures A and B are hyphen on display state diagrams. 1... Display device, 13... Counting circuit, 14
...Display control section, 15...Data memory circuit section,
58... Comparison circuit.

Claims (1)

[Claims] 1. An oscillation circuit that outputs a reference clock signal, a time clock means that obtains time information by counting the reference clock signal output from the oscillation circuit, and a display that displays the time information obtained by the time clock means. a memory means for storing a large number of character data consisting of a plurality of character data and numeric data; a display switching means for sequentially switching and displaying the large number of character data stored in the memory means on the display means; a delimiter display control means for displaying delimiters instead of the character data after the character data stored in the memory means is displayed by the display switching means; data input means for inputting new character data to be stored in the memory means during display; and a data input means operated after the new character data is input by the data input means. a switch means, the operation of which is started by the operation of the switch means, and based on the reference clock signal output from the oscillation circuit, the new character data and the character data stored in the memory means; editing means for comparing and editing both character data in a predetermined order and storing it in the memory means; and a reference clock signal outputted from the oscillation circuit while editing by the editing means a clearing means for displaying a predetermined display on the display device based on the display device to clearly indicate that editing is being performed by the editing means; and a clearing means for stopping displaying by the clearing means when editing by the editing means is completed. An electronic timepiece equipped with a data memory, characterized in that it is equipped with a stop means.