JP2524130Y2 - Data input device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an electronic organizer, an electronic memo, or an electronic timepiece or a small electronic computer incorporating these functions.

[Prior art and its problems]

2. Description of the Related Art Conventionally, there has been known an electronic device in which, for example, a telephone number, name data, schedule data, and the like are stored in a memory, and data is read from the memory as needed and displayed on a display device.

In this type of electronic device, data input to and stored in the memory is input using a keyboard. The keyboard includes numeric keys, alphabet keys, kana character keys, and the like. Have been.

On the other hand, if a large number of keys are provided, the size of the apparatus itself becomes large. Therefore, data is sequentially set by a key for selecting a digit and a setting key for the selected digit, and desired data is set. In this case, a so-called two-key select-and-set method of selecting the next digit and setting new data is also known.

However, in the above-mentioned select and set method, when the number of data set by the setting switch is large, there is a disadvantage that the operation is troublesome and a long time is required. For example, if numeric data of 0-9, 26-letter alphabet data, and 50 kana characters are sequentially set by the setting key for the selected digit, the setting key may be operated up to 86 times at the maximum. And was extremely inconvenient.

[Purpose of the invention]

The present invention has been made in view of the above conventional problems,
It is an object of the present invention to provide a data input device that can be set by a very simple operation even when there are many types of data that can be set in a data setting operation in data input.

[Points of the invention]

In order to achieve the above object, the present invention selects an arbitrary set of data from a set of data stored in data storage means and reads out the set of data from the selected set of data. , Data can be input to the position selected by the position selecting means.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a data input device according to an embodiment of the present invention.

As shown in FIG. 1, a switch S ₃ constituting the position selecting means for selecting a position for inputting data, alphabet pattern generating circuit 12 constituting the data storage means for storing a set of respective different data , A number pattern generating circuit 13, a kana character pattern generating circuit 14, and a switch constituting data selecting means for selecting an arbitrary data set from among the data sets stored in the alphabet pattern generating circuit 12, etc. S ₁ and switch
And S _2, reads the data sequentially from among a set of data selected by the switches S _1, S _2, input for inputting the read data to the selected position by said switch S ₃ and a switch S ₄ constituting the means. Hereinafter, these configurations will be described in detail. RAM2 is a random access memory capable of storing many pages of telephone memo data including (name, telephone number) or schedule data including (time, memo) in page units (one page is composed of 21 characters). Character codes such as the telephone memo data and the schedule data, which are composed of alphanumeric and kana characters, are stored.

In addition, the switch control unit 1 responds to the operation of the switches S ₁ and S ₂ so that the +1 signal for adding the page address of RAM 2 to the RAM address control unit 3 and the −1 signal for subtracting the page address of RAM 2 are sent to the RAM address control unit 3. a switch controller that outputs, +1 signal b when only the switch S ₁ is being operated
The, RAM -1 signal p when only the switch S ₂ is operated
Output to the address control unit 3. Also when the switch S ₁ or switch S ₂ is continuously operated for a predetermined time or more, it outputs the respective +1 signal or -1 signal sequentially in the RAM address controller 2 at a predetermined cycle (for example, 8 Hz). Furthermore, when the switch S ₁ and switch S ₂ are simultaneously operated, and outputs the mode switching signal K to the terminal T of the T flip-flop 19 of the data control unit 6.

Next, the RAM address control unit 3 is a circuit that supplies a page address signal PA to the RAM 2 and reads / writes data stored in the RAM 2 in page units.
When the SW is operated, a write signal WE is applied from the one-shot pulse generation circuit 4, and the data stored in the shift register 5 is written to the RAM 2 at the address specified by the page address signal PA. Further, at the time of a read operation when the signal b or p is given, the data of the address specified by the page address signal PA is read from the RAM 2 and stored in the shift register 5. The shift register 5 is a shift register in which 21-bit bit registers 5a to 5u are cascaded, and stores one page of data (consisting of 21 character codes) read from the RAM 2. Each bit shift register 5a to 5u of the shift register 5 is composed respectively 8 bits, gate G ₁ ~G ₂₁ of each of the data input terminals of each bit registers 5a to 5u are data setting section 6
It is connected to, telephone memo data and schedule data set by the user via the data setting unit 6 gate G ₁ ~
Is set in the shift register 5 through a G _21. The data of 21 characters stored in the shift register 5 is always displayed on the display unit 8 composed of a liquid crystal display (LCD) via the display control unit 7.

The display control unit 7 includes a character generator (Charac
Each character code of 21 characters read from the shift register 5 at a predetermined cycle is converted into a predetermined dot pattern (for example, a 5 × 7 dot configuration) using a character generator. And
A scanning signal for performing line-sequential scanning is supplied to the display unit 8 at a predetermined frame period, and an image signal (dot) on a scanning line to which a scanning signal obtained from dot pattern data converted in synchronization with the scanning signal is added. A display signal is output to the display unit 8 to display a character corresponding to the character code stored in the shift register 5 on the display unit 8.

FIG. 2 is a schematic configuration diagram of a screen of the display unit 8. The display unit 8 is a dot matrix character display device that displays 21 characters in 3 rows and 7 columns. In the figure, character display areas 8a, 8b, 8c... It consists of 7 vertical dots.

Next, the circuit configuration of the data setting unit 6 in FIG. 1 will be described. First, specify the digit storage unit 9 are up-counter for storing display digits setting is performed, when the switch S ₃ is operated, the count-up from the one-shot pulse generating circuit 10 adds the pulse, each the pulse is applied And counts from “0” to “21”. The count value of the designated digit storage unit 9 is added to the decoder 11 and the display control unit 7, and the decoder 11 is a decoder for decoding the designated display digit data value input from the designated digit storage unit 9. Decoder 11
1 Output to 21 output is applied to respective gates G ₁ ~G _21, the gate G ₁ ~G ₂₁ that joined the H level is opened,
An AND gate in which the character codes output from the alphabet pattern generation circuit 12, the number pattern generation circuit 13, and the kana character pattern generation circuit 14, which will be described later, are open.
AND gates G _{1 to} G that are open through G _{1 to} G ₂₁
It is set in the 8-bit shift register of the shift register 5 connected to ₂₁ .

On the other hand, the display control unit 7 controls the flashing and lighting of the display unit 8 in accordance with the designated display digit data input from the designated digit storage unit 9, and is designated based on the value of the designated display digit data. The display digit is flashed.

Reference numeral 15 denotes a character designation counter, which comprises an up counter that counts from "0" to "85". Then, enter the pulse from the one-shot pulse generating circuit 16 which is generated each time the switch S ₄ is operated, for counting the pulses. The count value of the character designation counter 15 is added to the decoder 17, and the decoder 17 decodes the count value input from the character designation counter 15 and sets the output according to the count value to the H level. The outputs 0 to 25 of the decoder 17 correspond to the alphabet pattern generation circuit 12.
The outputs 26 to 35 are applied to the numeral pattern generating circuit 13, the outputs 36 to 85 are applied to the kana character pattern generating circuit 14, and the output 36 is applied to the ungate 18.

The alphabet pattern generation circuit 12, the number pattern generation circuit 13, and the kana character pattern generation circuit 14 are composed of a ROM (Read Only Memory), and each of the decoder 17 has 0 to 25 outputs, 26 to 35 outputs, and 36 to 85 outputs. The output is input as an address signal.

The alphabet pattern generation circuit 12 converts “A” to “Z”.
The character codes of the alphabets up to are stored, and according to the address bit signal at H level among the address signals 0 to 25 applied from the decoder 17,
Each outputting one of the character code "Z" alphabet "A", applied to the gate G ₁ ~G _21. The number pattern generating circuit 13 stores character codes of numbers from "0" to "9", and outputs any one of 0 to 9 in accordance with the output 26 to 35 from the decoder 17, Add to G ₁ ~G _21. Kana character pattern generation circuit 1
4 stores character codes of kana characters from "a" to "n". Each of them stores a kana character in accordance with an H-level address bit signal among address signals 36 to 85 applied from the decoder 17. The characters "a", "i",
"C", ..., and outputs a character code of "down" applied to the gate G ₁ ~G _21.

Next, the T flip-flop 19 is connected to the switch control unit 1.
A trigger flip-flop being input mode switching signal K is output (simultaneous push the output of the switch S ₁ and S ₂₎ to the terminal T from, Q for each rise of the mode switching signal K, for inverting the output. The Q output (signal M ₁ ) and output (signal M ₂ ) of the T flip-flop are input to a switching pattern signal generation circuit 20, and the Q output is further supplied to an AND gate 18.
Is being entered. The output of the ungate 18 is input to the reset terminal R of the character designation counter 15 and
17 36 outputs Y and Q output of T flip-flop are both H
When the level is at the level, the character designation counter 15 is reset via the ungate 18.

Further, a switching pattern signal generating circuit 20 to which signals M ₁ and M ₂ output from the terminal Q of the T flip-flop 19 are input.
Is a circuit for outputting respective switching pattern signal to the display control unit 7 at the rising of the rising and the signal M ₂ of the signal M _1.

In the above configuration, sequentially alone operation of the switch S ₁
It is possible to select the RAM2 of the next page, it is possible to select the sequential Previous alone operation of the switch S _2. Therefore, it is possible to freely select a desired page by a single operation of the switch S ₁ or switch S _2. Figure 3 shows the display contents displayed on the display unit 8 by the operation of the switches S ₁ and S _2.

Further, after selecting the desired page alone operation of the switch S ₁ or switch S ₂ is the predetermined digit of the displayed for correction or set by operating the switch S ₃ on the display unit 8 pages You can choose. Operating the switch S _3, applied from the one-shot pulse generating circuit 10 to the input terminal of the pulse is designated digit storage portion 9 of the one-shot, designated digit storage unit 9 adds the digit data stored. Therefore, designation digit storage portion 9 for every operating the switch S ₃ are summed digits data applied to the decoder 11.

Decoder 11, opens one of the gates G ₁ ~G ₂₁ in accordance with the value of the digit data input from the designated digit storage unit 9. Therefore, every time to operate the switch S _3, the gate G _1, G ₂ ... G ₂₁
Are sequentially released.

Further, the display control unit 7 displays the display digit specified by the digit data added from the specified digit storage unit 9 in a dotted manner. Therefore,
Display digits selected by the operation of the switch S ₃ is displayed down point.

Data specification of the display digits selected by the switch S ₃ is performed by the operation of the switch S _4.

Operating the switch S _4, the one-shot pulse character specified counter from the one-shot pulse generating circuit 16
Apply to 15 input terminals. Character designation counter 15
Each time a pulse is applied to the input terminal, the count is incremented, and the count value is applied to the decoder 17. The decoder 17 changes one of the outputs to the H level in accordance with the value of the count data added from the character designation counter 15, and adds the output to the alphabet pattern generation circuit 12, the number pattern generation circuit 13, or the kana character pattern generation circuit 14. 12, when 0-25 either the output of the decoder 17 rises to H level, respectively outputs one of the character codes of the alphabet "a" ~ "Z" to the gate G ₁ ~G _21. Also, the number pattern generation circuit 1
3, one of 26-35 output of the decoder 17 is when the rises to H level, outputs one of the character codes of respective numerals "0" to "9" to the gate G ₁ ~G _21. Furthermore, the kana character pattern generation circuit 14
85 one of the outputs to output a character code of the kana letter "A" - "down" respectively when rises to H level to the gate G ₁ ~G _21. Therefore, the alphabet pattern generating circuit 12 for each to operate the switch S _4, numeral pattern generating circuit 13, a kana character pattern generating circuit 14, alphabetic "A" - "Z", numbers "0" to "9", kana characters “A”
Character Code - "down" is output sequentially to the gate G ₁ ~G _21, via the opened in which the gate is set to a register that is specified in the shift register 5.

Thus, the 36 output Y of the decoder 17 is applied to the ungate 18 and the Q output of the T flip-flop 19 (signal M ₁ ).
Is at the H level and is participating in the ungate,
When the 36 output Y of the decoder 17 becomes H level,
The H level is applied to the reset terminal R of the character designation counter 15 via 18 and the character designation counter 15 is set to "0".
Is reset to Therefore, the character designation counter 15 counts from "0" to "35" and outputs only alphabets and numbers. When the Q output of the T flip-flop 19 is at the L level, the character designation counter 15 is not reset even if the 36 output Y of the decoder 17 is at the H level, and counts from "0" to "85".
Output numbers and kana characters.

Here, 4 (a), shows the data set by operation of the key S ₄ in (b).

T Q output of the flip-flop 19 is in kana there mode at the L level, each operating the key S _4, the alphabet pattern generating circuit 12, numeral pattern generating circuit 13,
From the kana character pattern generation circuit 14 to the alphabet "A"
The character codes of “Z”, the numbers “0” to “9”, and the kana characters “a” to “n” are sequentially output, and the output character codes pass through the open G × and the shift register 5 because it is set in a register of the specified, as shown in FIG. 4 (a) for each the display the selected digit display section 8 to operate the key S _4, "a" → "B" → "C"
... → "Y" → "Z" → "0" → "1" → "2" ... →
"9" → "A" → "I" → "U" ... → "N" is displayed. Character specified counter 15, after counting up from "0" to "85", so to start counting again from "0", in Kana There mode, the operation of the key S ₄ "A" → "B" → "C" ... → "Y" → "Z" → "0" →
"1" → "2" ... → "9" → "A" → "I" → "U" ...
→ "N" is cyclically displayed at the selected display digit of the display section 8. Therefore, in the kana mode, the alphabets "A" to "Z" and the numbers "0" to
"9" and kana characters "a" to "n" can be sequentially set cyclically.

On the other hand, when the Q output of the T flip-flop 19 is at H level is kana mode without, in kana no mode is counted up from "0" to "35" for each character designation counter 15 to operate the key S ₄ every operating the key S ₄ so that, in alphabetical pattern generating circuit 12, alphabetic sequentially output from numerical pattern generating circuit 13 "a"
~ "Z" and the character codes of the numbers "0"-"9"
The shift register 5 passes through the open gate G ×
Is set to Via the display control unit 7 for each operating key S _4, display digit of the display unit 8 as shown in FIG. 4 (b) "A" → "B" → "C" ... → "Y" → "Z" → "0" →
"1" → "2" ... → "9" are displayed cyclically. Therefore, in the kanaless mode, alphabets “A” to “Z” and numbers “0” to “9” can be set.

Such mode switching Kana with-a pinion without mode, by performing the simultaneous operation of switches S ₁ and switch S ₂ as described above, alternately at any time mode switching signal K from the switch control unit 1 is output It is possible to switch.

When the mode with the kana and the mode without the kana are thus switched, the switching pattern signal generation circuit 20
Is a pattern signal indicating that the switched by detecting that the signal M ₁ or M ₂ has risen a predetermined time, for example 1
It is sent to the display control unit 7 for a second to notify the user of the switching.

FIG. 5 shows the display state when the mode is switched from the mode with kana to the mode without kana.
→ JAPANESE is displayed.

Thus, in the above embodiment, the setting switch S ₄
When the Kana character is set, it is possible to select in advance whether the Kana character is set or not when the Kana character is set. Only characters can be set, and the setting operation is extremely simplified.

In the above embodiment, the case of katakana has been described as the kana character, but it is needless to say that the character may be flat kana.

In addition, we made it possible to select whether or not kana, but instead of kana,
It may be made possible to select the presence or absence of alphabets and numbers, and further, it may be possible to select either alphabets or kana.

[Effect of the invention]

As described above, according to the present invention, an arbitrary data set is selected from among the data sets stored in the data storage means, and the data set is read out from the selected data set. Since the data can be input to the position selected by the position selection means,
The set of data to be set can be arbitrarily selected from among the set of stored data. Therefore, data input setting can be performed only with the necessary set of data, simplifying the data setting operation and significantly improving usability. This has the effect of achieving the following.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an overall block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an image configuration of a display unit 8, and FIG. 3 is a diagram showing a change in a display state by a switch operation. , FIGS. 4 (a) and 4 (b) show the display of the mode switching pattern with kana and the mode switching pattern without kana, respectively. FIG. 5 shows the switches S ₁ ,
S ₂ is a diagram illustrating a display state when co-operation. 2 ... RAM, 3 ... RAM address control unit, 5 ... shift register, 6 ... data control unit, 9 ... designated digit storage unit, 15
…… Character designation counter, 20 …… Switching pattern signal generation circuit.

Claims (1)

(57) [Scope of request for utility model registration] 1. A position selecting means for selecting a position for inputting data, a data storing means for storing a different set of data, and an arbitrary data set from a set of data stored in the data storing means. A data selecting means for selecting a set; and an input for reading data in order from a set of data selected by the data selecting means and inputting the read data to a position selected by the position selecting means. And a data input device.