JPS6236554B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic watch capable of displaying time, date, and memos, and more particularly to a memory diary circuit that stores daily memos as contents.

Electronic watches with a memory/dial that store and display daily memos have not been put into practical use due to their large storage capacity. There are the following two configurations of the memory circuit of the memory diary circuit that have been conventionally considered. With these configurations, it is possible to store memory for one year from "today", the number of memo types is up to 16, the number of memoable dates is 64, and the content of one type of memo uses character codes, etc. Ten
Consider the case where it is about the size of characters.

A first configuration example of a conventional storage circuit stores the date and month, and determines memo selection using a matching circuit. That is, 4 bits specifying the month and 5 bits specifying the day are stored in a circuit, specifically in a random access memory (hereinafter referred to as RAM), along with 4 bits specifying a predetermined memo type, and once a day, It compares the bit data of the month and day of "Today" and extracts the data that matches the month and day. Of course, it is possible to directly memorize the memo contents as character codes without memorizing the predetermined memo type, but some of the actual memo contents are the same, and 64 types of memo contents can be directly memorized. Doing so greatly increases capacity. For example, the character code is 5
If you need bits, please use 64× as a 10 character memo.
A capacity of 10×5=3200 bits is required. If you limit it to 16 types, 800 bits is sufficient. Then,
Instead of directly storing memo contents, the memo type is stored and the contents are called up using the type code. Now, in the first configuration, 64 types of 9 bits for month and day and 4 bits for memo type are required.
+4) x 64 = 832 bits, which requires quite a bit. Furthermore, with this configuration, it becomes complicated to replace old data with new data.

A second configuration example of a conventional memory circuit provides 4 bits for memory type for one year's worth of dates, for example, 384 dates with a margin. In other words, storage capacity for each memo type is secured for each day, regardless of whether it is selected or not. 384×4
= 1536 bits of capacity, and the capacity of the memory circuit becomes enormous.

In this way, in both the conventional first configuration and the second configuration, the capacity of the memory circuit increases,
Practical implementation is difficult.

SUMMARY OF THE INVENTION An object of the present invention is to realize a low-cost electronic watch with a memory diary that allows a memory diary to store a large number of dates and memo contents corresponding to the dates with a small storage capacity.

The present invention relates to an electronic watch capable of displaying time, date, and memo. This configuration includes a storage circuit that stores memo types. According to the configuration of the present invention, in the above-mentioned example, the memory circuit D has 384 bits corresponding to the dates of one year, and the memory circuit M has 64×4=256 bits, reducing the total to 640 bits. In this case, a storage circuit C may be provided that stores the memo type contents in the order of type using character codes or the like. However, if the memo type is determined in advance, the memory circuit C is not necessary. Furthermore, in order to associate the settings of the memory circuit D and the memory circuit M,
It has a circuit that counts the order of memo setting states from "today" date. In addition, to avoid breaking the association of settings even if the memo settings are not done in date order, the transition between the two states of memo setting and non-setting is possible.
It has a control circuit for performing an editing function of inserting or deleting the contents stored in the memory circuit M.

Next, the present invention will be explained in detail with reference to the drawings. First, the appearance and specifications of an electronic timepiece to which the present invention is applied will be explained. Figure 1a is an example of normal time display, May 26
Sunday (Monday) 12:56:34 is displayed. Prepare four operation switches 11, 12, 13, and 14. The display section specifically uses a liquid crystal display,
This is done using a 5x7 dot matrix method. Since the display material, driving method, etc. are not essential to the present invention, their explanation will be omitted. It may be embodied by an LED display or a starburst display method.

Now, if a memo is selected for "Today", that is, May 26th, and you press switch 11, the first
The display changes to that shown in Figure b. This display has a memo setting for “Today” and another number 10 “MEET”.
TOYODA”. If the memo is not set, the type number and contents will not be displayed. In this way, you can check your daily notes with just one touch.

FIG. 2a shows an example of the display when inputting memo settings and non-memo settings. When switch 12 is pressed, the memo setting date setting state is entered. At this time, the switch 13 is pressed to increase the date, and the switch 14 is pressed to decrease the date. The date change range is "today"
In other words, it is one year from the display date of the normal time. By pressing the switch 11, it is determined whether the displayed date is set as a memo or not set as a memo.
In the settings, the memo type number is displayed when the time is normal, and it is not displayed when it is not set. If the switch 12 is pressed without setting a memo, the state returns to the normal time or other functional state, and if the switch 12 is pressed with the memo setting, the memo type selection state is entered. In this state, the date display disappears, the memo type number blinks, and the contents are also displayed in characters. switch 13
Press to change decrease. There are 16 type numbers in total, and numbers 0 and 15 are consecutive. Along with changes in the type number, the contents are also displayed if they have been determined in advance. If you do not want to change the contents, press the switch 12 to return to the date setting state of the memo setting, and if you want to change the contents, press the switch 11 and move and select the corrected character position one character at a time. The corrected character position is identified as a blinking display. Press the switch 11 11 times to return to the type number selection state. If no change is required, press the switch 12 to return to the date setting state. To modify characters, select the necessary characters by arranging 0 to 9 and A to Z in order and changing them in increasing order by switch 13 and decreasing order by switch 14. If you modify it like this, you won't need any special character input keys. FIG. 2b shows an example of the display of the character correction state. This indicates that the first character of type number 2 "TRIPTOKYO" is being revised. FIG. 3 shows a block diagram showing the overall circuit configuration of an embodiment of the electronic timepiece of the present invention. An oscillation frequency dividing circuit 33 including a crystal oscillator etc. outputs basic signals for a clock to a clock counter 34 and outputs clock signals for control to a control circuit 32. The control circuit 32 inputs switch signals from the operation of the external switch 31, and stores various control signals in the memory circuit 35 and the clock counter 3.
4. Input to multiplexer 36, decoder 37, and driver 38. A clock counter counts seconds, minutes, hours, days, months, days, etc., and forms bit signals. The memory circuit 35 is a main part of the present invention and is for storing memos, and takes in "today" data from the clock counter 34. The multiplexer 36 selects data for normal display and data for memo display. The decoder 37 converts the bit signal into a specific signal for display, and its output is sent to the driver 38.
and drives a display device (not shown).

FIG. 4 is a block diagram showing the memory circuit 35 of the present invention in more detail. The main block configuration is a memory circuit (RAM-D) 41, a counter A
42, latch D43, counter N44, counter E45, adder 46, coincidence circuit 47, multiplexer E48, memory circuit (RAM-M) 49,
They are a latch M50, a multiplexer M51, and a counter B52. In addition, memo content storage circuit C
There is, but the explanation is omitted because it is not distinctive. In addition, signals and data are indicated by three characters, and the characteristic ones are shown in the timing chart shown in FIG.

In FIG. 4, a memory circuit (RAM-D) 41
has a memory capacity corresponding to one year's worth of dates from the current day, and stores the presence or absence of memo settings for each date.
The memory circuit (RAM-M) 49 is a memory circuit (RAM-M).
- D) Store the memo type of the date set as a memo in 41 as a code. At this time, the memory circuit (RAM-
M) 49 data is stored in the memory circuit (RAM-D) 41
Only the dates for which the memo setting is enabled must be stored in date order and have a corresponding relationship.

While maintaining this correspondence, the memory circuit (RAM)
-M) Counter N determines the address of 49.
44, and the counter D45 and the like perform editing functions such as rearranging and inserting dates.

Counter A42 is memory circuit (DAM-D) 4
1. A circuit for sequentially setting notes starting from the current day.
Counter B52 is a memory circuit (RAM-M) 49
This is a circuit for selecting the memo type to be stored in the memory circuit (RAM-M) 4, which changes the contents of counter B using the signal BCK to determine the memo type, and stores the value in memory circuit (RAM-M) 4.
9 to memorize it. The correspondence between the contents of counter B and the memo type is determined in advance by a decoder (not shown) or the like.

Next, the operation will be explained.

The counter A42 is a presettable up-down counter, and the preset data is the 4-bit month and 5-bit day "today" data TDY sent from the clock counter 34 in FIG. 3, and the preset signal is the normal time. This is the signal TOR that becomes 1 when returning to the state. That is, in the normal time state, the output of counter A is the same as the data for "today," so memo setting can be performed by sequentially incrementing the value of counter A starting from the current day. The up-down signal UDA and the clock signal ACK are obtained from the control circuit 32 when the switch 13 or the switch 14 is pressed in the date setting state of the memo setting.
You can get a clock signal with either UP with 14 or DOWN with 14. By operating the switches 13 and 14, a date for setting a memo is selected. counter A42
The output ADQ is the data of the memo setting date and is also the address data of the memory circuit D41. The memory circuit D41 is a 384-bit capacity RAM with 1-bit input/output, and receives the signal DRW as a read/write signal. 384 bits is enough capacity for one year's worth of dates. The signal DRW is a signal that becomes 0 every time the date setting/non-setting switch 11 of the memo setting is pressed, and this signal changes the memory contents from the first state indicating that it is not the specified date to the specified date. Invert it to the second state shown. For this purpose, a latch D43 is prepared, which is latched by the output latch signal DCL of the RAM, inputted as an inverted signal via an inverter and stored, and used as a display signal DDQ of the set state. These signal waveforms are shown in FIG. 5a.

Counter N44 is an up-down counter that counts the number of dates set as notes in RAM-D and determines the address of memory circuit RAM-M49. The signal TOR is used as a reset signal, and the signal UDA is used as an up-down signal, but the clock signal NCK is a delayed signal of the signal ACK.
It is an AND of ACK' and signal DDQ, and is configured to count only the dates in the set state. Inhibit signal to prohibit counting
INH uses signals NDQ and UDA, which become 1 when all bits are down (0) or all bits (1) are up, causing the counter N44 to stop writing. Counter N has 64 counters, 64
Allows daily memo settings. The output data NDQ of counter N is 6 bits.

The counter E45 is a presettable up-down counter and is used for an editing function when adding or deleting memo settings. The up-down signal is the signal UDE, which becomes 1 when deleting a memo setting and 0 when inserting and adding a memo setting.
This signal is generated from the reset latch. The preset data is data NDQ when counting up, and 111110 when counting down. Preset signal is signal PSE
This is the signal that pulses when the editing function starts. The clock signal is the ECK signal, and has a frequency of about 1KHz to allow editing work to be done in a short time. The inhibit signal to stop counting uses the signal IDT, which is obtained from the coincidence circuit 47, and when counting up, it becomes 1 at 111111,
When counting down, it becomes 1 when it matches data NDQ. Output data EDQ of counter E is input to adder 46. Adder 46 is a signal
When ADD is 1, add 1 to data EDQ,
When is 0, the data is output as is. Let the output data be EDQ′. The reason for the need for an adder is to synchronize it with the latch M50 and use the memory circuit RAM.
- This is because the address of the data in M49 is moved one location at a time, so the address that has been increased by one and the original address are specified alternately.

The signal EDT becomes 1 when a memo setting or non-setting occurs, that is, when the signal DRW becomes 0, and becomes 0 when the counter E temporarily finishes counting, that is, at the rising edge of the signal IDT.
This indicates that editing is in progress.

The multiplexer E outputs data EDQ' when the signal IDT is 0, that is, during editing work, and outputs the data NDQ when it is 1, that is, in the normal state, and outputs the address signal of the storage circuit M49 as the output data NEQ. becomes. Therefore, during editing work, the address can be changed at high speed using the counter E, and during non-editing, the address of the memo type of the set date can be specified using the counter N.

The memory circuit (RAM-M) 49 is a 256-bit capacity RAM with 4-bit parallel input/output.
The write signal is the signal MRW, and during editing work it is 1
and 0 are repeated in synchronization with the signal ECK. When not editing and changing the memo type, it becomes 0 and rewrites only after the pulse of the clock signal BCK of counter B52 is received. Otherwise, it remains 1 and is read. state. The output of RAM M49 becomes data MDQ latched by latch M50. The data MDQ means the memo type, and it is ANDed with the signal DDQ to become the display data DDD, which is stored in the RAM by the display device.
- The memo type is displayed in correspondence with the date of D41. Also, during editing work, multiplexer M5
1 also serves as a data-in signal. Counter B52 is a 4-bit up-down counter for changing the memo type, and the memo type is determined by the contents of counter B. clock signal
BCK and the up-down signal UDB change immediately after the switches 13 and 14 are pressed in the memo type selection state, and the memo type can be selected by the switches 13 and 14. This output data BDQ is sent to multiplexer M5 during non-editing.
1 becomes the data-in signal for RAM.M.

The waveforms of the main signals mentioned above, especially those related to editing work, are shown in FIGS. 5b and 5c.
b relates to deletion, and c relates to insertion/addition, but the signals DRW, EDT, PSE, and IDT are similar to b. As an example, the operation when deleting the memo setting at address n will be briefly described. First, counter N presets counter E to the value of the address in RAM-M49 where the memo type of the corresponding day is stored. Letting this address be n,
The signal ADD is already 1 and the data EDQ′ is n+
1, the memo type data at address n+1 is latched by latch M50, and immediately after, ADD becomes 0,
EDQ' returns to n and writes data MDQ to address n. After that, counter E counts up and n
The data at address +2 is written to address n+1, and the process is continued in the same manner up to the last address to complete the deletion. Regarding the insertion/addition operation, the counter E is preset to l-1, which is one address before the final address. ADD is 0
Then, data EDQ' indicates l-1, the type data at this address is latched, ADD becomes 1,
EDQ' indicates l, and data MDQ writes address l.
After that, counter E counts down and l-2
Write the item at address l-1, continue the process, write the item at address n-1 to address n, and then write the item at address n-1.
After emptying the address, new memo type data is written and the insertion is completed.

In the circuit configuration of the present invention, the memo type "today" must always be at address 0 of RAM.M. If it is the set date, it is necessary to delete address 0 at the end of "Today". Since this can be easily achieved using the editing function described above, the explanation will be omitted.

As described above, according to the memory/diary circuit of the present invention, an electronic watch can be equipped with a relatively low capacity RAM.
A memory/diary function can be realized by adding . It is particularly useful for wristwatches that require smaller ICs and other components.

[Brief explanation of the drawing]

1 and 2 show the appearance and specifications of an electronic timepiece according to an embodiment of the present invention. FIG. 3 is a block diagram showing the overall circuit configuration of the electronic timepiece according to the embodiment. FIG. 4 is a block diagram showing the detailed circuit configuration of the memory circuit of the embodiment. FIG. 5 is a timing chart showing characteristic signals of the embodiment. 11, 12, 13, 14...switch, 41...storage circuit D, 49...storage circuit M.

Claims (1)

[Claims] 1. In an electronic watch that includes an oscillation circuit, a frequency dividing circuit, a clock counter, a display device, and a memory diary that stores a plurality of specified dates and memo types corresponding to the specified days, the memory diary stores data for the number of days in a predetermined period. a first memory circuit having a corresponding memory capacity and having a memory address designated by month/day data;
a first counter to which a first external operating member is connected, which counts the number of operating signals from the first external operating member and supplies the counted value to the first storage circuit as a first address signal; In response to a read/write signal from a second external operation member connected to the first storage circuit, the value of the address of the first storage circuit specified by the first counter is set on the specified date. an inverting circuit that inverts from a first state representing that the specified day is not to a second state representing the specified date and writes it as specified date data; each specified date (second state) data stored in the first storage circuit; a second storage circuit in which the memo types corresponding to
1. An electronic timepiece with a memory and diary, comprising a second counter that supplies an address signal to a memory circuit.