JPH0447279A - Board testing circuit - Google Patents

Abstract

PURPOSE:To test a board having an A/D converter and a digital LSI mounted thereon by detecting a logical value from the test round connected to the digital LSI when all of the output logical values of the A/D converter are 0 and 1. CONSTITUTION:At a testing time, the max. and min. values of the input voltage of an A/D converter 4 are generated by a voltage converting apparatus 1. When the voltage is the max. value, all of the n-bit output logical values of the converter 4 become 1 and, therefore, both of the logical values of an AND circuit 2 and an OR circuit 23 become 1 and logical values 1 are obtained from two test rounds 8 on a board 2. When the voltage is the min. value, all of the n-bit output logical values of the converter 4 become 0 and both of the output logical values of the circuits 22, 23 become 0 and logical values 0 are obtained from two test rounds 8 on the board 2. If there is trouble or contact inferiority in either one of an analogue input terminal 3, the input and output terminals of the converter 4 and the input terminal of the digital LSI 5 and the logical values of the input terminal of a test part are different through one bit, no logical value is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a board test circuit for testing a board on which an A/D converter and a digital LSI are mounted, and a board on which a D/A converter and a digital LSI are mounted. This relates to a board test circuit for testing.

2. Description of the Related Art In recent years, board test circuits have been frequently used to check the operation and wiring of a board on which an LSI is mounted, and to identify defective boards.

An example of the above-mentioned conventional board test circuit will be described below with reference to the drawings.

FIG. 9 shows a circuit diagram of a conventional board test circuit called boundary scan.

In FIG. 9, 71 and 72 are digital LSIs.

73a - 73b and 73c are input terminals of the digital LSI 71, and input registers 74a, 74b, and 74c, respectively.
It is connected to the digital signal processing section 75 via. 76
A, 76b, and 76c are output terminals of the digital LSI 71, and are connected to the digital signal processing section 75 via output registers 77a, 77b, and 77c, respectively. 78a/78b
- 78c is an input terminal of the digital LSI 72, which is connected to the digital signal processing unit 80 via input registers 79a, 79b, and 79c, respectively. 81a, Blb, and 81c are output terminals of the digital LSI 72, and each output register 8
Digital signal processing section 83 via 2a, 82b, 82c
is connected to. 83 is a test input terminal of the digital l, 5I71, which is connected to the test output terminal 84 via input registers 74c, 74b, 74a and output registers 77a, 77b, 77c, and is shifted onto the boundary scan path 87. It constitutes a register. Similarly 85
are the test input terminals of the digital LSI 72, and the input registers 79c, 79b, 79a and the output registers 82a, 8
It is connected to the test output terminal 86 via terminals 2b and 82c, and forms a shift register on the boundary scan path 88. Further, each output terminal 76a, 76b, 76c of the digital LSI 71 is connected to each input terminal 78a, 78b, 78c of the digital LSI 72, and the test output terminal 84 of the digital LSI 71 is connected to each input terminal 78a, 78b, 78c of the digital LSI 72.
It is connected to the test input terminal 85 of 72.

Regarding the board test circuit configured as above,
The operation will be explained below.

First, in the normal operation mode, the input signals of the input terminals 73a, 73b, and 73c of the digital LSI 71 are processed by the digital signal processing unit 75 via the input registers 74a, 74b, and 74c, and the output registers 77a, 77b, and
Output signals are obtained from output terminals 76a, 76b, and 76c, respectively, via 77c. Each output signal is further input to the digital LS 172 through each input terminal 78a, 78b, 78c. In digital LSI72, input terminal 78a/7
Signals 8b and 78c are input to input registers 79a and 79, respectively.
The signals are processed by the digital signal processing unit 80 via the output terminals 81a, 81b, and 81c via the output registers 82a, 82b, and 82c, respectively, and output signals are obtained from the output terminals 81a, 81b, and 81c, respectively.

Next, in the test mode, the input signals of the input terminals 73a, 73b, 73c of the digital LSI 71 are loaded into the boundary scan path 87 by the input registers 74a, 74b, 74c, respectively, and the input signals of the input registers 74c, 74b-
The signal moves through a shift register consisting of output registers 74a, 77a, 77b, and 77C, and outputs the signal to output register 77.
This leads to a, 77b, and 77c. Output register 77a 17
Each signal of b-77c reaches each input register 79a, 79b, 79c via each output terminal 76a, 76b, 76c of digital LSI 71 and each input terminal 78a, 78b, 78c of digital LSI 72. Input register 79a・
79b and 79c signals are boundary scan path 8
loaded into the input registers 79c, 79b, 79a
The signal moves through a shift register composed of output registers 82a, 82b, and 82c, and outputs the output registers 82a, 82c.
2b/82c. Output register 82a, 82b, 8
The signals 2c are obtained from the output terminals 81a, 81b, and 81c, respectively, and are eventually sent to the input/output terminal 73a of the digital LSI 71.
・73b - "13c -16a 46b 46c and input/output terminal 78a of digital LSI 72 ・78b
・You can test the wiring of 78c, 81a, 81b, and 81c.

Furthermore, a test input terminal 83 of the digital LSI 71,
The test output terminal 84, the test input terminal 85 of the digital LSI 72, and the test output terminal 86 are
Since they are connected to one line via the scan paths 87 and 88, any terminal of each digital LSI 71 and 72 can be accessed from the test input terminal 83 of the digital LSI 71.

Problems to be Solved by the Invention However, the above configuration has a problem in that it cannot be used to test A/D converters or D/A converters because it can only be applied to digital circuits.

In view of the above problems, the present invention provides an A/D converter and a digital LS.
The present invention provides a board test circuit for testing a board on which an IC is mounted, and a board test circuit for testing a board on which a D/A converter and a digital LSI are mounted.

Means for Solving the Problems In order to solve the above problems, (]) The board test circuit of the present invention has an A/D converter installed inside a digital LSI connected to the output end of the A/D converter. The device is equipped with means for detecting whether the output logical values are all 0 or all 1 from a test round located on the board and connected to the output end of the digital LSI.

(2) The board test circuit of the present invention uses the LSB of the output end of the A/D converter as a clock input to input all bits other than the LSB into a digital LSI connected to the output end of the A/D converter. A first D flip-flop whose input is the LSB of the output terminal of the A/D converter is the clock input, and a second D flip-flop whose output terminal of the first D flip-flop is the D input.
A D flip-flop, a subtracter that takes the difference between the output logic values of the first D flip-flop and the second D flip-flop, and a subtracter that shows that the output logic value of the fIiX unit is 1 is printed on the board. It is equipped with means for detecting from a test round connected to the output end of the digital LSI.

(3) The board test circuit of the present invention includes a decoder and n AND circuits each having an n-bit output terminal of the decoder as an input, inside a digital LSI connected to an input terminal of a D/A converter. , an oscillator connected to the input terminal of each of the n AND circuits, and an output terminal of the n AND circuits and a digital L
It is equipped with a selector that switches the n-bit output terminal of the digital signal processing section inside the SI and outputs it to the input terminal of the D/A converter. The first test round is connected to the terminal, and the second test round is connected to the terminal for switching the output signal of the selector.

Operation The present invention has the above-described configuration. (1) The minimum and maximum values of the input voltage are given from the voltage generator to the A/D converter, and the output logic values of the A/D converter are all 0 and all 1. In the case of digital LS on the board
A wiring test that detects failures and poor connections of analog input terminals, A/D converter input/output terminals, and digital LSI input terminals by detecting from the test round connected to the output terminal of I, and A/D converter You can test the operation when the input voltage is at the minimum and maximum values.

(2) When a monotonically increasing voltage is applied from the voltage generator to the A/D converter from the minimum value to the maximum value of the input voltage, the A/D converter
The LSB of the output end of the D converter is used as the clock input.
The output logic value of the first D flip-flop whose D inputs are all bits other than It is always one value larger than the output logic value of the second D-flash flop. Therefore, it is detected from the test round that the value obtained by subtracting the output logic value of the second D flip-flop from the output logic value of the first D flip-flop is 1, and the analog input terminal and A/D conversion are performed. Failure of the input/output terminals of the device and the input terminals of the digital LSI
Wiring tests to detect contact failures and even contacts between adjacent bits, and operation tests for all output logic values of the A/D converter can be performed.

(3) During normal operation, the output signal of the digital signal processing section is
A signal is output to the input terminal of the /A converter, and during test operation, a signal in which the logic value generated by the oscillator toggles between 0 and 1 is output to the D/A converter.
By applying it to each bit of the converter and measuring the AC amplitude of its analog output, it is possible to detect malfunctions, poor connections, and adjacent connections between the output terminal of the digital LSI, the input/output terminal of the D/A converter, and the analog output terminal. Wiring tests to detect bit contact and rough operation tests of D/A converters can be performed.

Embodiment Below, a board test circuit according to a first embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a board test circuit in a first embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a voltage generator, which is connected to an analog input terminal 3 of a board 2. In FIG. The board 2 includes an A/Di converter 4 whose input terminal is the analog input terminal 3, and a digital LSI 5 connected to the n-bit output terminal of the A/D converter 4.
has been implemented.

Inside the digital LSI 5, there is a test section 6 connected to an n-bit input terminal and a digital signal processing section 7, and an output terminal of the test section 6 is connected to one or more test rounds 8 on the board 2. .

FIG. 2 is a circuit diagram of the test section 6 of FIG. 1 in the first embodiment of the present invention. In FIG. 2, 21 is an n-bit test section input terminal, and 22 and 23 are an AND circuit and an OR circuit that take the AND and OR of the n pins of the test section input terminal 21, respectively. 24a and 24b are test unit output terminals connected to the output terminals of the AND circuit 22 and the OR circuit 23, respectively, and are connected to the test round 8 on the board 2.

However, in this case, there are two last rounds 8.

Regarding the test circuit configured as above, the following is the first part.
The operation will be explained using FIG.

First, in FIG. 1, during normal operation, an analog input signal at the analog input terminal 3 is exchanged into an n-bit digital signal by the A/D converter 4, inputted to the digital LSI 5, and signal processed by the digital signal processing section 7. Do this.

Next, during testing, the voltage generator 1 generates the maximum and minimum values of the input voltage of the A/D converter 4.

When the voltage is at its maximum value, all n-bit output logical values of the A/D converter 4 are 1, and in FIG. 2, the logical value 1 is input to all bits of the test section input terminal 21. Therefore A
The output logic values of the ND circuit 22 and the OR circuit 23 are both 1, and the logic value 1 is obtained from the two test rounds 8 on the board 2 in FIG. 1 through the test section output terminals 24a and 24b. When the voltage is the minimum value, n of the A/D converter 4
The output logical values of the bits are all 0, and in FIG. 2, the logical value O is input to all the bits of the test section input terminal 21.

Therefore, the output logic values of the AND circuit 22 and the OR circuit 23 are both O, and the logic N10 is obtained from the two test rounds 8 on the board 2 via the test section output terminals 24a and 24b. If analog input terminal 3 or A/D converter 4
If there is a failure or poor contact in either the input/output terminal of the digital LS 5 or the input terminal of the digital LS
If the logical values of are different even by 1 bit, the above logical values will not be achieved.

As described above, according to this experimental example, by providing the test section 6 inside the digital LSI 5 that can detect when the output logic values of the A/D converter 4 are all 1 and when they are O, A wiring test to detect failures and poor connections between the analog input terminal 3, the A/D converter 40 input/output terminal, and the n-bit input terminal of the digital LSI 5, and the maximum and minimum values of the input voltage of the A/D converter 4. You can test the operation in the case of

A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit diagram of the test section 6 of FIG. 1 in a second embodiment of the present invention.

In FIG. 3, 21 is an n-bit test section input terminal;
31 is a D flip-flop whose D input is the upper (n-1) bits of the test section input terminal 21, and whose clock input is the LSB of the test section input terminal 21. 32 is a D flip-flop whose D input is the output terminal of the D flip-flop 31 and whose clock input is the LSB of the test section input terminal 21;
The bit output signal is also subtracted from the (n-1) bit output signal of the flip-flop 31 by the subtracter 33 .

The LSB of the (n-1) bit output end of the subtracter 33 is NO.
Connected to the input terminal of the T circuit 34, and connected to the upper (n-
2) The output terminal of the bit and the output terminal of the NOT circuit 34 are NOR
Connect to the input end of circuit 35. The output terminal of the NOR circuit 35 is connected to the test section output terminal 36, and the output terminal of the NOR circuit 35 is connected to the test section output terminal 36.
6 is connected to test round 8 in FIG.

Regarding the board test circuit configured as above,
The operation will be explained below.

First, since the normal operation is the same as that of the first embodiment, the explanation will be omitted.

Next, during the test, from the voltage generator 1 in FIG.
A voltage that monotonically increases from the minimum value to the maximum value of the input voltage of the A/D converter 4 is provided. Then, the n-bit output logic values of the A/D converter 4 also monotonically increase from all 0s to all 1s, and the theoretical values are input to the test section 6 and input to the test section input terminal 21 in FIG. reach. Figure 4 is n-4 in Figure 1.
FIG. 4 is an operation timing chart of the test section 6 at the time of the test section 6;

Below, the operation in the case of n-4 bits in Fig. 3 is explained in the fourth section.
This will be explained using figures.

The high-order 3 bits of the 4-bit test section input terminal 21 in FIG. 3 are used as D inputs, and the output logic value of the D flip-flop 31 to which the LSB is clocked increases monotonically from 0 to 7 as shown in FIG. . Also, D flip-flop 3
The output logic value of D flip-flop 32 is delayed by one clock period than the output logic value of D flip-flop 31, so when viewed on the same time axis as shown in FIG.・The value is always 1 smaller than the output logic value of the flop 31. Therefore, the output logic value of the 4 bits of the subtracter 33 is 1, that is, the upper 3 bits are O and the LSB is 1. Therefore, the NOT circuit 34 receives the logic value l and outputs the logic value 0, and the NOR circuit 35 receives all the logic values 0 at its 3-bit input terminal and outputs the logic value 1, and the test section output terminal Figure 1 test round 8 through 36
has a logical value of 1. If analog input terminal 3 or A
If there is a failure, poor contact, or contact between adjacent bits in either the input/output terminal of the /D converter 4 or the input terminal of the digital LSI 5, the output logical value of the 4 bits of the subtracter 33 will be l.
, and the logical value of test round 8 becomes 0.

As described above, according to this embodiment, the upper (n-1) bits of the test section input terminal 21 are connected to the digital LS 15.
A D flip-flop 31 whose clock input is the LSB, and an output terminal of the D flip-flop 31 whose clock input is the LSB.
A D flip-flop 32 whose clock input is the test section input terminal 21 (7) LSB, and the output logic value of the D flip-flop 31 and the D flip-flop 3.
A subtracter 33 that takes the difference between the output logical values of the subtracter 33 and the NOT circuit 34 that takes the LSB of the output terminal of the subtractor 33 as an input, and a NOT circuit 34 that takes the difference between the output terminals of the subtractor 33 and the upper (n-2) bits of the output terminal.
NOR circuit 35 whose input is the output terminal of
By providing a test section output terminal 36 connected to the output terminal of the analog input terminal 3 and the A/D
Wiring for detecting failures and poor contacts between the input/output terminals of the converter 4 and the n-bit input terminals of the digital LSI 5, and further detecting contacts between adjacent bits of each of the terminals that could not be detected in the first embodiment. Tests and operation tests for all output logic values of the A/D converter 4 can be performed.

A third embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 is a block diagram of a board test circuit in a third embodiment of the present invention.

In FIG. 5, 41 is a board, and on the board 41 there is a digital
There is a test section 45 connected to the n-bit output terminal of the digital signal processing section 44 . The test section 45 includes the D/A converter 4
It is connected to the n-bit input terminal of D/A 3 and at the same time to one or more test rounds 46 on the board 41.
The output end of the converter 43 is connected to an analog output terminal 47. 48 is a voltmeter that measures the voltage at the analog output terminal 47.

FIG. 6 is a circuit diagram of the test portion of FIG. 5 in a third embodiment of the present invention.

In FIG. 6, 51 is an n-bit test section input terminal. Reference numeral 52 denotes an m-bit test signal input terminal, which is connected to the input terminal of the decoder 53. The n-bit output terminal of the decoder 53 is input to n AND circuits 54, and the output terminal of the oscillator 55 is input to each of the n AND circuits 54. The n-bit output terminals of the n AND circuits 54 and the n-bit test section input terminal 51 are connected to a selector 56.
The test switching input terminal 57 is also connected to the selector 56. Also, test switching input terminal 5
7 is connected to the power supply via a pull-up resistor 58, and the n-bit output terminal of the selector 56 is connected to the n-bit test section output terminal 59. Note that the test switching input terminal 57 and the m-bit test signal input terminal 52 are connected to (m+1) test rounds 46 in FIG.

FIG. 7(a) is a circuit diagram of the decoder 53 in FIG. 6 when n=4 bits. In FIG. 7(a), in this case m=2 bits, 61a and 61b are decoder input terminals, and 62a and 62b are decoder input terminals 61, respectively.
This is the N07 circuit connected to a and 61b. 63a is NO
An AND circuit whose inputs are the output terminals of the T circuits 62a and 62b, and 63b is the decoder input terminal 61a and the NOT circuit 62.
63c is an AND circuit whose inputs are the output terminal of NOT circuit 62a and decoder input terminal 61b, and 63d is an AND circuit whose inputs are the output terminal of NOT circuit 62a and decoder input terminal 61b.
This is an AND circuit that takes as input. 64a, 64b, 64
c, 64d are AND circuits 63a, 63b, 63c, respectively.
This is a decoder output terminal connected to the output terminal of 63d. FIG. 7(b) is a circuit diagram of the oscillator 55 in FIG. In FIG. 7(b), 65 is a clock input terminal;
66 uses the clock input terminal 65 as a clock input, and the Q
A D flip-flop whose output is connected to the D input, 67 is an oscillator output terminal connected to the Q output of the D flip-flop 66.

The operation of the test circuit configured as described above will be explained below with reference to FIGS. 5, 6, 7(a), and 7(b).

First, in FIG. 5, during normal operation, an n-bit output signal from the digital signal processing section 44 is input to the test section 45 and reaches the test section input terminal 51 in FIG.

In FIG. 6, if no voltage is applied to the test round 46 of FIG. A signal from terminal 51 is output. Therefore, the same signal as the test section input terminal 51 is obtained at the test section output terminal 59, and as a result, in FIG. 5, the n-bit output signal of the digital signal processing section 44 is converted to analog by the D/A converter 43, An analog output signal is obtained from the analog output terminal 47.

Next, during testing, a voltage with a logical value of 0 is applied to the test round 46 in FIG. 5 connected to the test switching input terminal 57 in FIG. At this time, the logic value of the test switching input terminal 57 becomes 0 in FIG. FIG. 7(a) is a circuit diagram of the decoder 53 when n-4, and FIG. 7(b) is the circuit diagram of the oscillator 5.
FIG. 8 is an operational diagram of the decoder 53, the four AND circuits 54, and the oscillator 55 at the time of n-4 in FIG. Hereinafter, the decoder 53 at n-4 in FIG.
The operations of the four AND circuits 54 and the oscillator 55 will be explained using FIG. 7(a), FIG. 7(b), and FIG. 8. First, the oscillator 55 is connected to the clock input terminal 65 in FIG. 7(b).
The clock signal is divided into 1/2 and outputted to the oscillator output terminal 67. As shown in FIG. 7(a), when n-4, m-
2, for example, when the logic value of the test signal input terminal 52 in FIG. 6 is 1, that is, when each logic value of the decoder input terminals 61a and 61b in FIG. As shown in the second line of , decoder output terminals 64a, 64b,
Logic values 0.1.0.0 are obtained from 64c and 64d, respectively. Therefore, the logic value of only the second bit from the bottom toggles between 0 and 1 at the output terminals of the four AND circuits 54 in FIG.
A signal whose logic value is 0 is obtained for the other three bits. Even when the logic value of the test signal input terminal 52 is changed, as shown in FIG.
A signal is obtained in which the logical value of one bit toggles between 0 and 1, and the other three bits have logical values of 0.

However, the bit whose logical value toggles between O and 1 changes depending on the logical value of the test signal input terminal 52.

In the end, a signal is obtained from the test section output terminal 59 in FIG. 6 in which the logical value of only one bit toggles between O and 1, and the logical value of the other (n-1) bits is 0. is converted into an analog value by the D/A converter 43 at the output end of the test section 45 shown in FIG. 5, and an analog output signal is obtained from the analog output terminal 47.

From the analog output terminal 47, a signal that oscillates with the period of the output signal of the oscillator 55 shown in FIG. Bit loss is difficult to judge from the absolute value of the voltage of the analog output signal, but it is relatively easy to understand by measuring the AC amplitude as described above.

As described above, according to this embodiment, it is possible to switch between the normal operation and the test operation inside the digital LS 142, and during the test operation, the logical value is set to 1 bit for each of all bits of the D/A converter 43. By providing a test section 45 capable of giving a signal that toggles between
A wiring test to detect failures, poor connections, and contacts between adjacent bits between the n-bit output terminal of I5, the input/output terminal of the D/A converter 43, and the analog output terminal 47, and the wiring test of the D/A converter 4 You can perform a rough operation test.

Effects of the Invention As described above, according to the present invention, (1) a digital LSI connected to the output end of an A/D converter;
By providing a means inside the A/D converter to detect whether the output logical values of the A/D converter are all 0 or all 1 from the test round that is on the board and is connected to the output terminal of the digital LSI, Wiring tests to detect failures and poor connections between analog input terminals, A/D converter input/output terminals, and digital LSI input terminals, and operation tests when the A/D converter input voltage is at the minimum and maximum values. I can do it.

(2) Inside the digital LSI, the LSB of the output end of the A/D converter is used as a clock input, and all hits other than the LSB are input to the D.
a first D flip-flop whose input is the LSB of the output end of the A/D converter, and a second D flip-flop whose clock input is the output end of the first D flip-flop; 1st D flip-flop and 2nd D
A subtracter that takes the difference between each output logical value of the flip-flop, and means for detecting that the output logical value of the subtracter is 1 from a test round connected to the output end of the digital LSI on the board are provided. By doing so, we conduct wiring tests to detect failures, poor connections, and contacts between adjacent bits between analog input terminals, A/D converter input/output terminals, and digital LSI input terminals, and all outputs of the A/D converter. Operation tests for logical values can be performed.

(3) Digital L connected to the input end of the D/A converter
31 includes a decoder, n AND circuits each receiving the n-bit output terminal of the decoder, and n AND circuits.
An oscillator connected to each input terminal of the circuit, and n AND
A selector is provided to switch between the output end of the circuit and the n-bit output end of the digital signal processing section inside the digital LSI and output it to the input end of the D/A converter.
By providing a first test round connected to the input terminal of the decoder and a second test round connected to the terminal for switching the output signal of the selector on the board on which the SI is mounted, the output terminal of the digital LSI and the D Wiring tests to detect failures, poor contacts, and bad contacts between adjacent bits between the input/output terminals and analog output terminals of the /A converter, and D/A
You can perform a rough operation test of the converter.

[Brief explanation of the drawing]

1 is a block diagram of the board test circuit in the first and second embodiments of the present invention, FIG. 2 is a circuit diagram of the test section 6 of FIG. 1 in the first embodiment of the present invention, and FIG. 3 is a circuit diagram of the test section 6 of FIG. 1 in the second embodiment of the present invention, FIG. 4 is an operation timing chart of the test section 6 at n-4 of FIG. 1, and FIG. 5 is a circuit diagram of the test section 6 of FIG. A block diagram of a board test circuit according to a third embodiment of the present invention, FIG. 6 is a circuit diagram of the test section 45 of FIG. 5, FIG. 7(a) is a circuit diagram of the decoder 53 of FIG. 7(b) is a circuit diagram of the oscillator 55 in FIG. 6, FIG. 8 is an operational diagram of the decoder 53, four AND circuits 54, and the oscillator 55 at n-4 in FIG. 6, and FIG. FIG. 1 is a block diagram of a conventional board test circuit. 1... Voltage generator, 2... Board, 3
...Analog input terminal, 4...A/D
Converter, 5...Digital LSI, 6...
・Test section, 7...Digital signal processing section, 8.
...Test round, 21...Test section input terminal, 22...AND circuit, 23...
...OR circuit, 24a, 24b...Test section output terminal, 31.32...D flip-flop, 33...NX unit, 34... N. 7 circuits, 35...OR circuits, 36...
Test section output terminal, 41... Board, 42...
...Digital LSI, 43...D/A converter, 44...Digital signal processing section, 45...
...Test Department, 46...Test Round, 47
...Analog output terminal, 48...Voltmeter, 51...Test section input terminal, 52...
...Test signal input terminal, 53...Decoder,
54...n AND circuits, 55...
Oscillator, 56... Selector, 57...
Test switching input terminal, 58...Pull-up resistor, 59...Test section output terminal, 61a, 61b
...Decoder input terminals, 62a, 62b...
・NO7 circuit, 63a, 63b, 63c, 63d-・
-AND circuit, 64a, 64b, 64c, 64d--
Decoder output terminal, 65...Clock input terminal, 66...D flip-flop, 67...
...Oscillator output terminal, 71.72...Digital LS I, 73a, 73b, 73c, 78a. 78b, 78c =---・-input terminal, 74a
, 74b, 74c, 79a, 79b, 79cm-
-Manual register, 77a, 77b77c, 82a, 82
b, 82cm output register, 76a76b, 76c, 8
1a, 81b, 81c...=...output terminal, 75.80
...Digital signal processing section, 83.85...
...Test input terminal, 84.86...Test output terminal, 8788...Boundary scan path.

Claims (5)

[Claims] (1) A/D converter, digital LSI, and the A/D
a board on which a converter and the digital LSI are mounted; a digital signal processing section located inside the digital LSI and connected to the output end of the A/D converter;
A board comprising a test section located inside the board and connected to the output end of the A/D converter, and one or more test rounds located on the board and connected to the output end of the test section.・Test circuit. (2) The board test circuit according to claim 1, wherein the test section includes means for detecting when the output logic values of the A/D converter are all 0 and when they are all 1. . (3) The test section detects the LSB of the output terminal of the A/D converter.
a first D flip-flop which uses the clock input as a clock input and all bits other than the LSB as a D input; a second D flip-flop as an input, a first D flip-flop, and a second D flip-flop;
2. The board according to claim 1, further comprising: a subtracter that takes the difference between each output logic value of the flip-flop; and means for detecting that the output logic value of the subtracter is 1.
test circuit. (4) A digital LSI, a D/A converter, a board on which the digital LSI and the D/A converter are mounted, a digital signal processing section inside the digital LSI, and a digital signal processing section inside the digital LSI. n of the digital signal processing section
a test section connected to a bit output terminal and an n-bit input terminal of the D/A converter; and one or more test rounds located on the board and connected to the input terminal of the test section. board test circuit. (5) The test section includes a test signal input terminal connected to the first test round of the test rounds, a decoder having the test signal input terminal as an input terminal, and an n-bit output terminal of the decoder. n A each as input
an ND circuit, an oscillator connected to an input terminal of each of the n AND circuits, a test switching input terminal connected to a second test round of the test rounds, and an oscillator connected to an input terminal of each of the n AND circuits; It is characterized by comprising an output terminal and a selector that switches the n-bit output terminal of the digital signal processing section according to the logical value of the test switching input terminal and outputs it to the input terminal of the D/A converter. 5. The board test circuit according to claim 4.