JP2001141794A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of reducing dedicated pins or terminals connected to a board and carrying out a test of a connection state to the board. SOLUTION: This semiconductor integrated circuit 201 mounted on the board 100 comprises a normal circuit part composed of an internal logic part 113 and a circuit part 231 operating at the time of testing. The circuit part 231 has a test signal input pin 205 and a clock input pin 206. At the time of testing, a signal directing the test is inputted from the test signal input pin 205, and an edge detection circuit 211 detects the signal to latch signals inputted from respective input pins 102. A parallel/serial converting circuit 217 converts the latched signals into a serial signal and outputs the serial signal to output ins 103 through respective selector circuits 203 at one time in synchronization with a count value outputted from an N-ary counter circuit 214. By observing the signals inputted to the respective input pins 102 and the signals outputted to the respective output pins 103, the connection state between the board 100 and the semiconductor integrated circuit 201 can be judged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit suitable for performing a connection test between an integrated circuit and a substrate.

[0002]

2. Description of the Related Art With the miniaturization and high performance of electronic devices,
A large number of semiconductor integrated circuits (ICs (inte
grated circuit) or large scal
It is common to incorporate an e integrated circuit (hereinafter, generically referred to as a semiconductor integrated circuit). With respect to a substrate on which a semiconductor integrated circuit is mounted, a test for checking whether or not each terminal of each semiconductor integrated circuit is correctly connected to the substrate after mounting is conventionally performed.

[0003] Such a connection test between a semiconductor integrated circuit and a substrate is performed by inputting a test pattern for verifying logic to a predetermined terminal of a printed circuit board and checking the output pattern. ing. However, in recent years, as the scale of a semiconductor integrated circuit has increased, it has become difficult to realize a connection test of the semiconductor integrated circuit by a conventional method of inputting and verifying a test pattern. Therefore, recently, such a connection test using a method called boundary scan has become mainstream.

FIG. 3 shows a semiconductor integrated circuit on which boundary scan is performed and its periphery. Substrate 1
The semiconductor integrated circuit 101 mounted on the substrate 100
Input pins 102 ₁ , 102 ₂ ,.
_N , and output pins 103 ₁ , 103 ₂ ,..., 103 _M, and further, a test data input pin 104, a test data output pin 105, a transition state determination pin 106, a boundary Scan clock input pin 107 and TAP controller reset pin 10
8 are also connected. Each of the input pins 102 _1, 102 _2, and ...... 102 _N, the output pin 103 _1, 103 _2, ...... 103 _M, the corresponding registers 111 _1, 111 _2, ...... 111 _N, 112 _1, 1
12 _2, and it is connected to the internal logic 113 via ...... 112 _M. These registers 111 ₁ in a semiconductor integrated circuit within _{101, 111 2, ...... 111 N} , 11
_{2 1, 112 2, ...... 112} M are connected in this order so as to constitute a series circuit. The test data input pin 104 is connected to the Nth register 111 _N as one end of the series circuit, and the test data output pin 105 is connected to the Mth register 112 _M. A transition state determination pin 106, a boundary scan clock input pin 107, and a TAP controller reset pin 108 also provided on the substrate 100 side
It is connected to a TAP controller 115 provided inside. Based on these signals, the TAP controller 115 registers each of the registers 111 ₁ , 111 ₂ ,.
, 111 _N , 112 ₁ , 112 ₂ ,..., 112 _M are output.

In such a conventional semiconductor integrated circuit, T
The AP controller 115 is controlled to switch between a normal operation mode and a test mode. And in test mode, the test data input pin 104 registers 111 ₁ the input test data from, 111 _2, ...... 111 _N,
The connection test is performed by shifting to 112 ₁ , 112 ₂ ... 112 _M and setting a desired test pattern. The boundary scan is described in, for example, Japanese Patent Application Laid-Open Nos. 7-104035 and 7-159.
No. 483 discloses this.

[0006]

However, in a connection test using a method called a boundary scan, as shown in FIG. 3, pins connected to five dedicated pins in addition to ordinary input / output pins are connected to the semiconductor integrated circuit. Alternatively, a terminal needs to be provided. For this reason, there is a problem that a boundary scan cannot be performed in a semiconductor integrated circuit having an insufficient number of pins or terminals.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit capable of testing a connection state with a substrate by reducing the number of dedicated pins or terminals connected to the substrate side in the case of performing a boundary scan. is there.

[0008]

According to the first aspect of the present invention, (a) when mounting on a board, each input terminal connected to each input pin on the board side, and (b) mounting on the board. (C) an internal logic circuit for outputting a predetermined logic result to each output terminal in response to a signal given to each input terminal; (D) a parallel-serial conversion circuit for converting a signal input to each of the input terminals into a parallel signal by inputting the signal in parallel, and (e) corresponding between an output side of the internal logic circuit and each output terminal. In the normal mode other than the test mode for examining the connection state between the input pin and the input terminal or the output pin and the output terminal, the output terminal and the output side of the internal logic circuit are respectively connected,
In the test mode, a selector circuit for selecting a signal output from the parallel-serial conversion circuit as a common input signal, and a synchronizing circuit for outputting the converted serial signal from the parallel-serial conversion circuit at predetermined time intervals. Is provided in the semiconductor integrated circuit.

In other words, according to the first aspect of the present invention, a signal supplied from the input pin on the substrate side to the internal logic circuit through each input terminal in the normal mode is input to the parallel-serial conversion circuit, and the signal is synchronized in the test mode. The converted serial signal is output from the output terminal side to the output pin on the substrate side using a circuit. Thus, by checking the signal state of each input pin and the signal appearing at the output pin, it is possible to determine the electrical connection state between the input pin and the input terminal and between the output pin and the output terminal. Moreover, since only a signal for designating a test mode or a signal for operating a synchronous circuit needs to be input from the board side, the number of terminals or pins additionally connected to the board can be greatly reduced.

According to the second aspect of the present invention, (a) each input terminal connected to each input pin on the board when mounted on the board, and (b) each output on the board when mounted on the board. (C) an internal logic circuit that outputs a predetermined logic result to each output terminal in response to a signal given to each input terminal;
(D) a parallel-serial conversion circuit for converting a signal input to each of the input terminals into a parallel signal by inputting the signal in parallel, and (e) corresponding between an output side of the internal logic circuit and each output terminal. The output terminal and the output side of the internal logic circuit are connected in the normal mode other than the test mode, in which the connection state between the input pin and the input terminal or the output pin and the output terminal is checked. A selector circuit for selecting a signal output from a parallel-serial conversion circuit as a common input signal, a synchronizing circuit for outputting a serial signal after conversion from a parallel-serial conversion circuit at predetermined time intervals, and a test from a board side. Input the signal indicating the start of the mode and start the operation of the synchronous circuit at this timing. Re is and a synchronous circuit controller for stopping the operation in the semiconductor integrated circuit at the stage that has output the serial signal converted by a predetermined number greater than.

That is, in the invention according to claim 2, a signal supplied from the input pin on the substrate side to the internal logic circuit via each input terminal in the normal mode is input to the parallel-serial conversion circuit, and the signal is synchronized in the test mode. The converted serial signal is output from the output terminal side to the output pin on the substrate side using a circuit. Thus, by checking the signal state of each input pin and the signal appearing at the output pin, it is possible to determine the electrical connection state between the input pin and the input terminal and between the output pin and the output terminal. Moreover, since only a signal for designating a test mode or a signal for operating a synchronous circuit needs to be input from the board side, the number of terminals or pins additionally connected to the board can be greatly reduced. Further, the synchronous circuit control circuit inputs a signal indicating the start of the test mode from the substrate side and starts the operation of the synchronous circuit at this timing, and a predetermined number equal to or more than the number corresponding to the number of input terminals The operation is stopped at the stage when the converted serial signals are output by the number.

Therefore, by making the signal applied to each output pin via the selector circuit in this stopped state a specific signal, for example, the power consumption of the semiconductor integrated circuit can be suppressed to a low level thereafter. That is, this semiconductor integrated circuit can not only check the connection state of the input pins and the output pins after mounting on the board, but also stop the entire semiconductor integrated circuit even after it is determined that there is no problem in mounting. When the state is set, a predetermined effect such as suppressing power consumption can be obtained only by setting the test mode and leaving the apparatus in the test mode. Moreover, if you cancel the test mode,
Normal operation can be started.

The reason why the operation is stopped when the converted serial signal is output by a predetermined number equal to or greater than the number corresponding to the number of input terminals is not necessarily the number of input terminals. Means that there is no need to stop the operation after simultaneously outputting the converted signals to the number corresponding to the number. For example, if the predetermined number is an integral multiple of the number of input terminals, it is possible to repeat the test by the multiplication factor. For example, by changing the signal applied to the input pin side for each, it becomes more complicated. Tests can be performed.

According to a third aspect of the present invention, in the semiconductor integrated circuit of the second aspect, the converted serial signal output from the parallel-serial conversion circuit in a state where the operation of the synchronous circuit is stopped by the synchronous circuit control circuit. Is characterized in that a corresponding input signal is set so as to have a DC level.

This is to suppress the power consumption of the semiconductor integrated circuit while the operation of the synchronous circuit is stopped by the synchronous circuit control circuit as described above. You are free to set the output pin to any other signal state to reduce power consumption or achieve other effects.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit of the second aspect, the synchronous circuit control circuit is a counter for counting a number equal to the total number of input terminals.

That is, if a counter that counts a number equal to the total number of input terminals is used, the test can be easily completed in the shortest time.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, the input terminals are connected in parallel with signal lines connected from the input terminals to the respective input terminals of the internal logic circuit. A latch circuit for latching an input signal is provided, and an output of the latch circuit is input to a parallel-serial conversion circuit.

By providing such a latch circuit, it is not necessary to hold a predetermined signal at the input pin for a long time.
The load on the input control circuit for this purpose can be reduced.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit of the second aspect, the signal indicating the start of the test mode is a binary signal having a different signal level between the normal mode and the test mode. Is characterized by detecting a start of the test mode by inputting a signal indicating the start of the test mode and detecting a predetermined rising or falling edge.

That is, in the present invention, for example, the normal mode is a signal "0" and the test mode is a signal "1".
It is assumed that a signal of such a signal form as described above is input to a semiconductor integrated circuit. The edge detection circuit is a circuit that detects a change in the signal level in such a case. Unlike such a signal, when a trigger signal dedicated to the test mode is input, such a measure can be omitted.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows the configuration of a semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 1, the same portions as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. This semiconductor integrated circuit 201 is
Input Pin 102 ₁ 0 side, 102 _2, and ...... 102 _N, the output pin 103 _1, adapted for connection via the connection means (not shown) and ...... 103 _M. Input pins 102 ₁ , 1
02 _2, ...... 102 _N is adapted to be connected to the internal logic (logic circuitry) 113 disposed inside the semiconductor integrated circuit 201. The output pins 103 ₁ ,..., 10
3 _M is the corresponding internal selector circuit 203 ₁ ,.
03 _M is connected to the internal logic 113.

The semiconductor integrated circuit 201 of this embodiment is connected to a test signal input pin 205 and a clock input pin 206 on the substrate 100. A test signal 2 is input from the test signal input pin 205 to the semiconductor integrated circuit 201.
07 is input. A clock pulse 208 is input from the clock input pin 206. Inside the semiconductor integrated circuit 201, an edge detection circuit 211 for newly detecting an edge of the test signal 207, and input pins 102 ₁ , 102 ₂ ,.
A data latch circuit 213 that latches a signal input from _N and an edge detection circuit generation pulse 212 as an output signal of the edge detection circuit 211 in synchronization with a clock pulse 208, and a clock generated by the edge detection circuit generation pulse 212 of the edge detection circuit. An N-ary counter circuit 214 for counting in synchronization with the pulse 208;
14 and the data latch circuit 2
13 is provided with a parallel-serial conversion circuit 217 which receives the latch data 216 and the clock pulse 208 output from the circuit 13 and converts the parallel data into serial data. The serial signals 218 output from the parallel-serial conversion circuit 217 are input to the corresponding selector circuits 203 ₁ ,..., 203 _M so that the connection test is performed in the test mode in which the test signal 207 is turned on. Has become.

As described above, the semiconductor integrated circuit 20 of this embodiment is
Reference numeral 1 denotes input pins 102 ₁ , 1 provided on the substrate 100 side.
02 _2, ... 102 _N and output pins 103 _1, ... 10
In addition to 3 _M, also it would be connected to the test signal input pin 205 and a clock input pin 206 provided on the substrate side. The clock input pin 206 is used when the semiconductor integrated circuit 201 to be tested needs an external clock pulse as a normal operation.
This pin is required regardless of the connection test. Therefore, in a semiconductor integrated circuit that originally requires input of a clock pulse, the clock input pin 206 can be used for testing. Therefore, in such a case, only the test signal input pin 205 is newly required.
This makes it possible to add one terminal or pin on the semiconductor integrated circuit side. In all other cases,
Only two additional terminals or pins are required on the semiconductor integrated circuit side to perform the test.

FIG. 2 shows the signal generation timing of each part of the semiconductor integrated circuit of this embodiment. When a test of the semiconductor integrated circuit 201 is performed, the test signal 207 changes from a low level (“OFF”) to a high level (“ON”) at a predetermined time t ₁ as shown in FIG. . Assuming that a clock pulse 208 (FIG. 2B) is generated with a phase and a cycle as shown in FIG. 2B, the edge detection circuit 211 detects the edge of the test signal 207, and first rising time t ₂ from the edge detection circuit generates a pulse 212 of launch (FIG. 2 (c)). Edge detection circuit generates a pulse 212, falls at a time t ₃ after a lapse of a period of time corresponding to one cycle of the clock pulse 208.

The data latch circuit 213 for inputting the edge detection circuit generates a pulse 212, the output of the latch data 216 yet to be outputted even if the latch data which is input to the time t ₃ (see FIG. 2 (d)) Invalid. That is, until the time t ₃ , each input pin 10
21 ₁ , 102 ₂ ,..., 102 _N to the data latch circuit 21
No data is input to 3. The N-ary counter circuit 214 that inputs the clock pulse 208 holds the count value 215 (FIG. 2E) at “0” until the edge detection circuit generation pulse 212 falls. After time t ₃ , the count value 215 is counted up from “1” each time the clock pulse 208 rises. However, in this embodiment, the input pin 1
After counting up by a numerical value equal to the total number N of 02 ₁ , 102 ₂ ,..., 102 _N , the count value 215 is held at the numerical value “N”. The reason will be described later.

By the way, when the test signal 207 is input to the test signal input pin 205 and the connection test is started, the input pins 102 ₁ , 102 ₂ ,.
.. 102 _N are latched by the data latch circuit 213 and their values are held. The latched signal is supplied to the parallel-serial conversion circuit 2
17 are input to respective input pins 102 ₁ , 10 2
2 ₂ ,..., 102 _N
Serial signal 218 (FIG. 2 (f)) as a serial signal sequence sequentially selected one by one in synchronization with the rise of 8
Is converted to The serial signal 218 is commonly input to the selector circuits 203 ₁ ,..., 203 _M. The range of the circuit component surrounded by the broken line in FIG. 1 is the circuit portion 231 that operates during the test.

[0030] That is, while specifically from time t ₃ of one period of the clock pulse 208, the count value 215 becomes "1". The parallel-serial conversion circuit 217 is
The signal “1” as the count value 215 is input to perform parallel-serial conversion, and the signal input to the input pin 102 ₁ is input to all the selector circuits 203 ₁ for one cycle of the clock pulse 208 from the next time t _4. , ..., to input in common to 203 _M. These selector circuits 203 ₁ ,.
, 203M are _supplied with a test signal 207. In this test state, the serial signal 218 is selected instead of the output of the internal logic 113. Therefore, from time t ₄ , clock pulse 2
08 of one period elapsed time t ₅ all of the selector circuit 203 ₁ until the, ..., input pin 102 ₁ a 203 _M
, A serial signal 218 (in FIG. 2, this is represented as signal “* 1”) is output.

Similarly, at the next time t_FiveFrom the clock
Time t when one cycle of luth 208 elapses₆Until then,
Selector circuit 203₁, ......, 203_MFrom input pin
102 _TwoSignal 218 as a signal input to
(In FIG. 2, this is represented as a signal “* 2”.)
Is output. In the same manner,
Each time one cycle of the pulse 208 elapses, the input pin 102₁,
102_Two, ... 102_NThe signals input to
Circuit 203₁, ......, 203_MOutput in common from
02_NWhen the signal input to the
State will be maintained.

On the other hand, the semiconductor integrated circuit 201
During normal operation, the input pin 102₁,
102_Two, ... 102_NEach signal input to
Is supplied to the internal logic 113, and as a result
Output signal 221 output from ₁, 221_Two…… 221_M
Are the corresponding selector circuits 203₁, ......, 20
3_MIs input to In this normal state these select
Data circuit 203₁, ......, 203_MTest signal 207
Not force. Therefore, the selector circuit 203₁,
............ 203_MIs the output signal 221₁, 221_Two, ... 22
1_MAnd output pin 103₁, 103_Two, ... 103_M
Are output to the corresponding ones.

The manner of checking the connection with the pins on the substrate 100 side in such a semiconductor integrated circuit 201 will be described. In the test mode, the same signals are commonly output from the respective selector circuits 203 ₁ ,..., 203 _{M as} described above. Therefore,
While the serial signal 218 output from the parallel-serial conversion circuit 217 changes the signal state from “0” to “1” or “1” to “0”, each output pin 1
Observe the signal change of 03 ₁ ,..., 103 _M , and if there is a pin 103 that does not show the same signal change, the output pin 103 and the corresponding pin or terminal of the semiconductor integrated circuit 201 are not connected. Or the connection may not be good.

The input pins 102 ₁ , 102 ₂ ,..., 1
02 when added _N to the signal, for example all "1" or all "0", the output pin 103 _1, all in all intervals varying from ...... 103 _M to "N" from the count value 215 is "1""1 Or "0" signal should be output. Regardless of this, when there is a case where the signal state is inverted only during a section where the count value 215 indicates a predetermined value, the input pins 102 ₁ , 102 ₂ ,.
The pin corresponding to the value of 2 _N and the semiconductor integrated circuit 2
01 may not be connected or may not be connected well.

Of course, when the test cannot be performed in the test mode, the test signal input pin 205
There is a possibility that the connection between the clock input pin 206 and the semiconductor integrated circuit 201 is not made or is not connected well.

Incidentally, the semiconductor integrated circuit 20 of this embodiment is
1 is a normal mode other than the test mode,
7 is turned off (see FIG. 2A). By turning on the test signal 207 in a predetermined case regardless of the normal mode, it is possible to take measures to reduce the power consumption of the semiconductor integrated circuit 201 mounted on the substrate 100. That is, the specific semiconductor integrated circuit 2 on the substrate 100
When setting 01 to an unused state from a certain point, the test signal 207 applied to the test signal input pin 205 of the semiconductor integrated circuit 201 is turned on from that point. On the other hand, the signal applied to the input pin 102 _N is set to a DC level signal state.

Thus, the same operation as in the test mode described above is started, and the N-ary counter circuit 214 counts up the count value 215 to "N" and stops. In this stopped state, all the selector circuits 203 ₁ ,
......, the output pin 103 ₁ from 203 _M, signal is output to ... 103 _M becomes DC level. Since the signal states of the output pins 103 ₁ ,..., 103 _M are all at the DC level, the power consumption of the semiconductor integrated circuit 201 can be significantly reduced.

Of course, for some of the semiconductor integrated circuits 201 (only one is shown in FIG. 1 for simplicity) mounted on the substrate 100, the operation is restarted at the time of the restart. If the signal 207 is turned off, a normal operation can be performed thereafter.

In the embodiment described above, the test signal 207 is switched from the off state to the on state only once during the test mode, and the edge detection circuit 211 generates the edge detection circuit generation pulse 212 only once. However, the present invention is not limited to this. For example, input pin 102 _1, 102 _2, a cycle of time in which a slight margin to the time count to the stop of the N-ary counter circuit 214 determined by the generation period of the ...... 102 _N of the total number "N" and the clock pulse 208 Test signal 207
.., 102 _N in response to changing the state of the signal applied to the input pins 102 ₁ , 102 ₂ ,. All may be done.

Of course, if it is not necessary to particularly reduce the power consumption after the test or the normal operation, it is not necessary to adopt a circuit configuration for stopping the self-running of the N-ary counter circuit 214. It is.

[0041]

As described above, claims 1 to 6 are described.
According to the described invention, a signal supplied from the input pin on the substrate side to the internal logic circuit via each input terminal in the normal mode is
The signal is input to the parallel-serial conversion circuit, and in the test mode, the converted serial signal is output from the output terminal side to the output pin on the substrate side using a synchronous circuit. Thus, by checking the signal state of each input pin and the signal appearing at the output pin, it is possible to easily determine the electrical connection state between the input pin and the input terminal and between the output pin and the output terminal. Moreover, since only a signal for designating a test mode or a signal for operating a synchronous circuit needs to be input from the board side, the number of terminals or pins to be additionally connected to the board can be greatly reduced, and wiring and wiring on the board side The terminal design on the semiconductor integrated circuit side can be simplified.

According to the second aspect of the present invention, the synchronous circuit control circuit inputs a signal indicating the start of the test mode from the substrate side and starts the operation of the synchronous circuit at this timing. The operation is stopped when the converted serial signal is output by a predetermined number equal to or greater than the number corresponding to. Therefore, by making the signal applied to each output pin via the selector circuit in this stopped state a specific signal, for example, the power consumption of the semiconductor integrated circuit can be suppressed to a low level thereafter. That is, this semiconductor integrated circuit can not only check the connection state of the input pins and the output pins after mounting on the board, but also stop the entire semiconductor integrated circuit even after it is determined that there is no problem in mounting. When the state is set, a predetermined effect such as suppressing power consumption can be obtained only by setting the test mode and leaving the apparatus in the test mode. In addition, when the test mode is released, normal operation can be started.

Further, according to the second aspect of the present invention, the operation is stopped when the converted serial signal is output by a predetermined number equal to or greater than the number corresponding to the number of input terminals. Therefore, for example, if the predetermined number is an integral multiple of the number of input terminals, it is possible to repeat the test by the multiplication factor, and to change the signal applied to the input pin side for each of them. This has the effect that a more complicated test can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing signal generation timing of each part of the semiconductor integrated circuit of the present embodiment.

FIG. 3 is a schematic configuration diagram showing a conventional semiconductor integrated circuit on which boundary scan is performed and its periphery.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 substrate 102 input pin 103 output pin 113 internal logic 201 semiconductor integrated circuit 203 selector circuit 205 test signal input pin 206 clock input pin 207 test signal 211 edge detection circuit 213 data latch circuit 214 N-ary counter circuit 217 parallel-serial conversion circuit 231 Circuit part that operates during test

Claims (6)

[Claims] 1. An input terminal connected to each input pin on the board when mounted on a board, and an output terminal connected to each output pin on the board when mounted on the board. An internal logic circuit that outputs a predetermined logic result to each output terminal in response to a signal given to each input terminal; and converts a signal input to each of the input terminals into a serial signal by inputting the signal in parallel A parallel-serial conversion circuit, and a test mode arranged between the output side of the internal logic circuit and each of the output terminals to check a connection state between the input pin and the input terminal or between the output pin and the output terminal. In the normal mode other than the above, the output terminal and the output side of the internal logic circuit are connected respectively, while in the test mode, the signal output from the parallel-serial conversion circuit is output. A selector circuit for selecting as a common input signal, the parallel - semiconductor integrated circuit characterized by comprising a synchronization circuit for outputting a serial signal converted from the serial converting circuit at a predetermined time interval. 2. An input terminal connected to each input pin on the board when mounted on a board, and an output terminal connected to each output pin on the board when mounted on the board. An internal logic circuit that outputs a predetermined logic result to each output terminal in response to a signal given to each input terminal; and converts a signal input to each of the input terminals into a serial signal by inputting the signal in parallel A parallel-serial conversion circuit, and a test mode arranged between the output side of the internal logic circuit and each of the output terminals to check a connection state between the input pin and the input terminal or between the output pin and the output terminal. In the normal mode other than the above, the output terminal and the output side of the internal logic circuit are connected respectively, while in the test mode, the signal output from the parallel-serial conversion circuit is output. A selector circuit for selecting as a common input signal; a synchronizing circuit for outputting a converted serial signal from the parallel-serial conversion circuit at predetermined time intervals; and a signal indicating a start of a test mode from the substrate side. At this timing, the operation of the synchronization circuit is started, and the operation is stopped at the stage where the converted serial signal is output by a predetermined number equal to or greater than the number corresponding to the number of the input terminals. A semiconductor integrated circuit, comprising: a circuit control circuit. 3. A corresponding input signal is set so that a converted serial signal output from the parallel-serial conversion circuit has a DC level in a state where the operation of the synchronization circuit is stopped by the synchronization circuit control circuit. 3. The semiconductor integrated circuit according to claim 2, wherein: 4. The semiconductor integrated circuit according to claim 2, wherein said synchronous circuit control circuit is a counter for counting a number equal to the total number of said input terminals. 5. A latch circuit for latching signals input from these input terminals in parallel with signal lines connected from said input terminals to respective input terminals of said internal logic circuit. The output is the parallel-
3. The semiconductor integrated circuit according to claim 1, wherein the signal is input to a serial conversion circuit. 6. A signal indicating the start of the test mode,
The signal is a binary signal having a different signal level between the normal mode and the test mode. The edge detection circuit inputs a signal indicating the start of the test mode and detects a predetermined rising or falling edge to start the test mode. 3. The semiconductor integrated circuit according to claim 2, wherein: