JPH0444259A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0444259A
JPH0444259A JP14850990A JP14850990A JPH0444259A JP H0444259 A JPH0444259 A JP H0444259A JP 14850990 A JP14850990 A JP 14850990A JP 14850990 A JP14850990 A JP 14850990A JP H0444259 A JPH0444259 A JP H0444259A
Authority
JP
Japan
Prior art keywords
thin film
window
sputtering
electrode
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14850990A
Other languages
Japanese (ja)
Inventor
Norio Yamamoto
憲郎 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14850990A priority Critical patent/JPH0444259A/en
Publication of JPH0444259A publication Critical patent/JPH0444259A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the contact resistance of a bulk Si-Al electrode by sputtering a CrSiX thin film on an Si substrate in which an electrode forming opening window is opened at an insulating film, annealing it to modify it to a thin layer, patterning it to form a resistor, removing an SiO2 layer generated in the bottom of the window, sputtering Al, patterning it, and forming electrodes on an electrode forming region and in the window. CONSTITUTION:An Si substrate 1 is thermally oxidized by a normal method, an oxide insulating film 2 of 400Angstrom of thickness is formed, and an electrode forming opening window 3 is opened by selective etching (a). An output sputtering is conducted at 0.5kW of output in Ar of 10mTorr for 10 min to form a CrSiX thin film 4 of 200Angstrom of thickness is formed (b). Thereafter, after the surface of the thin film is modified to a CrSiXNO thin film, and a thin film resistor 5 is formed by selectively reactive ion etching (c). In the substrate of this state, a spontaneously oxidized SiO2 thin film present at the bottom of the window 3 is removed. Then, the entire surface is covered with Al 900Angstrom thick by Al sputtering, selectively wet etched, and Al electrodes 6, 6' are formed in the window 3 and in the electrode forming region of the resistor 5 (d).

Description

【発明の詳細な説明】 〔概 要〕 CrSix (xは1〜2の範囲の数を表すン薄膜抵抗
体を有する半導体装置の製造方法に関し、バルクSi 
−A!電極の接触抵抗を改良することを目的とし、 N2および02の混合ガス中で400〜480℃に加熱
して、CrSi工薄膜の表面をCrSixN(]薄層に
改質し、0.5〜5.0%HFで処理した後に、へβ電
極を形成するように構成する。
Detailed Description of the Invention [Summary] CrSix (x represents a number in the range of 1 to 2)
-A! In order to improve the contact resistance of the electrode, the surface of the CrSi thin film was modified to a CrSixN(] thin layer by heating to 400-480°C in a mixed gas of N2 and 02, and the contact resistance was 0.5-5. After processing with .0% HF, a β electrode is formed.

〔産業上の利用分野〕[Industrial application field]

本発明は、crs1M薄膜抵抗体を有する半導体装置の
製造方法に関する。近年、薄膜抵抗体は、シート抵抗が
、IKΩ/口以上で、かつ抵抗の温度係数が±1100
pp/を程度に小さいことが要求されている。これには
CrSixまたは[:rSi、0(xは1〜2の範囲の
数を表す〉が使用される。
The present invention relates to a method for manufacturing a semiconductor device having a crs1M thin film resistor. In recent years, thin film resistors have a sheet resistance of IKΩ/unit or higher and a temperature coefficient of resistance of ±1100.
pp/ is required to be as small as possible. CrSix or [:rSi, 0 (x represents a number in the range 1 to 2) is used for this.

〔従来の技術〕[Conventional technology]

バルクS1の表面には自然酸化されて生成した5102
薄層が存在する。これを除去する目的で、Cr51M抵
抗体を有するSi基板をHF処理すると、[r3iX薄
膜まで溶解されてしまう。そのため従来はCr5lX抵
抗体を有する半導体装置にHF処理を行うことがなかっ
た。従ってバルクSi −Aj!電極間の接触抵抗が大
きい欠点があった。
5102 generated by natural oxidation on the surface of bulk S1
A thin layer is present. When a Si substrate having a Cr51M resistor is subjected to HF treatment for the purpose of removing this, the [r3iX thin film is also dissolved. Therefore, conventionally, a semiconductor device having a Cr5lX resistor has not been subjected to HF treatment. Therefore, the bulk Si −Aj! The disadvantage was that the contact resistance between the electrodes was large.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

本発明は、crslK薄膜の表面を、導電性を保ちなが
ら改質するとともに、改質された薄層を溶解せずに、S
i基板の開口窓の底の自然酸化SlO□薄層を除去でき
るHF処理条件を求めて、バルク5i−Aβ電極の接触
抵抗を改良することを目的とする。
The present invention modifies the surface of a crslK thin film while maintaining its conductivity, and also allows S
The purpose of this study is to find HF treatment conditions that can remove the naturally oxidized SlO□ thin layer at the bottom of the opening window of the i-substrate, thereby improving the contact resistance of the bulk 5i-Aβ electrode.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題は、CrSix薄膜抵抗体を有する半導体装置
の製造方法であって、 (イ)絶縁膜に電極形成用開口窓をあけた31基板上に
、CrSix (xは1〜2の範囲の数を表す)薄膜を
スパッタリングし、(ロ)N2および02の混合ガス中
で400〜480℃においててニールして、Cr5lX
薄膜の表面をCr51.NO(xは1〜2の範囲の数を
表す)薄層に改質して、CrSix薄膜をバターニング
して抵抗体を形成し、(ハ)0.5〜5.0%HFで処
理して、開口窓の底においてバルクS1の表面が自然酸
化されて生成したSin、薄層を除去し、(ニ)Afを
スパッタリングし、バターニングして、CrSix薄膜
抵抗体の電極形成領域および開口窓に電極を形成する工
程を含むことを特徴とする方法によって解決することが
できる。
The above problem is a method for manufacturing a semiconductor device having a CrSix thin film resistor, and (a) CrSix (x is a number in the range of 1 to 2) Cr5lX
The surface of the thin film is coated with Cr51. Modified into a thin layer of NO (x represents a number in the range of 1 to 2), patterned the CrSix thin film to form a resistor, and (c) treated with 0.5 to 5.0% HF. Then, at the bottom of the opening window, the surface of the bulk S1 is naturally oxidized and the thin layer of Sin is removed, and (iv) Af is sputtered and buttered to form the electrode forming area of the CrSix thin film resistor and the opening window. This problem can be solved by a method characterized by including a step of forming an electrode.

〔作 用〕[For production]

本発明によれば、CrSix薄膜がアニーリングされる
と、表面がCrSixN01層に改質される。CrS+
、NOは導電性を有し、しかも0.5〜5.0%HFに
溶解しない。CrSixのアニーリング温度は、400
℃より低いと改質に要する時間が長くなり、480℃よ
り高いとバルクS1に悪影響を与える。HFの濃度は、
0.5%より薄いとバルクSi上の自然酸化5in2を
除去することができず、5.0%より濃いと改質された
CrSixNOも消耗するのでCrSix薄膜にダメー
ジを与える。
According to the present invention, when the CrSix thin film is annealed, the surface is modified into a CrSixN01 layer. CrS+
, NO has conductivity and is not soluble in 0.5-5.0% HF. The annealing temperature of CrSix is 400
If it is lower than 480°C, the time required for modification will be longer, and if it is higher than 480°C, it will have an adverse effect on the bulk S1. The concentration of HF is
If it is thinner than 0.5%, the natural oxidation 5in2 on bulk Si cannot be removed, and if it is thicker than 5.0%, the modified CrSixNO will also be consumed, thereby damaging the CrSix thin film.

空気が流入できるシリンダ形炉内でてニーリングを行う
とき、炉の軸方向に対して基板面が直角になるように配
置した複数の基板に対して、配列の方向に窒素を15〜
50β/ m i nの流量で送ることが便宜である。
When performing kneeling in a cylindrical furnace that allows air to flow in, nitrogen is applied in the direction of the array for 15 to 30 minutes to a plurality of substrates arranged so that the substrate surfaces are perpendicular to the axial direction of the furnace.
It is convenient to send at a flow rate of 50β/min.

流量が15A/minより少ないと、絶縁性のCr2O
3を生じ、50β/■inより多くしても効果が変らな
い。
If the flow rate is less than 15A/min, insulating Cr2O
3, and the effect does not change even if the amount is more than 50β/■in.

またAfをバターニングする83PO4ウェットエツチ
ング温度は40℃より低いとエツチング時間が長くなり
、60℃より高いとサイドエツチングをおこす。
Furthermore, if the 83PO4 wet etching temperature for patterning Af is lower than 40°C, the etching time will be long, and if it is higher than 60°C, side etching will occur.

この方法はバイポーラ型またはMOS型の半導体装置の
製造に使用することができる。
This method can be used to manufacture bipolar or MOS type semiconductor devices.

〔実施例〕〔Example〕

第1図に示すSi基板1は、常法によって熱酸化し、厚
さ4000人の酸化絶縁膜2を形成し、選択的エツチン
グにより電極形成用開口窓3をあけた(a)。
The Si substrate 1 shown in FIG. 1 was thermally oxidized by a conventional method to form an oxide insulating film 2 having a thickness of 4,000 yen, and an opening window 3 for forming an electrode was opened by selective etching (a).

lQ mTorrOAr中で、出力0.5KWで8カス
バツタリングを10分間行って、厚さ200人のCrS
+x薄膜4を形成した(b)。
CrS with a thickness of 200 mm was subjected to 8-cush bumper for 10 minutes at an output of 0.5 KW in lQ mTorrOAr.
+x thin film 4 was formed (b).

その後、図示しない内径15cmのシリンダ形開放炉内
に、基板面が炉の軸方向に対して直角となるように配置
し、ンリンダの一端から流量30A/+ninでN2を
導入しながら450℃で30分間アニーリングを行って
Cr5IX薄膜の表面をCrSiイNO薄層に改質した
後に、選択的反応性イオンエツチングによって薄膜抵抗
体5を形成した(c)。
Thereafter, the substrate was placed in a cylindrical open furnace (not shown) with an inner diameter of 15 cm so that the substrate surface was perpendicular to the axial direction of the furnace, and heated at 450°C for 30 minutes while introducing N2 from one end of the cylinder at a flow rate of 30 A/+nin. After annealing for a minute to modify the surface of the Cr5IX thin film into a CrSi-NO thin layer, a thin film resistor 5 was formed by selective reactive ion etching (c).

この状態の基板を1%HFで10秒間前処理して、開口
窓3の底に存在する自然酸化5iO7薄層を除去した。
The substrate in this state was pretreated with 1% HF for 10 seconds to remove the naturally oxidized 5iO7 thin layer present at the bottom of the opening window 3.

このとき薄膜抵抗体は影響を受けなかった。At this time, the thin film resistor was not affected.

次に、lQ mTorrのAr中で、出力3KWでAI
スパッタリングを行って全面に厚さ9000人のAlを
被着し、50℃のH,PO,で選択的ウェットエツチン
グを行い、開口窓3と薄膜抵抗体5の電極形成領域とに
、Al電極6.6′を形成した(d)。
Next, in Ar with lQ mTorr, AI with an output of 3KW
Sputtering is performed to deposit Al with a thickness of 9000 nm on the entire surface, and selective wet etching is performed with H, PO at 50° C. to form an Al electrode 6 in the opening window 3 and the electrode formation area of the thin film resistor 5. .6' was formed (d).

バルク5i−Al電極の接触面積4X6#−”について
の接触抵抗はlOΩであった。
The contact resistance of the bulk 5i-Al electrode with a contact area of 4×6#-” was 10Ω.

〔発明の効果〕〔Effect of the invention〕

本発明の方法によれば、Al電極形成前に開口窓の底の
バルクS1をHF前処理することができ、かつバルクS
iおよび(:rS I M薄膜と、Al電極との接触形
成を同時に行うことができる。これによって温度係数が
低く、高い抵抗の薄膜抵抗体を有するIC,すなわちD
/A、A/Dコンバータの開発に寄与するところが大き
い。
According to the method of the present invention, the bulk S1 at the bottom of the opening window can be pretreated with HF before forming the Al electrode, and the bulk S1 can be pretreated with HF before forming the Al electrode.
Contact formation between the i and (rS I M thin films and the Al electrodes can be performed simultaneously. This allows ICs with low temperature coefficients and high resistance thin film resistors, that is, D
/A, greatly contributed to the development of A/D converters.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の方法の実施態様を示す工程図である。 1・・・Si基板、    2・・・絶縁膜、3・・・
電極形成用開口窓、 4・・・Cr518薄膜、  5−=CrSiX薄膜抵
抗体、6・・・Al電極。
FIG. 1 is a process diagram showing an embodiment of the method of the present invention. 1...Si substrate, 2...insulating film, 3...
Opening window for electrode formation, 4...Cr518 thin film, 5-=CrSiX thin film resistor, 6...Al electrode.

Claims (1)

【特許請求の範囲】 1、CrSi_x薄膜抵抗体を有する半導体装置の製造
方法であって、 (イ)電極形成用開口窓をあけた保護膜を半導体基板上
に形成したのち、CrSi_x薄膜をスパッタリングし
、 (ロ)前記CrSi_x薄膜の表面をCrSi_xNO
薄層に改質して、前記保護膜上に薄膜抵抗体のパターン
を形成し、 (ハ)HFで処理して、開口窓の底に表出している半導
体基板の表面に形成された自然酸化膜を除去し、 (ニ)電極材料をスパッタリングし、パターニングして
CrSi_x薄膜抵抗体の電極形成領域および開口窓に
電極を形成する工程を含むことを特徴とする半導体装置
の製造方法。 2、CrSi_xNO改質を、N_2及びO_2の混合
ガス中で400〜480℃に加熱しながら行うことを特
徴とする、請求項1記載の方法。
[Claims] 1. A method for manufacturing a semiconductor device having a CrSi_x thin film resistor, which comprises: (a) forming a protective film with openings for electrode formation on a semiconductor substrate, and then sputtering a CrSi_x thin film; (b) The surface of the CrSi_x thin film is coated with CrSi_xNO
(c) treatment with HF to remove natural oxidation formed on the surface of the semiconductor substrate exposed at the bottom of the opening window; A method for manufacturing a semiconductor device, comprising the steps of: (d) sputtering and patterning an electrode material to form an electrode in an electrode formation region and an opening window of a CrSi_x thin film resistor. 2. The method according to claim 1, wherein the CrSi_xNO modification is carried out in a mixed gas of N_2 and O_2 while heating at 400 to 480°C.
JP14850990A 1990-06-08 1990-06-08 Manufacture of semiconductor device Pending JPH0444259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14850990A JPH0444259A (en) 1990-06-08 1990-06-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14850990A JPH0444259A (en) 1990-06-08 1990-06-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0444259A true JPH0444259A (en) 1992-02-14

Family

ID=15454357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14850990A Pending JPH0444259A (en) 1990-06-08 1990-06-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0444259A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5989970A (en) * 1994-06-08 1999-11-23 Nippondenso Co., Ltd. Method for fabricating semiconductor device having thin-film resistor
US6242792B1 (en) 1996-07-02 2001-06-05 Denso Corporation Semiconductor device having oblique portion as reflection
US6274452B1 (en) 1996-11-06 2001-08-14 Denso Corporation Semiconductor device having multilayer interconnection structure and method for manufacturing the same
US7312515B2 (en) 2003-06-11 2007-12-25 Ricoh Company, Ltd. Semiconductor apparatus including a thin-metal-film resistor element and a method of manufacturing the same
US7358592B2 (en) 2004-03-02 2008-04-15 Ricoh Company, Ltd. Semiconductor device
CN114792742A (en) * 2022-04-22 2022-07-26 深圳大学 Photoelectric sensor based on modified SnTe thin film and preparation method thereof

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5989970A (en) * 1994-06-08 1999-11-23 Nippondenso Co., Ltd. Method for fabricating semiconductor device having thin-film resistor
DE19520768B4 (en) * 1994-06-08 2006-09-28 Denso Corp., Kariya Method for producing a semiconductor device with thin-film resistor
US6242792B1 (en) 1996-07-02 2001-06-05 Denso Corporation Semiconductor device having oblique portion as reflection
US6274452B1 (en) 1996-11-06 2001-08-14 Denso Corporation Semiconductor device having multilayer interconnection structure and method for manufacturing the same
US7312515B2 (en) 2003-06-11 2007-12-25 Ricoh Company, Ltd. Semiconductor apparatus including a thin-metal-film resistor element and a method of manufacturing the same
US7718502B2 (en) 2003-06-11 2010-05-18 Ricoh Company, Ltd. Semiconductor apparatus including a thin-metal-film resistor element and a method of manufacturing the same
US7358592B2 (en) 2004-03-02 2008-04-15 Ricoh Company, Ltd. Semiconductor device
CN114792742A (en) * 2022-04-22 2022-07-26 深圳大学 Photoelectric sensor based on modified SnTe thin film and preparation method thereof
CN114792742B (en) * 2022-04-22 2024-04-02 深圳大学 Photoelectric sensor based on modified SnTe film and preparation method thereof

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