JPH0444237A - Manufacture of electric field effect transistor - Google Patents

Abstract

PURPOSE:To enable a gate whose section is in T or mushroom shape to be formed by forming a mask pattern using a second resist on a metal film which is provided on a first resist and then by forming a groove for cladding a gate metal at a first resist using the mask pattern of this metal film. CONSTITUTION:First, a tentative gate 12 is formed at a region where the gate on a semiconductor substrate 10 is formed (a). Then, a first resist 14 is spin- coated (b). Then, an Ni film 16 is formed on this first resist 14. Then, the second resist is spin-coated and a region which is positioned at an upper part of the tentative gate 2 is eliminated, thus forming a resist pattern (d). Then, the Ni film which exists at the opening of the resist is eliminated (e). Then, a groove 20 is formed by etching the first resist 14 (f). The tentative gate 12 within this groove 20 is eliminated by using a shock-absorbing fluoric acid (g). Then, a gate 22 is formed within the groove 20 by cladding a gate metal on an entire surface of the first resist 14 (h). Finally, the first resist 14 is eliminated, thus enabling only the gate 22 to remain on the semiconductor substrate 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a field effect transistor (hereinafter referred to as FET), and particularly to a method for manufacturing a gate having a T-shaped or mushroom-shaped cross section.

[Prior Art] Schottky junction FETs, so-called MESFETs, using compound semiconductors such as GaAs have been developed. This MESFET is suitable for miniaturization of gate length because of its simple structure and manufacturing process, and is widely used in elements with excellent high frequency characteristics and high-speed operation integrated circuits.

However, simply increasing the miniaturization of the gate length increases the electrical resistance of the gate, which on the contrary becomes a factor that impedes high-speed operation. Therefore, a method has been considered to form a gate having a T-shaped or pine mushroom-shaped cross section, with the lower part in contact with the active layer of the semiconductor being thinner and the upper part being thicker.

As these methods, for example, a method using a multilayer resist and direct writing using an electron beam, a method using focused ion beam lithography, or a method combining a temporary gate and a planarization technique are known.

On the other hand, in order to realize higher speed FETs, not only miniaturization of the gate length but also reduction of source resistance is an important issue. For this reason, a structure is generally used in which the active layer in the source/drain region is formed deeper and has a higher impurity concentration than the active layer under the gate.

However, the misalignment between the active layer (high concentration layer) in the source/drain region and the gate becomes a problem as the gate length becomes finer as described above. For this reason, self-lined MESFETs in which source/drain regions and gates are configured in a self-aligned manner are widely used.

Such self-lined MESFETs can be manufactured by implanting ions into a highly concentrated layer using the heat-resistant gate as a mask, then performing heat treatment to electrically activate the ion-implanted layer while leaving the heat-resistant gate as is, or using a temporary gate. After forming a high concentration layer ion implantation using this temporary gate as a mask,
It is manufactured by a method in which heat treatment is performed while the temporary gate or an inverted pattern of the temporary gate remains on the semiconductor substrate, and a gate is formed at the position where the temporary gate existed.

[Problems to be Solved by the Invention] However, in order to miniaturize the gate length and reduce gate resistance, when forming the gate with the above-mentioned T-shaped or pine mushroom cross-sectional shape, direct writing using a multilayer resist and an electron beam is difficult. Methods using ion beam lithography and methods using focused ion beam lithography require the use of special equipment such as electron beam or ion beam direct writing equipment.
There was a problem that the manufacturing process became complicated.

In addition, when manufacturing a heat-resistant gate type self-line MESFET, which is often used to reduce source resistance, the gate needs to withstand heat treatment (approximately 800 degrees Celsius) to activate the high concentration layer, as described above. Therefore, gate materials are limited to compounds based on W or Ta, which are high melting point metals, and the resistivity thereof is several tens of times higher than that of ordinary metals.

Therefore, the applicant of the present application previously proposed in Japanese Patent Application No. 1-120989 a method of forming gates by skillfully using image reverse photolithography.

In this manufacturing method, the resist remains at a constant thickness at the bottom, and the cross-sectional width becomes narrower toward the opening by combining a resist pattern for gate formation and a temporary gate. It is possible to form a gate having a T-shaped cross section using a simple process and without using a high-resistance heat-resistant material.

However, when forming a gate with a T-shaped cross section using image reverse photolithography, it is necessary to precisely control various parameters of image reverse photolithography, such as exposure amount, baking time, development time, etc. There is.

The present invention has been made in view of the above-mentioned prior art and the manufacturing method proposed by the present applicant, and its purpose is to provide a method for manufacturing an FET that can form a gate with a T-shaped cross section or a pine mushroom shape in a simple process. Our goal is to provide the following.

[Means for Solving the Problems] In order to achieve the above object, a method for manufacturing an FET according to the present invention includes a step of forming a temporary gate in a region on a semiconductor substrate where a gate is to be formed, and a step of forming a temporary gate on a region where a gate is to be formed. a step of applying a covering first resist to the surface of the semiconductor substrate; a step of forming a metal thin film on the first resist; a step of applying a second resist onto the metal thin film; A step of removing a region of the resist located above the temporary gate, a mask creation step of removing the metal film in the removed second resist region, and a metal film obtained in this mask creation step. a step of etching the first resist as a mask so as to expose a predetermined amount of the upper part of the temporary gate to form a groove; a step of removing the temporary gate in the groove; and a step of etching the first resist in the groove. The method is characterized by comprising a step of depositing a gate metal thinner than the resist, and a step of removing the first resist.

[Function] As described above, the FET manufacturing method of the present invention uses the second resist to create a mask pattern on the metal film provided on the first resist, and uses the mask pattern of this metal film to create a second resist. In this method, grooves for depositing gate metal are formed in resist No. 1, and a gate having a T-shaped cross section can be easily obtained without using special techniques such as image reverse photolithography.

[Embodiment] Hereinafter, a preferred embodiment of the method for manufacturing an FET according to the present invention will be described with reference to the drawings.

FIG. 1 is a partial cross-sectional view illustrating the method of manufacturing the FET in this embodiment.

First, as shown in FIG. 1(a), Si
A temporary gate 12 is formed using N, S i ON, S i 02, or the like.

Next, as shown in FIG. 1(b), a resist 14 of jfjl is applied with a spin code to a thickness such that the temporary gate 12 is completely covered.

Then, as shown in FIG. 1C, a Ni film 16 is formed as a metal thin film on this first resist 14 by vacuum evaporation or sputtering. As described later, this N
The i film 16 functions as a mask when etching the first resist 14.

After forming the Ni film 16, a second resist 18 is coated on the Ni film 16 using a spin code, exposed through a photomask, and developed to remove the region located above the temporary gate 12 and form the first resist 18. A resist pattern as shown in Figure (d) is created. Note that this resist pattern has a width such that the resist removed portion completely includes the temporary gate 12.

After forming the resist pattern in this way, as shown in FIG.
), the Ni film present in the openings of the resist is removed using hydrochloric acid or the like.

Then, as shown in FIG. 1(f), the temporary gate 12
Using the partially removed Ni film 18 as a mask, the first resist 14 is etched to form a groove 20 so that a predetermined amount of the upper part of the temporary gate 12 is exposed.

As an etching method, reactive ion etching (hereinafter referred to as 02RIE) using 02 plasma, whose etching rate can be controlled relatively easily, can be used.
By adjusting the pressure, the groove width can be set to be slightly wider than the opening width of the Ni film.

After forming the groove 20 in the first resist 14, as shown in FIG.
), the temporary gate 12 in this groove 20 is removed using buffered hydrofluoric acid.

Then, by depositing a gate metal such as aluminum on the entire surface of the first resist 14 by vacuum deposition or sputtering, a gate 22 is formed in the groove 20 as shown in FIG. 1(h).

Finally, by removing the first resist 14 using acetone or the like, only the gate 22 remains on the semiconductor substrate 10 as shown in FIG. 1(i).

As described above, by using the process of this example, it is possible to easily manufacture a gate having a T-shaped cross section.
A self-line MESFET can also be easily manufactured using such a temporary gate and a gate having a T-shaped cross section.

FIG. 2 is a partial sectional view showing the process of manufacturing this self-line type MESFET.

First, as shown in FIG. 2(a), Si
Temporary gates 12 such as N, S i ON, S i 02, etc. are formed.

Then, as shown in FIG. 2(b), a highly concentrated N-layer ion implantation resist 24 is applied using a spin code, exposed to light through a photomask, and developed to form a predetermined area near the temporary gate 12. Form grooves and create a mask pattern.

Then, as shown in FIG. 2(b), Sl 2 ions are implanted into the semiconductor substrate 10 using the resist 24 as a mask pattern.

In FIG. 2(b), the N layer immediately below the temporary gate 12 is previously formed by ion implantation before forming the temporary gate 12 on the GaAs substrate.

After removing the resist 24, the entire surface is coated with SiN or 5iON as shown in FIG. 2(C).

An annealing protective film 26 such as SiO2 is formed and heat treatment is performed to activate the N and N layers.

Finally, only this annealing protective film 26 is removed by wet etching or dry etching using plasma, and the source/drain regions are then etched through the steps shown in FIGS. 1(b) to (i). It is possible to obtain a self-line MESFET in which the gate is configured in a self-aligned manner, the gate length is shortened, and the gate resistance is reduced.

[Effects of the Invention] As explained above, according to the FET manufacturing method according to the present invention, a gate having a T-shaped cross section or a pine mushroom shape can be easily manufactured, and a self-line type ME using a metal gate can be easily manufactured. SFET etc. can be easily manufactured.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an embodiment of the FET manufacturing method according to the present invention, and FIG. 2 is an explanatory diagram of a self-line type FET manufacturing method using the same embodiment. 10... Semiconductor substrate 12... Temporary gate 14... First resist 16... N1 metal film 18... Second resist 20... Groove 22... Gate

Claims (1)

[Claims] A step of forming a temporary gate in a region on a semiconductor substrate where a gate is to be formed; a step of applying a first resist to the surface of the semiconductor substrate to cover the temporary gate; forming a metal thin film on the resist; applying a second resist on the metal thin film; removing a region of the second resist located above the temporary gate; a mask creation step for removing the metal film in a second resist region; and etching the first resist using the metal film obtained in this mask creation step as a mask so as to expose a predetermined amount of the upper part of the temporary gate. removing the temporary gate in the trench; depositing a gate metal thinner than the first resist in the trench; and removing the first resist. A method for manufacturing a field effect transistor, comprising: