JPH0443434A - Microprocessor - Google Patents

Abstract

PURPOSE:To execute plural programs without increasing a CPU core and without causing the collision of a data bus by providing plural register parts including accumulators, storing respective programs in said register parts and permitting a selection means to selectively connect the register parts to the CPU core. CONSTITUTION:The register parts L1 and L2 including the accumulators 1a, 2a, 1b and 2b are provided and the programs are held in the register parts. The selection means 7 selectively connects the register parts to the CPU core. In such a case, respective register parts L1 and L2 connected to a CPU internal bus 8 are sequentially switched, connected and are connected to the CPU internal bus 8 in the selection means 7 when a register switch instruction 9 is executed in the CPU core. The executed program is temporarily interrupted by using the detached register part and the content of the register part remains as it is while it is held. Thus, the register switch instruction 9 is executed again and the program can continuously be executed even if the register part is selected. Thus, plural programs can be executed.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention relates to a microprocessor that can execute multiple programs in parallel without installing multiple CPU cores. .

[Conventional technology]

In some conventional microprocessors, in order to simultaneously execute a plurality of programs, the number of CPU cores is increased by the number of programs to be executed.

FIGS. 3 and 4 show an example of the internal structure of a single-chip microcomputer that includes a built-in microprocessor that can simultaneously execute two programs.

In each figure, 10 is a single-chip microcomputer, 12 is a ROM in which a program is recorded, and 1
3 is RAM, 14 is peripheral I10.15 is built-in timer, 1
1a and σ11b are microprocessors that execute instructions. Further, 16 is an accumulator, 17 is a flag flip-flop, 18 is a general-purpose register, 19 is an instruction register, 20 is an instruction recorder, and 21 is a sieving logic unit.

In this configuration, the microprocessor consists of two CPU cores lla and 11b, each with a CPU core 11a.
, llb execute respective programs in the ROM.

Peripheral circuits other than the microprocessor are common.

(Problems to be Solved by the Invention) As described above, conventional microprocessors require multiple CPU cores in order to execute multiple programs, and the chip area increases by the increased number of CPU cores. It had the disadvantage of being large. Also, multiple CPUs
By implementing the core, it is also necessary to take measures to avoid data collisions that occur when reading and writing ROM-RAM.

This invention was made in order to solve the above-mentioned problems, and it is possible to execute at least one C++ program without causing data bus collision while executing multiple programs in parallel.
An object of the present invention is to provide a microprocessor that can be configured with a PU core.

[Means to solve the problem]

Register section L1 including an accumulator. A plurality of L2 and L3 are provided, each of which holds a program, and these register portions L'l, L2. L3 is selectively connected to the CPU core by selection means 7.

[Effect]

Each register section Ll, L2 . L3 is selectively connected to the CPU core by a selection means, and a program is selectively activated.

〔Example〕

FIG. 1 is a block diagram showing a connection configuration between a CPU core and a register section according to an embodiment of the present invention. In the figure, the accumulator 1a and the accumulator 1b are connected to the CPU internal bus 8 via the switching means S1, and similarly, the accumulator 2a and the accumulator 2b are connected to the switching means S2, the registers 3a and 3b are connected to the switching means S3, and the registers 4a and 2b are connected to the switching means S3. The register 4b serves as the switching means S4, and the registers 5a and 5b serve as the switching means S5.
, the program counter 6a and the program counter 6
b are respectively connected to the CPU internal bus 8 via switching means S6. Note that the switching means S] to S6 are selected by the register selection means 7. In this case, accumulator 1a.

Accumulator 2a, register 3a, register 4a,
A register 5a and a program counter 6a constitute a register section L1, and an accumulator 1b, an accumulator 2b, a register 3b, a register 4b, a register 5b, and a program counter 6b constitute a second register section L2.

When the second register section L1 is selected in this state and the program held in the second register section is executed, data input/output is performed by the accumulators 1a, 2a, and 2a constituting the selected register section L1. This is performed only for the register 3a, register 4a, register 5a, and program counter 6a, and each register constituting the second register section [2 is unselected.

As described above, when the register switching instruction 9 is executed in the CPtJ core, the selection means 7 selects the CPU
Each register section L1. connected to the internal bus 8. L2 is sequentially switched and selected, and is connected to the CPU internal bus 8.

The program that was being executed using the truncated register section will be temporarily interrupted, but the contents of that register section will remain retained, so register selection instruction 9 will be executed again. , even if that register section is selected, the program can continue to be executed.

FIG. 2 is a block diagram of a register portion of a CPU core showing an embodiment of the present invention, in which an accumulator, a register, and a program counter are collectively arranged in blocks, and the first to third register portions L1. The first to third register sections 11.12.13 constitute L2 and 13, respectively.
is connected to the CPU internal bus 8 via switching means SO.

The operation will be described below. Assuming that register section L1 is selected by selection means 7 and connected to CI]U internal bus 8 by executing register switching instruction 9, register section L2. Since L3 is not selected, data output of the program being executed is performed only in the register section 11. In this state, the register switching instruction 9 causes the register section [
2 is selected, the register section L2 is selected by the register selection means 7 and connected to the CPLI internal bus 8. The program being executed on the register section L1 is temporarily stopped, and the program on the register section L2 starts execution.

As described above, it becomes possible to execute programs in parallel by the number of increased register units.

In the example shown in Fig. 1 above, each register section is shown to have a configuration of two, but it may have two or more, and it is possible to execute a program for the multiplexed registers. effective.

The same applies to the example shown in FIG. 2, and the number of register sections may be three or more, and it becomes possible to execute programs in parallel by the number of increased register sections.

Further, in FIG. 3, the microprocessors 11a, 11
b and Ilo 14. Timer 15° ROM12. R.A.
Although a single-chip microcomputer configured with M13 or the like is shown as an example, it may be a single CPU core, and if the CPU core has the above-described configuration, the same effect will be achieved.

(Effects of the Invention) As explained above, according to the present invention, a program is stored in each of a plurality of register sections, and each register section is
Since it is selectively connected to the PU core, multiple programs can be executed without increasing the number of CPU cores and without causing data bus collision.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a register section including an accumulator inside a microprocessor according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a further embodiment of the present invention.
FIGS. 3 and 4 are diagrams showing an example of a conventional microprocessor. L1-L3...Register section, So, S1-S6
...Switching means, 7...Register selection means, 8...CPU internal bus, 9...Register switching instruction, 11a, 11b--・C
PIJ core. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a microprocessor that has a CPU core and executes a plurality of programs, a plurality of register sections including at least an accumulator are provided, each program is stored in each, and the register sections are selectively transferred to the CPU by a selection means. A microprocessor characterized by being connected to a core.