JPH0442731U - - Google Patents
Info
- Publication number
- JPH0442731U JPH0442731U JP8367690U JP8367690U JPH0442731U JP H0442731 U JPH0442731 U JP H0442731U JP 8367690 U JP8367690 U JP 8367690U JP 8367690 U JP8367690 U JP 8367690U JP H0442731 U JPH0442731 U JP H0442731U
- Authority
- JP
- Japan
- Prior art keywords
- recess
- metal layer
- semiconductor element
- insulating substrate
- glass material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011521 glass Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 230000003746 surface roughness Effects 0.000 claims 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Die Bonding (AREA)
Description
第１図は本考案に係る半導体素子収納用パツケ
ージの一実施例を示す断面図である。
１……絶縁基体、１ａ……凹部、２……蓋体、
５……金属層、６……封止用ガラス部材。
FIG. 1 is a sectional view showing an embodiment of a package for housing semiconductor elements according to the present invention. 1... Insulating base, 1a... Recess, 2... Lid,
5... Metal layer, 6... Glass member for sealing.
Claims (1)
粉末とガラス材とから成る金属層を被着させた半
導体素子収納用パツケージにおいて、前記絶縁基
体の凹部底面の表面粗さが中心線平均粗さＲａで
０．４μｍ≦Ｒａ≦１．０μｍであり、且つ前記
金属層のガラス材の量が８．０乃至１６．０重量
％であることを特徴とする半導体素子収納用パツ
ケージ。 In a package for housing a semiconductor element in which a metal layer made of gold powder and a glass material is coated on the bottom surface of a recess for accommodating a semiconductor element in an insulating substrate, the surface roughness of the bottom surface of the recess in the insulating substrate is a center line average roughness Ra. 0.4 μm≦Ra≦1.0 μm, and the amount of glass material in the metal layer is 8.0 to 16.0% by weight.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8367690U JP2515659Y2 (en) | 1990-08-07 | 1990-08-07 | Package for storing semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8367690U JP2515659Y2 (en) | 1990-08-07 | 1990-08-07 | Package for storing semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0442731U true JPH0442731U (en) | 1992-04-10 |
| JP2515659Y2 JP2515659Y2 (en) | 1996-10-30 |
Family
ID=31631538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8367690U Expired - Fee Related JP2515659Y2 (en) | 1990-08-07 | 1990-08-07 | Package for storing semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2515659Y2 (en) |
-
1990
- 1990-08-07 JP JP8367690U patent/JP2515659Y2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2515659Y2 (en) | 1996-10-30 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |