JPH0442544A - Microwave integrated circuit - Google Patents

Abstract

PURPOSE:To realize a microwave integrated circuit at a high production yield which can prevent non-uniformity of solder flowing into a via-hole produced when assemblying and a cavity of the electric field effect transistor and which has a sufficiently-small value of a thermal resistance and an excellent high frequency characteristic by a method wherein an opening end is provided on the bottom of a recess part in which a via-hole is formed in an upper surface of a semiconductor substrate. CONSTITUTION:In a MMIC, directly under an MESFET part in which a GaAa semi-insulating substrate 10 of a part to be grounded by a via-hole 111 previous ly comprises a source electrode 13, a drain electrode 14, and a gate electrode 115, a recess 118 having a thickness portion of GaAs semi-insulating substrate is formed. Thus, a via-hole depth is in the same degree as a depth of a cavity 110 directly under the MESFET part. With this arrangement, an increase in a grounding inductance between an electrode for grounding to be generated in an element assembly step and an electrode on the rear face can be prevented.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a microwave integrated circuit (hereinafter abbreviated as AMIC), and in particular a field effect transistor (hereinafter abbreviated as MESFET) on a semiconductor substrate. The present invention relates to the structure of a via hole in an MMIC that is provided with a reduced board thickness and has a grounded via hole.

(Prior Art) In order to improve the characteristics of MMICs using gallium arsenide (GaAs), it is necessary to reduce the thermal resistance and grounding inductance of MESFETs. The thermal resistance of the MESFET can be reduced as the thickness of the GaAg substrate becomes thinner. Furthermore, grounding inductance can be reduced by employing a via hole structure. by the way,
In an MMIC, the thickness of the GaAs substrate is also designed as part of the matching circuit, so it is not possible to reduce the thickness of the GaAs substrate with consideration only to improving the performance of the MESFET. Therefore, recently, in order to achieve both NESFET performance and matching circuit design, the thickness of the GaAs substrate directly under the MESFET section has been reduced, and the thickness of the matching circuit section has been increased, thereby improving the characteristics of MMIC. .

FIG. 3 shows a conventional example. In the figure, 30 is a GaAs semi-insulating substrate, 31 is an active layer (N layer), 32 is an ohmic contact layer (N layer), 33 is a source electrode, 34 is a drain electrode, 35 is a gate electrode, and 36 is an insulating layer. Membrane (S13N4)
, 315 is a grounding electrode, 37 is a capacitor top electrode, 3
11 is a via hole, 330 is a cavity directly under the MESFET section, and 39 is a back electrode.

The main part of the manufacturing process of the above MMIC will be explained below with reference to FIG.

First, Ga is formed by ion implantation, photolithography, vapor deposition, etc.
An operating layer (N layer) 31, an ohmic contact layer (N layer) 32, a source electrode 33, a drain electrode 34, a gate electrode 35, a grounding electrode 335, a capacitor insulating film (Si, N layer) 36, capacitor top electrode 3
form 7. Next, the back surface of the GaAs semi-insulating substrate 30 is wrapped and chemically borated to a thickness of about 1,007 cm.
Thin the layer to g. Next, a via hole 311 reaching the grounding electrode 335 is formed from the back surface of the GaAs semi-insulating substrate 30 in a portion facing the grounding electrode 335 by reactive ion etching (RIE), which has excellent etching precision control. Next, a portion of the GaAs semi-insulating substrate 3 facing the source electrode 33, drain electrode 34, and gate electrode 35 is
Etching is performed to a thickness of, for example, 501 Im by RIE from the back side of the substrate 30 to form a cavity 330 on the lower surface of the GaAs semi-insulating substrate 30 directly under the MESFET section. Finally, a back electrode 39 is formed by vapor deposition or the like.

The MNIC with the above structure uses gold tin (AuSn) for the package etc.
) By mounting with solder or the like, the holes are filled with metal, so the thermal resistance of the MESFET and the grounding inductance of the matching circuit can be made sufficiently small, resulting in excellent high frequency characteristics. However, this MMIC has the following problems.

(Problem to be Solved by the Invention) When assembling the element part and adhering it to the package using gold-tin (AuSn) solder, etc., ideally the solder should flow into the via hole and the hollow part directly under the MESFET part. Although it is possible to achieve perfect adhesion between the MESFET, the ground electrode, and the package, in reality, as shown in Figure 4, the solder 300 does not flow into the via hole sufficiently.
01 is likely to occur. When such a void 301 is created,
The grounding inductance between the grounding electrode 335 and the back electrode 39 increases, leading to deterioration of high frequency characteristics. This is ME
This phenomenon occurs because the depth of the via hole is deeper than the depth of the cavity directly below the SFET. Even in this case, if you increase the amount of solder and adjust the assembly process to fit a deeper via hole, it seems possible to pour the solder to a certain degree, but in reality, the amount of solder becomes too large and flows out of the mounting area. There are serious problems such as a decrease in reliability, non-uniformity in the thickness of the solder at the mounting portion, and an increase in thermal resistance and variations.

In view of the above conventional problems, the present invention provides an improved MMIC
It provides the structure of

[Structure of the invention]

(Means for Solving the Problems) A microwave integrated circuit according to the present invention includes a via hole provided in a semiconductor substrate and an electric field provided in a portion of the semiconductor substrate where the plate thickness is reduced from the lower surface side. 1. A microwave integrated circuit including an effect transistor section, wherein a via hole has an open end at the bottom of a recess formed on an upper surface of a semiconductor substrate.

In the structure of the MMIC according to the present invention, the depth of the via hole and the depth of the cavity directly under the MESFET can be made to be approximately the same by processing the upper surface side of the semiconductor substrate directly under the grounding electrode into a concave shape in advance. It is possible to prevent non-uniformity of solder flowing into the via hole and the MESFET cavity during assembly. Therefore, an MMIC with sufficiently small thermal resistance and ground inductance and excellent high frequency characteristics can be realized with high yield.

(Example) Hereinafter, an example of the present invention will be described with reference to FIG. 1, and further a main part of the manufacturing process will be explained with reference to FIG. 2.

In FIG. 3, 10 is a GaAs semi-insulating substrate, 11 is an active layer (N layer), 12 is an ohmic contact layer (N layer), 1
3 is a source electrode, 14 is a drain electrode, 15 is a gate electrode, 16 is a Si, N4 layer, 115 is a grounding electrode, 17
is the capacitor top electrode and bonding pad electrode,
118 is a recess, ill is a via hole, 11 is an MES
The cavity 19 directly below the FET section is a back electrode. As shown in FIGS. 1 and 2, the MNIC according to the present invention is
A portion of the GaAs semi-insulating substrate 10 that is to be grounded through a via hole is connected in advance to a source electrode 13, a drain electrode 14, .
GaAs directly below the MESFET section consisting of the gate electrode 15
The thickness of the semi-insulating substrate, for example, 30. If,
A recess 18 having a depth of 30 mm is formed. In this way, it has a structural feature that allows the depth of the pipe hole to be approximately the same as the depth of the cavity directly below the MESFET section.

The above structure can prevent an increase in ground inductance between the ground electrode and the back electrode that occurs during the element assembly process.

Next, a method of manufacturing the above structure will be explained with reference to FIG.

First, an acceleration energy of 140 KeV and a dose layer of 3×101
012a'' Si ions are selectively implanted. Next, an acceleration energy of 120 KeV and 2
Si ions are selectively implanted at 50 KeV and at a dose of 2×10"am'"2. Subsequently, annealing is performed at a temperature of 850°C to activate the Si ions and form the active layer (
An ohmic contact layer (N layer) 21 and an ohmic contact layer (N layer) 22 are formed. Next, a recess 288 with a depth of 30/a is formed by RIE, which can be precisely controlled, using a photoresist 299 having an opening in the area where the ground electrode is to be formed as a mask (FIG. 2(a)).
. Here, the depth of the recess 288 is approximately the thickness of the GaAs semi-insulating substrate directly below the MESFET section. Next, a source electrode 23, a drain electrode 24, etc. are formed by photolithography, vapor deposition, plasma CVD, etc. A gate electrode 25, a grounding electrode 255, and the like are respectively formed.

Next, Ga
The As semi-insulating substrate 20 is thinned to a thickness of 100p.

Next, by photolithography using infrared rays, the grounding electrode 2 is
After forming a photoresist pattern having an opening on the back surface of the GaAs semi-insulating substrate 20 facing the substrate 5, BCl2. By RIE using the system, the GaAs crystal is etched by about 70% IIIn to form a via hole 211 that reaches the grounding electrode 215 (FIG. 2(b)).
.

Next, after forming a photoresist pattern having an opening on the back surface of the GaAs semi-insulating substrate 20 facing the MESFET section consisting of the source electrode 23, drain electrode 24, and gate electrode 25, GaAs
The As crystal is etched 70 times to form a cavity 220 (FIG. 2(C)).

Finally, a back electrode 28 is formed by vapor deposition to complete the MMIC shown in FIG.

As mentioned above, by processing the upper surface of the GaAs semi-insulating substrate 20 directly below the grounding electrode 215 into a concave shape, the via hole depth and the etching depth of the GaAs semi-insulating substrate 20 directly below the MESFET section can be made to be approximately the same. can do.

Note that the depth of the recess and the MESFET described in the above example
Although the thickness of the GaAs semi-insulating substrate directly under the part was set to 30 ia, the thickness is not limited to this, and the depth of the recess and the MESFE
It does not matter as long as the thickness of the GaAs semi-insulating substrate directly under the T portion is approximately the same.

〔Effect of the invention〕

According to the present invention, as described above, by processing the lower surface of the GaAs semi-insulating substrate directly under the grounding electrode into a concave shape, the thickness of the GaAs semi-insulating substrate directly under the MESFET portion can be made thin, while the via hole can be formed. Depth and MESFET
Since the etching depth of the GaAs semi-insulating substrate directly under the surface can be made to the same level, it is possible to prevent an increase in the grounding inductance between the grounding electrode and the back electrode that occurs during the device assembly process, thereby reducing thermal resistance and grounding inductance. There is a remarkable advantage that an MMIC having a sufficiently small value and excellent high frequency characteristics can be realized at a high yield.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an MMIC according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view for explaining the main parts of the manufacturing process of the MNIC shown in FIG. 1, and FIGS. 3 and 4 are the conventional MM.
FIG. 3 is a cross-sectional view showing the main parts of the IC. 10, 2O-GaAs semi-insulating substrate, 118.218-
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Claims (1)

[Claims] In a microwave integrated circuit including a via hole provided in a semiconductor substrate and a field effect transistor section provided in a portion of the semiconductor substrate whose thickness is reduced from the lower surface side, the via hole is provided on the upper surface of the semiconductor substrate. A microwave integrated circuit characterized in that the formed recess has an open end at the bottom.