JPH0441856B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to the use of pseudo random signals.
Sequence signal (hereinafter abbreviated as PRS signal) generation device, especially PRS that generates multiple sequences of PRS signals used for testing digital communication equipment, etc.
This invention relates to a signal generator.

[Conventional technology]

The maximum period length R of a pulse train pattern obtained from a combination of an N-stage shift register and an exclusive OR circuit (hereinafter abbreviated as EX-OR) is R.
= (2 ^N -1), and since this maximum period length pulse train has equal probability of occurrence of "0" and "1" and randomness is guaranteed within its period,
It is used as a PRS signal for testing digital communication equipment.

As the capacity of digital communication equipment increases, multilevel modulation methods are being used, and in order to test equipment using this method, it is necessary to generate multiple strings of PRS signals that are high-speed and have small correlations with each other. A device is needed to do this.

FIG. 2 is a block diagram showing an example of a conventional PRS signal generator.

The conventional example shown in Figure 2 is a shift register and EX
−OR (neither shown) and PRS
a conventional PRS signal generator B generating a signal S ₀ ;
By serial-parallel converting the PRS signal _S0 , m
The serial-to-parallel converter C outputs the column PRS signals S ₁ to S _n . When PRS signal generator B operates at a clock frequency of Hz, PRS
The pulse repetition frequency of the signal S ₀ is Hz,
The pulse repetition frequency of PRS signals S ₁ to S _n is /
mHz, which is 1/m of the original clock frequency. In other words, the PRS signal generator B needs to operate at a clock frequency m times the pulse repetition frequency required for the PRS signals S ₁ to _{S n} .

As described above, the conventional PRS signal generation device that generates multiple columns of PRS signals has the drawback that it requires a circuit that operates at high speed, and also has the drawback that it requires a serial-parallel converter.

[Problem that the invention seeks to solve]

The problem to be solved by the present invention, or in other words, the purpose of the present invention is to solve the above-mentioned drawbacks, to enable low-speed operation, to eliminate the need for a serial-to-parallel converter, and to connect multiple columns with small correlation to each other. An object of the present invention is to provide a PRS signal generator that outputs a PRS signal.

[Means for solving problems]

The pseudo-random signal generator of the present invention has a first transition matrix representing a pseudo-random signal generator that generates a first pseudo-random signal with a period length of (2 ^N -1) (N is an integer of 3 or more). (n= ^2k1 , _k1 is a positive integer less than N) N binary signal storage means connected so as to be represented by a second transition matrix which is lm=n (l=2 ^k2 , _k2 is zero or
(a positive integer less than ₁ )), m columns of second pseudo-random signals of
It is configured by outputting from the value signal storage means.

〔Example〕

The present invention will be described in detail below with reference to the drawings showing embodiments.

FIG. 1a is a block diagram showing a first embodiment of the PRS signal generator of the present invention.

FIG. 1b is a block diagram showing an example of a conventional PRS signal generator from which the configuration of the embodiment shown in FIG. 1a is derived.

First, a conventional example shown in FIG. 1b will be explained.

This conventional example includes a 15-stage shift register A having N ₀ 1 FF (FF is an abbreviation for flip-flop circuit) 20 to N ₀ 15 FF 34, and an EX-OR 35. Each time a clock pulse (not shown) is input, N ₀ 2FF21 to _{N 0} 15FF34 change their state to the state before the input of the clock pulse of N ₀ 1FF20 to _{N 0} 14FF33. Every time a clock pulse is input, N ₀ 1FF20 changes its state to the value of the output of EX-OR35 before the clock pulse was input. EX-OR35 outputs the exclusive OR of the states of N ₀ 14FF33 and N ₀ 15FF34. The state of N ₀ 1FF20 is output to the outside as a PRS signal S ₁₀₁ . PRS
A PRS in which the signal S ₁₀₁ has a period length equal to the maximum period length R ₁ (=2 ¹⁵ −1) of the pulse train pattern obtained from a combination of a 15-stage shift register and an EX-OR.
It is well known that it is a signal.

N ₀ jFF ( _{j is 1} or more and 15
The following integers) are expressed as U _i and _j . Further, the vertical vector with U _i , _j as the j-th component is expressed as U _i . From the configuration shown in Figure 1b, U _i+1 = T ₁ U _i ...(1) T ₁₁ : Zero matrix with 1 row and 13 columns T ₁₂ : (11) T ₁₃ : Identity matrix with 14 rows and 14 columns T ₁₄ : A relational expression of zero matrix with 14 rows and 1 column holds true. T ₁ is a transition matrix representing the conventional example shown in FIG. 1(b). From equations (1) and (2), U _i+1 , _j+1 = U _i , _j (j=1 to 14) ...(3) U _i+1,1 = U _i,14 U _1,15 ( represents an exclusive OR operation) is obtained. Expression of PRS signal S ₁₀₁ in time series
Expressed as (4). Two vertical lines indicate divisions of one cycle of the pulse train pattern S ₁₀₁ =(S ₁ S ₂ S ₃ . . . S _R1 ‖S ₁ ……) (4). N ₀ 2FF21~ _{N 0} 4FF (N ₀
3FF・N ₀ 4FF is not shown) _.
When expressed in time series as S ₁₀₃ and S ₁₀₄ , it becomes as follows from equations (3) and (4).

S ₁₀₂ = (S _R1 S ₁ S ₂ ...S _R1-1 ‖S _R1 ...) ...(5) S ₁₀₃ = (S _R1-1 S _R1 S ₁ ...S _R1-2 ‖S _R1-1 ...) ...(6) S ₁₀₄ = (S _R1-2 S _R1-1 S _R1 ...S _R1-3 ‖S _1-2 ...) ...(7) Next, carry out the implementation shown in Figure 1 a. An example configuration will be explained.

This example is a case where the parameters in "Claims" are N=15, n=m=4, l=1, and _N01FF1 to _N0 are used as binary signal storage means.
Equipped with 15 FF of 15FF15. The state of each FF is expressed in the same way as U _i and _j in the conventional example shown in Figure 1b.
If the vertical vector V _i is defined in the same way as _{U i ,} then the transition matrix representing the state that each FF changes for each clock pulse input is T ₁ to the nth _power , that is,
Since T ₁ ⁴ , relational expression (8) holds true. T ₁ ⁴ becomes as follows from the formula V _i+1 = T ₁ ⁴ V _i ...(8) (2). T ₁ ⁴ in the first to fourth rows _{N _ _ _ 0} 1FF1~N ₀
The output ends of EX-OR16 to EX-OR19 are connected to the input ends of 4FF4, respectively. Connections between each FF and each EX−
The connection of the input end of the OR is determined by the row and column where "1" exists in T ₁ ⁴ , as shown in FIG. 1a. Also, since l-1=0, every zero number, that is, four consecutive FFs, N ₀ 1FF1~
PRS signals S ₁₁ to _{S 14} are output from N ₀ 4FF4 to the outside.

The operation of the embodiment shown in FIG. 1a will be explained in relation to the operation of the conventional example shown in FIG. 1b.

From equation (1), U _i+4 = T ₁ U _i+3 = T ₁ ² U _i+2 = T ₁ ³ U _i+1 =
T ₁ ⁴ U _i . From this relationship and equation (8), it can be seen that the time series obtained by extracting every third time series from the time series of U _i becomes the time series of V _i . Based on this, equations (4) to (7), and the fact that “R ₁ +1” (=2 ¹⁵ ) is divisible by “4” (=n), the PRS signals S ₁₁ to _{S 14} are time-series as follows. is expressed in One cycle of PRS signals S ₁₁ to _{S 14} is one signal S ₁₁ = (S ₁ S ₅ ...S _R1-2 | S ₂ S ₆ ... S _R1-1 | S ₃ S ₇ ... S _R1 | S ₄ S ₆ ……S _R1-3 ‖S ₁ S ₅ ……) ……(10) S ₁₂ = (S _R1 S ₄ ……S _R1-3 ｜S ₁ S ₅ ……S _R1-2 ｜S ₂ S ₆ ……S _R1-1 ｜S ₃ S ₇ ……S _R1-4 ‖S _R1 S ₄ ……) …… (11) S ₁₃ = (S _R1-1 S ₃ ……S _R1-4 ｜S _R1 S ₄ ……S _R1 S ₄ ……S _R1-3 ｜S ₁ S ₅ ……S _R1-2 ｜S ₂ S ₆ ……S _R1-5 ‖S _R-1 S ₃ ……) ……( 12) S ₁₄ = (S _R1-2 S ₂ ……S _R1-5 ｜S _R1-1 S ₃ ……S _R1-4 ｜S _R1 S ₄ ……S _R1-3 ｜S ₁ S ₅ ……S _R1-6 ‖S _R1-2 S ₂ ……) ……(13) It is divided into four parts separated by vertical lines, and each part is offset from each other. This deviation is (R ₁ +1)/4 (=2 ¹⁵ /4) bits, which is the maximum deviation that can occur when a pulse train pattern with period length R ₁ is shifted to create a four-row pulse train pattern. Therefore, the correlation between PRS signals S ₁₁ to S ₁₄ is becoming smaller.

As mentioned above, the embodiment shown in FIG. 1a is 2 ¹⁵ /
Four columns of PRS signals S ₁₁ to _{S 14} that are shifted by 4 bits are generated, and the correlation between these PRS signals is small at best.
It has also been explained that each FF operates at a clock frequency equal to the pulse repetition frequency of these PRS signals.

FIG. 3a is a block diagram showing a second embodiment of the PRS signal generator of the present invention.

FIG. 3b is a block diagram showing an example of a conventional PRS signal generator from which the configuration of the embodiment shown in FIG. 3a is derived.

This conventional example has N ₀ 1FF67 to _{N 0} 23FF89
It is composed of a 23-stage shift register D and an EX-OR90, and the EX-OR90 is N ₀ 18FF84/N ₀
Outputs the exclusive OR of the states of 23FF89 to N ₀ 1FF67. The state of N ₀ 1FF67 is output to the outside as PRS signal S ₂₀₁ . PRS signal S ₂₀₁ is the maximum period length R ₂ (=2 ²³ −1) of a pulse train pattern obtained from a combination of a 23-stage shift register and EX-OR
It is well known that this is a PRS signal with a period length of . From the configuration shown in FIG. 3b, the transition matrix T ₂ representing this conventional example is expressed as equation (14).

T ₂₁ : Zero matrix with 1 row and 17 columns T ₂₂ : [100001] T ₂₃ : Identity matrix with 22 rows and 22 columns T ₂₄ : Zero matrix with 22 rows and 1 column The embodiment shown in FIG. range"
The parameters in are N=23, n=m=8, l=
In the case of 1, there are 23 pieces from N ₀ 1FF36 to _{N 0} 23FF58.
Equipped with FF. The transition matrix representing this embodiment is T ₂ to the nth power, that is, T ₂ ⁸ , and is expressed as equations (14) to (15). From equation (15), 8 EX−
OR 00 00000100001 T ₂₃₈ : An _identity matrix of 15 rows and 15 columns T ₂₄₈ : It is decided that a _zero matrix of 15 rows and 8 columns is required, and Each FF/Each EX−
The OR connection is determined as shown in Figure 3a.
Since l-1=0, PRS signals S ₂₁ to _{S 28} are output to the outside from the eight consecutive FFs N ₀ 1FF36 to _{N 0} 8FF43.

Next, the operation of the embodiment shown in FIG. 3a will be explained.

If we consider the same considerations as we _have made regarding the description of the operation of the embodiment shown in FIG _.
The time series of is N ₀ 1FF67 to _{N 0} 8FF in Figure 3b.
(N ₀ 3FF to _{N 0} 8FF are not shown) The time series is created by extracting every seventh state from the time series, and the time series of N ₀ 1FF67 to _{N 0} 8FF are each 1
It is found that the bits are shifted, and from these facts and the fact that “R ₂ +1” (=2 ²³ ) is divisible by “8” (=n), the PRS signals S ₂₁ to _{S 28} are mutually (R ₂ ±1 )/8 (=2 ²³ /8) bit shift. This deviation is the maximum deviation that can occur when creating an 8-series pulse train pattern by shifting a pulse train with period length R ₂ , and therefore
The correlation between PRS signals S ₂₁ to S ₂₈ is becoming smaller. Each FF operates at a clock frequency equal to the pulse repetition frequency of these PRS signals.

This concludes the description of the embodiment shown in FIG. 3a.

In the embodiment shown in FIG. 3a, the PRS signal S ₂₁
~ Every other PRS signal of S ₂₈ S ₂₁・S ₂₃・S ₂₅・
A third embodiment of the PRS signal generator of the present invention outputs four columns of PRS signals _S21 , _S23 , _S25 , and _S27 without changing the _circuit by outputting only S27 to the outside. can get. This example is the “Claims”
The parameters in are N=23, n=8, m=4,
This is the case when l=2. Since l-1=1, every other four FFs are N ₀ 1FF36・N ₀ 3FF38・N ₀
5FF40・N ₀ FF42 to PRS signal S ₂₁・S ₂₃・S ₂₅・
S ₂₇ will be output. Each of these PRS signals is shifted by 2 ₂₃ /4 bits, and this shift is made by shifting the pulse train of period length (2 ²³ -1) by 4 bits.
It is the maximum deviation that can occur when creating a pulse train pattern of a train, and therefore the PRS signal S ₂₁ .
The correlation between S ₂₃ , S ₂₅ , and S ₂₇ is becoming smaller.

In the same way as the third embodiment was obtained from the embodiment shown in ^FIG . 3a, lm=n(l = ^2k2 ,
The PRS signal generator of the present invention, which outputs m columns of PRS signals where k2 is a positive integer less than k1, can be obtained without changing the circuit.

Note that an all-zero prohibition circuit or an initial value setting circuit may be added to the conventional PRS signal generator. These circuits can also be added to the PRS signal generator of the present invention.

〔Effect of the invention〕

As explained in detail above, the PRS signal generator of the present invention operates at a clock frequency equal to the pulse repetition frequency of the plurality of PRS signals to be output, so it has the advantage of requiring low-speed operation. This has the advantage of not requiring any PRS signals, and further has the advantage that the correlation between each PRS signal is guaranteed to be small.

[Brief explanation of drawings]

FIG. 1a is a block diagram showing a first embodiment of the PRS signal generator of the present invention, and FIG. 1b is a block diagram of a conventional PRS signal generator from which the configuration of the first embodiment is derived. FIG. 2 is a block diagram showing an example of a conventional PRS signal generating device that generates a plurality of columns of PRS signals. FIG. 3a is a block diagram showing a second embodiment of the PRS signal generating device of the present invention. FIG. 3b is a block diagram showing an example of a conventional PRS signal generator from which the structure of the second embodiment is derived. 1~12...N ₀ 1~12FF, 16~19EX-
OR.

Claims (1)

[Claims] 1 ⁿ (n= ^2k1 ,
N binary signal storage means from number one to number N connected so as to be represented by a second transition matrix where k ₁ is a positive integer less than N) and one or more exclusive OR function means having m columns of second pseudorandom signals with lm=n (l= ^2k2 , _k2 is zero or a positive integer less than _k1 ).
-1) A pseudo-random signal generating device, characterized in that it outputs from m binary signal storage means arranged at intervals.