JPH03101307A - Parallel pseudo randam pattern generation circuit - Google Patents

Abstract

PURPOSE:To reduce a circuit scale by constituting parallel output terminals by means of the output terminals of the outputs of FF in a serial PN pattern generation circuit and the output terminals of an exclusive OR circuit (EX-OR) obtaining the exclusive OR of the outputs of FF. CONSTITUTION:For obtaining P-number of parallel output terminals PN1-PN4, PNN and PNP, a flip flop(FF) having the large circuit scale is not added to a serial pseudo random pattern (PN pattern) generation circuit 30, but they are constituted by the output terminals of the outputs of FF1, 2...N-2, N-1 and N in the serial PN pattern generation circuit 30 and the output terminals of EX-OR having the comparatively small circuit scale, which obtains the exclusive OR of the outputs of FF1, 2...N-2, N-1 and N. Thus, a parallel PN pattern generation circuit having the small circuit scale can be obtained.

Description

[Detailed Description of the Invention] [Summary] Pseudo-random pattern (hereinafter referred to as PN pattern) with a period of (2N-1) expressed by an N-th order generator polynomial.
A serial type PN pattern generation circuit is used to generate the pattern using N flip-flops (hereinafter referred to as FF), and the phase is sequentially shifted by a predetermined bit from P more than N parallel output terminals. Regarding a parallel type PN pattern generation circuit that generates a PN pattern with a period of (2''-1) expressed by an Nth degree generator polynomial, the purpose of this paper is to provide a parallel type PN pattern generation circuit that can be realized with a small circuit scale. , The P parallel output terminals include an output terminal of the output of the serial type PN pattern generation circuit OFF, and an exclusive OR circuit (hereinafter referred to as EX-O) for calculating the exclusive OR of the output of the FF.
It consists of an output terminal (referred to as R).

[Industrial application field]

The present invention provides a PN pattern with a period of (2"-1) expressed by an N-th order generator polynomial, which is used when scrambling two signals with a PN pattern of P parallel outputs. Using a series-type PN pattern generation circuit that generates N patterns using OFF, an N-order generating polynomial whose phase is sequentially shifted by a predetermined bit by P parallel output terminals 31, which are more than N, is used. Represented by (2N-1)
This invention relates to an improvement of a parallel type PN pattern generation circuit that generates a PN pattern with a period of .

[Conventional technology]

FIG. 4 is a circuit diagram of an example of a series type PN pattern generation circuit,
Figure 5 is a circuit diagram of a conventional parallel type PN pattern generation circuit, Figure 6 is a diagram showing PN patterns from each parallel output terminal in the case of Figure 5, and Figure 7 is a conventional parallel type PN pattern. FIG. 3 is an explanatory diagram for determining an exclusive OR circuit of a generating circuit.

FIG. 4 is a circuit diagram of a series type PN pattern generation circuit when the 5th order generating polynomial is X'+X'+1.
It consists of F5 and EX-ORIO, and in this case the PN
Since the pattern has a 5th degree generator polynomial, 2N −1=
It has a period of 31, and the contents are as shown in the right direction from the beginning of the first line in Figure 6, and then the second line is shown in the right direction, and the 31 bit at the intersection of PN7 and clock time 5. Eyes 1
It is a cycle.

In this case, for example, when outputting the same PN pattern as the output of the above-mentioned serial type PN pattern generation circuit, which has eight parallel outputs and shifts a predetermined bit from each parallel output,
X-OR is determined as shown in FIG.

That is, as shown in FIG. 7(A), three FFs are added until the number of parallel outputs reaches eight.

As shown in (B), each FF 1 to 8 at time t
For the output L(t) to X5(t), the output L(t+1) of each FFI to
) to X++(t+ 1) is expressed as shown in (B).

Let the equation shown in (B) be the equation shown in (C).

In the equations (B) and (C), (T) is a value indicating the input coefficient from above to FF1-FF8 as shown in (D).

In this case, since 8 parallel outputs are obtained, the output in the state after 8 clock hours is taken out, so (X < t
-+n) is as shown in (E), and T is raised to the 8th power.

By finding the value of this 8th power, it is possible to know what kind of EX-OR should be provided.

The circuit diagram obtained in this way is shown in Figure 5 (for example, EX-OR20 on the input side of FFI is FF2.FF
3. It takes the exclusive OR of the outputs of F and F4,
EX-OR21 on the input side of FF2 is FF3. FF4. F
EX-OR27 on the input side of FF8 takes the exclusive OR of the output of F5. This is to calculate the exclusive OR of the outputs of FF5.

In this case, the output terminal PNI~ which outputs the PN pattern
The output from PN8 is as shown in Figure 6,
The output of PN2 is the same as that of PN3. PN4. ...
The value 4 bits earlier than PN8 is sequentially output, and the PN pattern of each output is the same as the output of the serial type PN pattern generation circuit shown in FIG.

[Problem to be solved by the invention]

However, until the number of parallel output terminals is reached, large-scale FFs must be added and EX-ORs must be provided, resulting in a problem that the circuit scale becomes large.

An object of the present invention is to provide a parallel PN pattern generation circuit that can be realized with a small circuit scale.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

A PN pattern with a period of (2N-1) expressed by an N-th order generator polynomial is divided into N FF1, 2°...N-2,
A serial type PN pattern generation circuit 30 is used to generate a PN pattern using P parallel output terminals PN1, PN2, PN3 . PN4. PNN, PNP
When configuring a parallel PN pattern generation circuit that generates a PN pattern with a period of (2N-1) expressed by an N-order generator polynomial whose phase is sequentially shifted by a predetermined bit, the circuit shown in Fig. 1 is used. , the P parallel output terminals PNI.

PN2. PN3. PN4. As PNN and PNP, FFI2, . . . N of the series type PN pattern generation circuit 30 are used.
-2, N-1, H output terminal and J-FF1,
2. . . . Consists of an EX-OR output terminal for calculating the exclusive OR of the outputs of N-2, N-1, and N.

[For production]

According to the invention, P parallel output terminals PNI.

PN2. PN3. PN4. To obtain PNN and PNP,
The serial type PN pattern generation circuit 30 has a large circuit scale F.
F is not added, and the FF of the series type PN pattern generation circuit 30 is
1, 2. . . . N-2, N-1, output terminals of N outputs, and FF1, 2. ...A relatively small circuit scale E that calculates the exclusive OR of the outputs of N-2, N-1, and H
Since it is composed of X-OR output terminals, it is possible to obtain a parallel type PN pattern generation circuit with a small circuit scale.

〔Example〕

FIG. 2 is a circuit diagram of a parallel type PN pattern generation circuit according to an embodiment of the present invention, and FIG. 3 is an explanatory diagram of one example of remote ring calculation.

As in the case of the conventional example, FIG. 2 shows a series PN pattern generation circuit as shown in FIG. FIG. 3 is a circuit diagram for outputting in parallel eight PN patterns obtained by shifting the output of a generating circuit by 4 bits.

In the case of this Fig. 2, the outputs of the output terminals PNI to PN8 are outputted after 5 clocks of the output of FFI, so the outputs of the output terminals PNI to PN8 are as shown in Fig. 6.
From the output of FI, 9.5°1.28.24,20.16
．． It will be shifted by 12 bits.

Therefore, EX-OR is determined using a method of calculating a remote ring of a series formed from n-stage feedback shift registers.

For example, in the case of PNI, there is a 9-bit delay, so the generator polynomial is
Since it is 3+1, 5.3. as shown in ■■■. Set it as O.

Then, find the value 4 to add so that 5 becomes 9, place it in ■, 5, 3, and so on. If we subtract the 9 and 7.4 added to O from the 9 of ■, the remainder becomes 7.4.

Therefore, find the value 2 to add so that 5 becomes 7, and place it in ■, 5, 3, and so on. If we subtract the 7.5.2 added to O from 7°4, the remainder becomes 5.4.2.

In this case, the remaining head is 5, so this completes,
The remaining 5, 4.2 or FF5. If EX-ORIl is provided to take the exclusive OR of the outputs of FF4 and FF2, an output as shown by PNI in FIG. 6 can be obtained.

In the next case, PN2, there is a 5-bit delay, so EX
-OR is not necessary, just set the output of FF5 to PN2, and P
In the case of N3, since there is a 1-bit delay, it is sufficient to output it from the output of the FFI without using EX-OR.

Similarly, by performing remote method calculations, the desired EX-O
R can be found.

The parallel type PN pattern generation circuit obtained in this way is the second
As shown in the figure, the output terminal PNI is connected to FF5.4.2 (
7) The output of EX-OR11 which takes exclusive OR, the output terminal PN2 is the output of FF5, and the output terminal PN3 is the output of FF
The output of output terminal PN4 is the output of FF5, 3.2.
The output terminal PN5 is the output of EX-OR12 which takes the exclusive OR of FF4, 3.2(7), and the output terminal PN6 is the output of EX-OR13 which takes the exclusive OR of FF4, 3.2(7).
The output of EX-OR14, which takes the exclusive OR of 4゜2,
The output terminal PN7 is E which takes the exclusive OR of FF3.2.
At the output of X-OR15, output terminal PN8 is connected to FF3, 2
．． 1 (7) This is the output of EX-OR 16 which takes the exclusive OR.

In this way, by adding EX-OR without increasing the number of FFs, a parallel type PN pattern generation circuit is constructed, so that the circuit scale can be reduced.

〔Effect of the invention〕

As described above in detail, the present invention has the advantage of providing a parallel PN pattern generation circuit with a small circuit scale.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a circuit diagram of a parallel type PN pattern generation circuit according to an embodiment of the present invention, Fig. 3 is an explanatory diagram of calculation of a remote term in an example, and Fig. 4 is a 1 A circuit diagram of a serial type PN pattern generation circuit as an example, Figure 5 is a circuit diagram of a conventional parallel type PN pattern generation circuit, and Figure 6 is a diagram showing PN patterns from each parallel output terminal in the case of Figure 5. , FIG. 7 is an explanatory diagram for determining an exclusive OR circuit of a conventional parallel type PN pattern generation circuit. In the figure, 1 to B, N-2, N-1, and N are flip-flops, and 10
~16. 20 to 27 are exclusive OR circuits, 30 is a serial pseudo random pattern generation circuit, PNI to PN8. P.N.
N and PNP indicate output terminals. Honashi Akira's thrust M! Example of concave U in parallel type 2N Bakun generation outlet path
Figure 2 Figure 4 An example of a confusing term

Claims (1)

[Claims] A pseudo-random pattern with a period of (2^N-1) expressed by an N-th order generator polynomial is connected to N flip-flops (1, 2, . . . N-2, N-1). , N).
0), and P parallel output terminals (PN1
, PN2, PN3, PN4, PNN, PNP), a parallel type that generates a pseudo-random pattern with a period of (2^N-1) expressed by an N-order generator polynomial whose phase is sequentially shifted by a predetermined bit. When configuring the pseudo-random pattern generation circuit, the P parallel output terminals (PN1, PN2, PN3, PN
4, PNN, PNP), the flip-flops (1, 2) of the series type pseudo-random pattern generation circuit (30)
,...N-2, N-1, N) output terminals, and
The flip-flops (1, 2,...N-2, N-1,
1. A parallel pseudo-random pattern generation circuit comprising an output terminal of an exclusive OR circuit that obtains an exclusive OR of the outputs of the circuits N).