JP2000278099A - M-sequencies generating circuit and pn code generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an M-sequencies generating circuit and a PN code generating circuit for easily generating a PN code (M-sequencies) with required code length. SOLUTION: An M-sequencies generating circuit 10 is provided with N bit shift registers 11 which shift and store each value, M pieces of XOR (exclusive logical sum) circuit 12 inserted between the shift registers 11 according to a generation polynomial, a register (register R) which stores the value in the final stage of the shift registers 11, and which has an initial value 0, an N bit counter (COUNT) 14 which counts the number of clocks in one cycle of the M-sequencies, an OR circuit 15 which calculates the logical sum of the values of each bit of the N bit counter 14, a register (register L) 16 which holds the value of the OR circuit 15, an NAND circuit 17 which calculates the negation of the logical product of the output value of the OR circuit 15 held in the register L and a value directly outputted from the OR circuit 15, a selector (MUL1) 18 which is controlled by the output of the OR circuit 15, and a selector (MUL2) 19 which is controlled by the output value of the OR circuit 15 held in the register L.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an M-sequence generator and a PN code generator, and more particularly, to an M-sequence generator in a mobile communication system using a code division multiple access (CDMA) communication system. The present invention relates to a sequence generation circuit and a PN code generation circuit.

[0002]

2. Description of the Related Art In recent years, research and development on a CDMA system has been actively conducted as one of techniques for improving the frequency use efficiency in mobile communication.

[0003] In this CDMA, an interference signal from a transmitting station other than a desired signal multiplexed in a spreading / despreading process is treated in the same manner as thermal noise, so that it is proportional to the processing gain. The same number of transmitting stations can use the same frequency band at the same time. In CDMΑ, for example, direct diffusion (DS: Direct Seq
uence), transmitting stations such as users using the same frequency are separated by pseudo orthogonal codes.

In direct spreading (DS), a PN (pseudo noise) sequence used in spreading modulation plays a very important role. There are various ways to make the PN sequence, but especially the M sequence (Maximum Length Code).
Is often used because it is the simplest way to make it, the disorder of the extracted sequence has a property close to a true random number, and the property is well analyzed. As a PN sequence used in actual CDMA, a GOLD code sequence obtained by preparing two types of M-sequence generators having the same period and adding their outputs is used.

[0005] The M series is composed of an n-stage shift register and an XOR
(Exclusive OR).

The number of bits in one cycle of a PN code periodically generated in a certain bit unit is called a code length. For example, it is known that a PN code (M sequence) generator having a code length of 16 has a configuration shown in FIG. 22 when a generator polynomial is given by the following equation (1).

[0007]

(Equation 1) FIG. 22 is a diagram showing a configuration of a conventional internal XOR type M-sequence generator.

In FIG. 22, an M-sequence generator includes a 1-bit shift register (S0, S
1, S2, S3), an XOR (exclusive OR) is provided inside. The M-sequence generator inputs the circuit output that has been fed back to the XOR through a feedback tap provided at a specific position in the middle of the shift register S3. Output to The M sequence is output from the right end of the shift register S0.

When the initial values are set in the shift registers S0 to S4, the value of each register is shifted to the next register at every clock cycle. However, the exclusive OR of the output of the S2 register and the output of the S0 register is obtained,
Stored in a register.

If the shift is continued, the shift register S
A PN code is generated at the output terminal connected to 0. The same code is repeated for every 15 bits of the PN code (M sequence) generated at the output end.

[0011]

However, such a conventional PN code (M-sequence) generator has the following problems. 1. PN code (M-sequence) generator with spread length 16 CDMA
When used in communication, the required period of the PN code (M-sequence) is 16 bits, whereas the conventional example has only a period of 15 bits. One bit of 0 must be inserted at the beginning or end of one code cycle, and no specific circuit for the insertion has been reported. 2. In the conventional example, the insertion of one bit is limited to the beginning or end of one period of the PN code, and 0 cannot be inserted at an arbitrary position within one period. 3. The above-described circuit supports only the generator polynomial expressed by the above equation (1), and when another generator polynomial is realized, it is necessary to redesign the circuit. 4. Further, the above-mentioned circuit corresponds only to the case of the spread length of 16, and when a PN code (M sequence) generator of another spread length is required, it is necessary to redesign the circuit.

An object of the present invention is to provide an M-sequence generation circuit and a PN code generation circuit that can easily generate a PN code (M sequence) having a required code length.

[0013]

An M-sequence generating circuit according to the present invention comprises a plurality of shift registers and exclusive-OR operation means. An N-bit shift register for shifting and storing, M exclusive OR operation means inserted between the shift registers according to a generator polynomial,
An N-bit counter for counting the number of clocks in a cycle, a first logical operation means for calculating a logic value of each bit of the N-bit counter, and a shift register inserted between the shift registers and output from the first logical operation means And first selection means for selecting an input value.

An M-sequence generating circuit according to the present invention has a first register having the same number of bits as an N-bit counter, and an arbitrary value set from outside, an N-bit counter and a first register.
And a second logical operation means for obtaining the logic of each bit of the register of the first logical operation means, and the first logical operation means may obtain the logic of the output value of the second logical operation means.

An M-sequence generation circuit according to the present invention has a second register having one less bit number than a shift register, and takes a logic of a second register to which an arbitrary value is externally set, and a logic of each bit of the second register. A third logical operation means may be provided, and the exclusive OR operation means may perform an exclusive OR operation of the value of the shift register and the output value of the third logical operation means.

The M-sequence generation circuit according to the present invention has a third register having one less bit number than the shift register and having an arbitrary value set externally, and a third register inserted between the shift register and the third register. As a control signal, and selecting whether to output the value of the shift register to the next stage or to output it as a shift register of an arbitrary bit. It may be arbitrarily selectable.

An M-sequence generation circuit according to the present invention includes a plurality of shift registers and an XOR circuit. In an M-sequence generation circuit for generating an M-sequence, an N-bit shift register for shifting and storing respective values. And M XOR circuits inserted between the shift registers according to the generator polynomial, values of the last stage of the shift register are stored, a register R having an initial value of 0, and the number of clocks in one cycle of the M series are counted. An N-bit counter, an OR circuit that takes a logical sum of the values of the respective bits of the N-bit counter, a register L that holds the value of the OR circuit, an output value of the OR circuit held by the register L, and an output directly from the OR circuit. A NAND circuit that takes the negation of the logical product of the AND value, a first selector controlled by the output of the OR circuit, and an OR circuit held by the register L.
A second selector controlled by a circuit output value.

An M-sequence generating circuit according to the present invention includes a plurality of shift registers and an XOR circuit. In an M-sequence generating circuit for generating an M-sequence, each value is shifted and stored, and an arbitrary initial value is set. , An M-bit XOR circuit inserted between the shift registers according to a generator polynomial, an N-bit counter for counting the number of clocks in one cycle of the M series, and an N-bit counter for each bit of the N-bit counter. An OR circuit for taking a logical sum of values, a register RST for holding a value of the OR circuit, and a first selector controlled by an output value of the OR circuit are provided.

An M-sequence generation circuit according to the present invention has a first register having the same number of bits as an N-bit counter, and an arbitrary value set from outside, an N-bit counter and a first register.
M AND circuits that take the logical product of the respective bits of the registers of the AND circuit. The OR circuit may take the logical sum of the output values of the AND circuit.

The M-sequence generating circuit according to the present invention has a second register which has one less bit number than the shift register and has an arbitrary value externally set, and an output of the second register as one input. N-1 AND circuits having
N-1 having -1 AND circuit output as one input
N-1 XOR circuits, and the N-1 XOR circuits may perform an exclusive OR operation of the value of the shift register and the output value of the N-1 AND circuits.

The M-sequence generating circuit according to the present invention has a third register having one less bit number than the shift register and having an arbitrary value set from the outside, and a third register inserted between the shift register and the third register. N-1 as a control signal, and selects whether to output the value of the shift register to the next stage or to output it as a shift register of an arbitrary bit.
May be provided so that the number of bits in one cycle of the M sequence can be arbitrarily selected.

A PN code generation circuit according to the present invention is a PN code generation circuit for generating a PN code using an M sequence, wherein the M sequence is generated by the M sequence generation circuit according to any one of claims 1 to 9. It is characterized by making it.

The PN code has two types of M having the same period.
It may be a GOLD code sequence obtained by adding these outputs using a sequence generation circuit.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 is a block diagram showing a configuration of an M-sequence generating circuit according to a first embodiment of the present invention, which has a code length of 16, an M-sequence generation obtained by the generator polynomial shown in the above equation (1). This is an example applied to a vessel.

In FIG. 1, an M-sequence generation circuit 10 operates on the same clock, and shifts and stores an N-bit (here, 4-bit) shift register S of each value.
A shift register 11 including 0, S1, S2, and S3;
M XOR circuits 12 (exclusive OR operation means) inserted between the shift registers 11 according to a generator polynomial, and a register (register R) 13 which stores the value of the last stage of the shift register 11 and has an initial value 0 An N-bit (here, 4-bit) counter (COUNT) 14 for counting the number of clocks in one cycle of the M sequence; an OR circuit 15 for taking the logical sum of the values of the respective bits of the N-bit counter 14;
5, a register (register L) 16 for holding the value of 5 and the output value of the OR circuit 15 held by the register L
NA for negating logical product with the value output from circuit 15
ND circuit 17, selector (MUL1) 18 controlled by the output of OR circuit 15 (first selection means, first selector), and selector (MUL2) controlled by the output value of OR circuit 15 held by register L ) 19 (second
Selector).

The shift registers S0, S1, S2, S
3. The register R and the register L operate on the same clock.

The output of the shift register S3 is supplied to one input of the XOR circuit 12, the output of the XOR circuit 12 is supplied to the input of the shift register S2, the output of the shift register S2 is supplied to the input of the shift register S1, and the output of the shift register S1. Is connected to one data input of the selector MUL1,
The output of L1 is connected to the input of the shift register S0, and the output of the shift register S0 is connected to the output terminal PN_OUT, the input of the register R, and one input of the selector MUL2.

The output of the register R is connected to the other input of the selector MUL1 and the other input of the selector MUL2.

The control signal of the selector MUL1 is O
The output signal of the R circuit 15 is connected to the selector MU.
L1 is the shift register S1 when the output of the OR circuit 15 is 1.
The output value of the register R is output when the output of the OR circuit 15 is 0.

The output of the selector MUL2 is connected to the input of the shift register S3 and the other input of the XOR circuit 12. The control signal of the selector MUL2 is connected to the output of the register L. At this time, the output of the register R is selected, and when the output of the register L is 1, the output of the shift register S0 is selected.

The N-bit counter COUNT is a counter which counts up at the same clock as each of the above registers, and each bit of the N-bit counter COUNT is O
These are the four inputs of the R circuit 15.

The output of the OR circuit 15 becomes a control signal for the selector MUL1, and also becomes an enable signal for the shift registers S1 to S3. When the output of the OR circuit 15 is 1, the shift registers S1 to S3 are write-enabled, and the OR circuit 15 When the output is 0, the shift registers S1 to S3 are write-protected.

The output of the OR circuit 15 is also connected to one input of the NAND circuit 17 and the input of the register L. The other input of the NAND circuit 17 is connected to the output of the register L, and the output of the NAND circuit 17 is
When the output of the NAND circuit 17 is 1, the register R is write-enabled, and when the output of the NAND circuit 17 is 0, the register R is write-disabled.

The register (register R) 13, the OR circuit 15, the register (register L) 16 and the NAND circuit 17 as a whole constitute a first logical operation means for taking the logic of each bit value of the N-bit counter 11. Constitute.

Hereinafter, the operation of the M-sequence generation circuit 10 configured as described above will be described.

FIG. 2 is a timing chart showing the operation of each part of the M-sequence generation circuit 10.

Here, the initial values of S0, S1, S2, and S3 are 1, 1, 1, and 1, respectively.

As shown in FIG. 2, an N-bit counter CO
When the UNT output is 0, each register is in the initial state, and the initial value 0 of the register R is stored in the shift register S0 at the next rising edge of the clock (see FIG. 2, the same applies hereinafter), and the output PN_OUT becomes 0. That is, 0 is inserted here.

At the next rising edge of the clock (), the value of the register R and the value of the shift register S
2 is the exclusive OR of the register R and the shift register S3, the shift register S1 is the value of the shift register S2,
The value of the shift register S1 is selected and input to the shift register S0 by the selector MUL1.

Similarly, shift registers S0 to S0
When the value of 3 is updated and the value of the N-bit counter COUNT is 0 again, the internal state of the shift registers S0 to S3 becomes 1111, which is the same as the initial value. Beyond this, PN_
OUT is followed by a 16-bit cycle output.

As described above, the M-sequence generating circuit 10 according to the first embodiment shifts and stores each value in an N-bit shift register 11 and is inserted between the shift registers 11 in accordance with a generator polynomial. M XORs
A circuit 12, a register (register R) 13 that stores the value of the last stage of the shift register 11 and has an initial value 0,
An N-bit counter (COUNT) 14 that counts the number of clocks in one cycle of the system, an OR circuit 15 that takes the logical sum of the values of the respective bits of the N-bit counter 14, and a register (register L that holds the value of the OR circuit 15) ) 16 and a NAND for negating the logical product of the output value of the OR circuit 15 held by the register L and the value output directly from the OR circuit 15
Circuit 17, a selector (MUL1) 18 controlled by the output of the OR circuit 15, and the O held by the register L.
Selector (MUL) controlled by output value of R circuit 15
2) Since 19 is provided, it is possible to easily generate a required 16-bit cycle M sequence.

That is, the required PN code (M sequence)
Has a period of only 15 bits in the conventional example in the case of 16 bits. In order to generate a 16-bit PN code, a one-bit 0 is added at the beginning or end of one period of the PN code.
However, in the present embodiment, it is possible to generate an M sequence having a 16-bit cycle with the circuit configuration shown in FIG. Second Embodiment FIG. 3 is a block diagram showing a configuration of an M-sequence generation circuit according to a second embodiment of the present invention. In the description of the M-sequence generation circuit according to the present embodiment, the same components as those in FIG. 1 are denoted by the same reference numerals.

In FIG. 3, M-sequence generation circuit 20 includes N
Bit (4 bit) shift registers S0, S1, S
2 and S3, and M XORs inserted between the shift registers 11 according to the generator polynomial
A circuit 12 for counting the number of clocks in one cycle of the M sequence N
A bit (4-bit) counter (COUNT) 14, an OR circuit 15 that takes the logical sum of the values of the respective bits of the N-bit counter 14, and an arbitrary value can be designated as the reset value, and the reset is controlled by the output of the OR circuit 15. A register (RST) 21 for outputting a signal, and a selector (MUL3) 22 (first selection means, first selection means) controlled by the output of the OR circuit 15
Selector).

The shift registers S0, S1, S2, S
3 and the register RST operate on the same clock.

The output of the shift register S3 is supplied to one input of the XOR circuit 12, the output of the XOR circuit 12 is supplied to the input of the shift register S2, the output of the shift register S2 is supplied to the input of the shift register S1, and the output of the shift register S1. Is connected to one data input of the selector MUL3,
The output of L3 is connected to the input of the shift register S0, and the output of the shift register S0 is connected to the output terminal PN_OUT and the input of the shift register S3.

The N-bit counter COUNT is a counter that counts up at the same clock as the above registers, and each bit of the N-bit counter COUNT is ORed.
The four inputs of the circuit 15 and the output of the OR circuit 15 are the control signal of the selector MUL3 and the shift registers S1 to S1.
This becomes the enable signal of S3.

A logic 0 is applied to the other input of the selector MUL3.
The output of the OR circuit 15 is connected to the control signal of the selector MUL3. When the output of the OR circuit 15 is 1, the value of the shift register S1 is selected, and when the output of the OR circuit 15 is 0, the logic 0 is selected.

The output of the OR circuit 15 is also connected to the input of a register RST operating at the same clock as the shift registers S0 to S3, and the output of the register RST is connected to the reset input of the shift registers S0 to S3. .

The shift registers S0 to S3 have initial values. When a reset signal from the register RST is input, the initial values are always written in synchronization with the clock. Also,
Regarding the shift registers S1 to S3, when the enable signal is 1, writing is permitted, and when it is 0, writing is prohibited.

Hereinafter, the operation of the M-sequence generation circuit 20 configured as described above will be described.

FIG. 4 is a timing chart showing the operation of each part of the M-sequence generation circuit 20.

Here, the initial values of the shift registers S0 to S3 are all 1, and when the rising edge of the clock is input while the reset signal is input, the shift registers S0 to S3 are reset.
3 are all initialized, that is, 1 is written.

When the output of the N-bit counter COUNT is 0, the output of the OR circuit 15 becomes 0. At the rising edge of the clock at this time, 0 is written into the shift register S0, and PN_OUT also becomes 0 at the same time. At the same time, the output of the register RST becomes 0, and all the shift registers S0 to S3 are initialized and 1 is written at the next rising edge of the clock ().

From the next rising edge of the clock (), the output of the shift register S3 takes an exclusive OR with the output of the shift register S0 to obtain the shift register S2, the output of the shift register S2 to the shift register S1, and the shift register S1.
The output is input to the shift register S0, and the output of the shift register S0 is input to the shift register S3.
The series shown in FIG. 4 occurs in T.

Again, at the rising edge of the clock when the output of the N-bit counter COUNT is 0, 0 is written into the shift register S0 and 0 is inserted into the PN output.

As described above, the M-sequence generation circuit 20 according to the second embodiment includes an N-bit shift register 1
1, M XOR circuits 12 inserted between the shift registers 11 in accordance with a generator polynomial, and an N-bit counter (COUNT) 14 for counting the number of clocks in one cycle of the M series.
And an OR circuit 15 that takes the logical sum of the values of the respective bits of the N-bit counter 14, and an arbitrary value can be designated as the reset value.
Since a register (RST) 21 controlled by the output of the OR circuit 15 and outputting a reset signal and a selector (MUL3) 22 controlled by the output of the OR circuit 15 are provided, the scale is smaller than that of the first embodiment. 16 in circuit configuration
An M sequence with a bit period can be generated. this is,
This is effective when a register that can specify an arbitrary value for the reset value can be used. Third Embodiment FIG. 5 is a block diagram showing a configuration of an M-sequence generation circuit according to a third embodiment of the present invention. In the description of the M-sequence generation circuit according to the present embodiment, the same components as those in FIG. 1 are denoted by the same reference numerals.

In FIG. 5, M-sequence generation circuit 30 includes N
Bit (4 bit) shift registers S0, S1, S
2 and S3, and M XORs inserted between the shift registers 11 according to the generator polynomial
(Exclusive OR) circuit 12, a register (register R) 13 which stores the value of the last stage of shift register 11 and has initial value 0, and N which counts the number of clocks in one cycle of M series.
Bit (4 bit) counter (COUNT) 14 and N
M having the same number of M bits as the bit counter COUNT
A bit (4-bit) register (MASK) 31 (first register) and M (4 bits) which take the logical product of the M-bit register MASK and each bit of the N-bit counter COUNT
AND) consisting of AND circuits 10 to 13
A circuit 32 (second logical operation means), an OR circuit 15 for taking a logical sum of outputs of the AND circuit 32, a register (register L) 16 for holding the value of the OR circuit 15, and a register L
The output value of the OR circuit 15 held by the
5, a NAND circuit 17 for negating the logical product with the value output from the selector 5, a selector (MUL1) 18 controlled by the output of the OR circuit 15, and the OR held by the register L.
Selector controlled by output value of circuit 15 (MUL2)
19.

The N-bit register MASK is a 4-bit register, and its clock may be the same as or different from other registers. Also, an N-bit register MASK
Can be written from an external circuit (not shown).

The AND circuit 32 composed of the AND circuits 10 to 13 is a logical sum, and the input of the AND circuit 10 has the 0th bit (LS) of the N-bit counter COUNT.
B: Least Significant Bit) and N-bit register MA
The 0th bit (LSB) of SK is connected, and AND circuit 1
The input of the OR circuit 15 is connected to the output of 0. A
Similarly, the ND circuit 11 to the AND circuit 13 are connected to the same bit of the N-bit counter COUNT and the N-bit register MASK, and the output is connected to the input of the OR circuit 15.

Hereinafter, the operation of the M-sequence generation circuit 30 configured as described above will be described.

FIG. 6 is a timing chart showing the operation of each part of the M-sequence generation circuit 30.

The initial values of the shift registers S0, S1, S2, S3 are 1, 1, 1, 1 respectively. Also,
0011 is set in the N-bit register MASK in advance from the most significant bit from the outside in advance.

The output of the OR circuit 15 is an N-bit counter C
When the OUT output is 0, each register is in the initial state, and the shift register S0 output is shifted to the shift register S3 from the next rising edge of the clock, and the shift register S3 output and the shift register S0 output are exclusive ORed and shifted to the shift register S2. , The output of the shift register S2 is the shift register S1
The output of the shift register S1 is input to the shift register S0, and the same operation is repeated thereafter to generate a PN code.

When the output of the N-bit counter COUNT is 0011, which is the same as the value of the N-bit register MASK, the value of the register R is input to the shift register S0 at the next rising edge of the clock (), and 0 is inserted in the PN code output. Is done. At the next rising edge of the clock (), the value of the register R is input to the shift register S3, and the value of the shift register S0, that is, 0, is input to the register R.

In the subsequent clock, the output of the shift register S0 is again sent to the shift register S3,
The output and the output of the shift register S0 are exclusive-ORed and input to the shift register S2, the output of the shift register S2 is input to the shift register S1, and the output of the shift register S1 is input to the shift register S0. A code is generated.

As described above, the M-sequence generation circuit 30 according to the third embodiment further includes an N-bit counter CO
An M-bit register (M bits) having the same number of M bits as UNT
ASK) 31 and M A's that take the logical product of M-bit register MASK and each bit of N-bit counter COUNT
AND circuit 32 including ND circuit 10 and AND circuit 13
And an OR circuit 15 that takes the logical sum of the output of the AND circuit 32
Thus, an M sequence in which 0 is inserted at an arbitrary position can be generated in a 16-bit cycle. That is, in the conventional example, insertion of one bit is limited to the beginning or end of one period of the PN code, and 0 cannot be inserted at an arbitrary position in one period. However, in the present embodiment, An M-sequence in which 0 is inserted at an arbitrary position can be generated. Fourth Embodiment FIG. 7 is a block diagram showing a configuration of an M-sequence generation circuit according to a fourth embodiment of the present invention. In this embodiment, the M-sequence generation circuit according to the second embodiment and the M-sequence generation circuit according to the third embodiment
This is a combination of a series generation circuit. In the description of the M-sequence generation circuit according to the present embodiment, the same components as those in FIGS. 3 and 5 are denoted by the same reference numerals.

In FIG. 7, M-sequence generation circuit 40 includes N
Bit (4 bit) shift registers S0, S1, S
2 and S3, and M XORs inserted between the shift registers 11 according to the generator polynomial
A circuit 12 for counting the number of clocks in one cycle of the M sequence N
A bit (4 bit) counter (COUNT) 14, an M bit (4 bit) register (MASK) 31 having the same number of M bits as the N bit counter COUNT, and a logic of each bit of the M bit register MASK and the N bit counter COUNT. An AND circuit 32 composed of M AND circuits 10 to 13 that take a product, an OR circuit 15 that takes a logical sum of outputs of the AND circuit 32, and an arbitrary value can be designated as a reset value. Register (RST) 21 which is controlled to output a reset signal, and selector (MUL3) 22 which is controlled by the output of OR circuit 15
It is composed of

The N-bit register MASK is a 4-bit register, and its clock may be the same as or different from other registers. Also, an N-bit register MASK
Can be written from an external circuit (not shown).

Hereinafter, the operation of the M-sequence generation circuit 40 configured as described above will be described.

FIG. 8 is a timing chart showing the operation of each part of M-sequence generation circuit 40.

Here, the initial values of the shift registers S0 to S3 are all 1, and when the rising edge of the clock is input while the reset signal is input, the shift registers S0 to S3 are reset.
3 are all initialized, that is, 1 is written.

When the output of the N-bit counter COUNT is 3, the output of the OR circuit 15 becomes 0, and at the rising edge of the clock at this time, 0 is written into the shift register S0, and PN_OUT also becomes 0 at the same time. At the same time, the output of the register RST becomes 0, and all the shift registers S0 to S3 are initialized and 1 is written at the next rising edge of the clock ().

At the next rising edge of the clock (), the output of the shift register S3 takes an exclusive OR with the output of the shift register S0 to take the exclusive OR, the output of the shift register S2 goes to the shift register S1, and the shift register S1
The output is input to the shift register S0, and the output of the shift register S0 is input to the shift register S3.
The series shown in FIG. 8 occurs in T.

Again, at the rising edge of the clock when the output of the N-bit counter COUNT is 3, 0 is stored in the shift register S0.
Is written, and 0 is inserted into the PN output.

As described above, the M-sequence generation circuit 40 according to the fourth embodiment is different from the M-sequence generation circuit according to the second embodiment in that an M-bit register having the same number of M bits as the N-bit counter COUNT. (MASK) 31 and M
Bit register MASK and N-bit counter COUNT
AND circuits 10 to AN that take the logical product of each bit of
An AND circuit 32 comprising a D circuit 13;
And an OR circuit 15 that takes the logical sum of the outputs of the M.
A series can be generated, and a generator can be realized with a smaller number of gates than in the third embodiment. This is effective when a register that can specify an arbitrary value for the reset value can be used. Fifth Embodiment FIG. 9 is a block diagram showing a configuration of an M-sequence generation circuit according to a fifth embodiment of the present invention. In the description of the M-sequence generation circuit according to the present embodiment, the same components as those in FIG. 5 are denoted by the same reference numerals.

In FIG. 9, M-sequence generation circuit 50 includes N
Bit (4 bit) shift registers S0, S1, S
2, a shift register 11 consisting of S3, an N-1 bit register (GEN) 51 (second register) having one less number than the shift register 11, and an N-1 bit register GEN output as one input. N-1 A
N-1 XOR circuits 53 (exclusive OR operation) which are inserted between the ND circuit 52 (third logical operation means) and the shift register 11 and have N-1 AND circuit 52 outputs as one input. Means) and a register (register R) 1 which stores the value of the last stage of the shift register 11 and has an initial value 0.
3, an N-bit (4-bit) counter (COUNT) 14 for counting the number of clocks in one cycle of the M series, and an OR circuit 1 for taking the logical sum of the values of each bit of the N-bit counter 14
5, a register (register L) 16 holding the value of the OR circuit 15, and the OR circuit 15 held by the register L
A NAND circuit 17 for negating the logical product of the output value and the value output directly from the OR circuit 15, a selector (MUL1) 18 controlled by the output of the OR circuit 15, and an output of the OR circuit 15 held by the register L And a selector (MUL2) 19 controlled by a value.

The shift registers S0 to S3, the registers R and L are registers operating at the same clock,
The bit register GEN is a 3-bit register that operates with the same or different clock as the shift registers S0 to S3, and can be written from outside (not shown).

XO comprising XOR circuits 0 to 2
Each of the R circuits 53 is an exclusive OR, and each of the AND circuits 52 including the AND circuits 0 to 2 is a logical product. Also, the NAND circuit 17 performs a logical negation, the selector MUL1, the selector MUL2 is a selector, the N-bit counter COUNT is a 4-bit counter,
The OR circuit 15 is a logical sum.

The output of the shift register S3 is input to one input of the XOR circuit 2, the output of the XOR circuit 2 is input to the input of the shift register S2, the output of the shift register S2 is input to one input of the XOR circuit 1, and the XOR circuit 1 Is the input of the shift register S1, and the output of the shift register S1 is the XOR
The output of the XOR circuit 0 is input to one data input of the selector MUL1, the output of the selector MUL1 is input to the input of the shift register S0, the shift register S0
Are connected to the output terminal PN_OUT, the input of the register R, and one input of the selector MUL2.

The output of the register R is connected to the other input of the selector MUL1 and the other input of the selector MUL2.
Are connected, and the selector MUL1 is connected to the OR
When the output of the circuit 15 is 1, the output value of the shift register S1 is output, and when the output of the OR circuit 15 is 0, the value of the register R is output.

The output of the selector MUL2 is connected to the input of the shift register S3 and one of the inputs of the AND circuits 0 to 2, the control signal of the selector MUL2 is connected to the output of the register L, and the selector MUL2 is connected to the register L When the output is 0, the register R output is selected and the register L
When the output is 1, the shift register S0 output is selected.

The 3-bit output of the 3-bit register GEN is connected to the other inputs of the AND circuits 0, 1, and 2, respectively.

The N-bit counter COUNT is a counter that counts up at the same clock as the above registers. Each bit of the N-bit counter COUNT becomes four inputs of the OR circuit 15, and the output of the OR circuit 15 is a control signal of the selector MUL1. And the shift register S
When the output of the OR circuit 15 is 1, the shift registers S1 to S3 are enabled for writing. When the output of the OR circuit 15 is 0, the shift registers S1 to S3 are enabled.
S3 is write-protected.

The output of the OR circuit 15 is also connected to one input of the NAND circuit 17 and the input of the register L. The other input of the NAND circuit 17 is connected to the output of the register L. The output of the NAND circuit 17 becomes an enable signal of the register R. When the output of the NAND circuit 17 is 1, the register R is write-enabled and the output of the NAND circuit 17 is 0.
In this case, the register R is write-protected.

Hereinafter, the operation of M-sequence generation circuit 50 configured as described above will be described.

A bit corresponding to the generator polynomial is stored in 3-bit register GEN. 3-bit register GEN
AND outputs of the selectors MUL2 are taken by AND circuits 0 to 2 and input to the XOR circuits 0 to XOR circuit 2, respectively. XOR circuits 0 to XO
The XOR circuit 53 composed of the R circuit 2 takes the exclusive OR of the AND circuits 0 to 2 and the shift registers S1 to S3, respectively. Therefore, the 3-bit register GE
If a bit corresponding to an arbitrary generator polynomial is stored in N, an M sequence represented by an arbitrary generator polynomial is generated.

For example, shift registers S0, S1, S
If the initial values of S2 and S3 are respectively 1, 1, 1, and 1, and 100 is stored in advance in the 3-bit register GEN, the operation is exactly the same as in the first embodiment.

As described above, the M-sequence generating circuit 50 according to the fifth embodiment further includes an N-1 bit register (GE) having one less number than the shift register 11.
N) 51, N-1 AND circuits 52 having the N-1 bit register GEN output as one input, and the output of the N-1 AND circuits 52 inserted between the shift register 11 and one input. Since it is configured to include N-1 XOR circuits 53, it is possible to realize a PN code (M sequence) generator represented by an arbitrary generator polynomial.
That is, in the conventional example, only the generator polynomial represented by the above-described equation (1) is supported, and when another generator polynomial is realized, it is necessary to redesign the circuit. However, in this embodiment, , A PN code (M-sequence) expressed by an arbitrary generator polynomial can be generated, and there is no need to redesign the circuit. Sixth Embodiment FIG. 10 is a block diagram showing a configuration of an M-sequence generation circuit according to a sixth embodiment of the present invention. In the description of the M-sequence generation circuit according to the present embodiment, the same components as those in FIGS. 3 and 9 are denoted by the same reference numerals.

In FIG. 10, M-sequence generation circuit 60 includes:
N-bit (4-bit) shift registers S0, S1, S
2, S3, an N-1 bit register (GEN) 51 having one less number than the shift register 11, and N-1 ANDs having an N-1 bit register GEN output as one input. A circuit 52, N-1 XOR circuits 53 inserted between the shift register 11 and having N-1 AND circuits 52 outputs as one input, and N bits for counting the number of clocks in one cycle of the M sequence (4-bit) counter (COUNT) 14, an OR circuit 15 for taking the logical sum of the values of the respective bits of the N-bit counter 14, and an arbitrary value can be designated as the reset value.
A register (RST) 21 which is controlled by five outputs to output a reset signal, and a selector (MUL3) 22 which is controlled by the output of the OR circuit 15.

The shift registers S0 to S3, the registers R and L are registers operating at the same clock,
The bit register GEN is a 3-bit register that operates with the same or different clock as the shift registers S0 to S3, and can be written from outside (not shown).

The output of the shift register S3 is input to one input of the XOR circuit 2, the output of the XOR circuit 2 is input to the input of the shift register S2, the output of the shift register S2 is input to one input of the XOR circuit 1, and the XOR circuit 1 Is input to the input of the shift register S1, the output of the shift register S1 is input to one input of the XOR circuit 0, and the output of the XOR circuit 0 is
One of the data inputs of UL3, the output of the selector MUL3 is the input of the shift register S0, and the output of the shift register S0 is the output terminal PN_OUT and the input of the shift register S3 and one of the AND circuit 0, the AND circuit 1, and the AND circuit 2. Each is connected to an input.

The 3-bit output of the 3-bit register GEN is connected to the other inputs of the AND circuits 0, 1, and 2, respectively.

The N-bit counter COUNT is a counter which counts up at the same clock as the register. Each bit of the N-bit counter COUNT becomes four inputs of the OR circuit 15, and the output of the OR circuit 15 is a control signal of the selector MUL3. , And enable signals for the shift registers S1 to S3.

A logic 0 is input to the other input of the selector MUL3, and the output of the OR circuit 15 is connected to the control signal of the selector MUL3. When the output of the OR circuit 15 is 1, the value of the shift register S1 is changed. , OR circuit 15 output is 0
In the case of, logic 0 is selected.

The output of the OR circuit 15 is also connected to the input of a register RST operating at the same clock as the shift registers S0 to S3, and the output of the register RST is connected to the reset input of the shift registers S0 to S3. .

Each of the shift registers S0 to S3 has an initial value, and always writes the initial value in synchronization with a clock when a reset signal is input. Also, shift registers S1 to S
Regarding 3, when the enable signal is 1, the write is permitted,
When 0, writing is prohibited.

Hereinafter, the operation of M-sequence generation circuit 60 configured as described above will be described.

The basic operation of the M-sequence generation circuit 60 is the same as that of the second embodiment.
This is the same as the fifth embodiment.

In FIG. 10, shift registers S0, S1, S
When the initial values of S2 and S3 are set to 1, 1, 1, and 1, respectively, and 100 is stored in advance in the 3-bit register GEN, the operation is exactly the same as in the second embodiment.

As described above, the M-sequence generation circuit 60 according to the sixth embodiment is different from the M-sequence generation circuit according to the second embodiment in that N−1 Bit register (GEN) 51 and N
N-1 AND circuits 52 each having a -1 bit register GEN output as one input and N-1 AND circuits 52 inserted between the shift registers 11 and having N-1 AND circuit 52 outputs as one input. The XOR circuit 53 is provided, so that the PN code (M
A (series) generator can be realized with a smaller number of gates than in the fifth embodiment. This is effective when a register that can specify an arbitrary value for the reset value can be used. Seventh Embodiment FIG. 11 is a block diagram illustrating a configuration of an M-sequence generation circuit according to a seventh embodiment of the present invention. The present embodiment is a combination of the M-sequence generation circuit according to the third embodiment and the M-sequence generation circuit according to the fifth embodiment. 5 and 9 for explaining the M-sequence generation circuit according to the present embodiment.
The same components as those described above are denoted by the same reference numerals.

In FIG. 11, the M-sequence generation circuit 70
N-bit (4-bit) shift registers S0, S1, S
2 and S3, an N-bit (4-bit) counter (COUNT) 14 for counting the number of clocks in one cycle of the M sequence, and an N-bit counter COUNT
An M-bit (4-bit) register (MASK) 31 having the same number of M bits as M, and M-bit registers MASK and N
M which takes the logical product of each bit of the bit counter COUNT
AND circuit 32 including four (four) AND circuits 10 to 13, an OR circuit 15 that takes the logical sum of the outputs of the AND circuits 32, and an N−1 bit register having one less number than the shift register 11 (GEN) 51 and N
N-1 AND circuits 52 each having a -1 bit register GEN output as one input and N-1 AND circuits 52 inserted between the shift registers 11 and having N-1 AND circuit 52 outputs as one input. An XOR circuit 53, a register (register R) 13 for storing the value of the last stage of the shift register 11 and having an initial value 0, and an N-bit (4-bit) counter (COUNT) for counting the number of clocks in one cycle of the M series )
14, an OR circuit 15 that takes the logical sum of the values of the respective bits of the N-bit counter 14, a register (register L) 16 that holds the value of the OR circuit 15, and an output value of the OR circuit 15 held by the register L A NAND circuit 17 for directly negating a logical product with a value output from the OR circuit 15;
Selector (MUL1) controlled by output of R circuit 15
18 and a selector (MUL2) 19 controlled by the output value of the OR circuit 15 held by the register L.

The N-bit register MASK is a 4-bit register, and its clock may be the same as or different from other registers. Also, an N-bit register MA
SK can be written from an external circuit (not shown).

An AND circuit 32 composed of AND circuits 10 to 13 is a logical sum, and the input of the AND circuit 10 has the 0th bit (LSB) of the N-bit counter COUNT as an input.
And the 0th bit (LSB) of the N-bit register MASK are connected, and the output is connected to the input of the OR circuit 15. Similarly, the AND circuits 11 to 13 are connected to the same bit of the N-bit counter COUNT and the N-bit register MASK, and the output is connected to the input of the OR circuit 15.

The operation of M-sequence generation circuit 70 having the above-described configuration will be described below.

The basic operation of the M-sequence generation circuit 70 is the same as that of the third embodiment.
This is the same as the fifth embodiment.

In FIG. 11, shift registers S0, S1, S
When the initial values of S2 and S3 are set to 1, 1, 1, and 1, respectively, and 100 is stored in advance in the 3-bit register GEN, the operation is exactly the same as in the third embodiment.

As described above, the M-sequence generation circuit 70 according to the seventh embodiment is configured by combining the M-sequence generation circuit according to the third embodiment and the M-sequence generation circuit according to the fifth embodiment. Therefore, 0 can be inserted at an arbitrary position in a 16-bit cycle, and an M sequence represented by an arbitrary generator polynomial can be generated. Eighth Embodiment FIG. 12 is a block diagram showing a configuration of an M-sequence generation circuit according to an eighth embodiment of the present invention. This embodiment is a combination of the M-sequence generation circuit according to the fourth embodiment and the M-sequence generation circuit according to the sixth embodiment. 7 and 1 for explaining the M-sequence generation circuit according to the present embodiment.
The same components as those of 0 are denoted by the same reference numerals.

In FIG. 12, M-sequence generation circuit 80 includes:
N-bit (4-bit) shift registers S0, S1, S
2, S3, an N-1 bit register (GEN) 51 having one less number than the shift register 11, and N-1 ANDs having an N-1 bit register GEN output as one input. A circuit 52, N-1 XOR circuits 53 inserted between the shift register 11 and having N-1 AND circuits 52 outputs as one input, and N bits for counting the number of clocks in one cycle of the M sequence (4-bit) counter (COUNT) 14, M-bit (4-bit) register (MASK) 31 having the same number of M bits as N-bit counter COUNT, and logical product of M-bit register MASK and each bit of N-bit counter COUNT An AND circuit 32 composed of M AND circuits 10 to 13 and an OR of the output of the AND circuit 32 It comprises a circuit 15, a register (RST) 21 which can specify an arbitrary value for the reset value, is controlled by the output of the OR circuit 15 and outputs a reset signal, and a selector (MUL3) 22 which is controlled by the output of the OR circuit 15 Is done.

N-bit register MASK is a 4-bit register, and its clock may be the same as or different from other registers. Also, an N-bit register MA
SK can be written from an external circuit (not shown).

An AND circuit 32 composed of AND circuits 10 to 13 is a logical sum, and the input of the AND circuit 10 is the 0th bit (LSB) of the N-bit counter COUNT.
And the 0th bit (LSB) of the N-bit register MASK are connected, and the output is connected to the input of the OR circuit 15. Similarly, the AND circuits 11 to 13 are connected to the same bit of the N-bit counter COUNT and the N-bit register MASK, and the output is connected to the input of the OR circuit 15.

Hereinafter, the operation of M-sequence generation circuit 80 configured as described above will be described.

The basic operation of the M-sequence generation circuit 80 is the same as that of the fourth embodiment.
This is the same as the sixth embodiment.

In FIG. 12, shift registers S0, S1, S
When the initial values of S2 and S3 are respectively 1, 1, 1, and 1, and 100 is stored in advance in the 3-bit register GEN, the operation is exactly the same as that of the fourth embodiment.

As described above, the M-sequence generation circuit 80 according to the eighth embodiment is configured by combining the M-sequence generation circuit according to the fourth embodiment and the M-sequence generation circuit according to the sixth embodiment. Therefore, 0 can be inserted at an arbitrary position in a 16-bit cycle, and an M sequence represented by an arbitrary generator polynomial can be generated. This means that if a register that can specify an arbitrary value as the reset value can be used, the seventh
It can be realized with a smaller number of gates than the embodiment. Ninth Embodiment FIG. 13 is a block diagram showing a configuration of an M-sequence generation circuit according to a ninth embodiment of the present invention. In the description of the M-sequence generation circuit according to the present embodiment, the same components as those in FIG. 1 are denoted by the same reference numerals.

In FIG. 13, M-sequence generation circuit 90 includes:
N-bit (4-bit) shift registers S0, S1, S
2 and S3, and M XORs inserted between the shift registers 11 according to the generator polynomial
A circuit 12 and an N-1 bit (3-bit) register (DR) 91 having one less number than the shift register 11
(Third register) and N-1 selectors (MUL10) having an N-1 bit register DR output as a control signal.
... MUL 12) 92 (second selecting means), a register (register R) 13 which stores the value of the last stage of the shift register 11 and has an initial value 0, and N which counts the number of clocks in one cycle of the M sequence. Bit (4 bit) counter (COUN
T) 14, an OR circuit 15 for taking the logical sum of the values of the respective bits of the N-bit counter 14, a register (register L) 16 for holding the value of the OR circuit 15, and an output of the OR circuit 15 held by the register L NAND circuit 17 for negating the logical product of the value and the value output directly from OR circuit 15
And a selector (MU) controlled by the output of the OR circuit 15
L1) 18 and the OR circuit 1 held by the register L
And a selector (MUL2) 19 controlled by five output values.

The N-1 bit register DR is a 3-bit register, and its clock may be the same as or different from other registers. Also, a 3-bit register DR
Can be written from an external circuit (not shown).

Selectors MUL10 to MUL12
Is a selector that switches between the outstanding output of the shift register 11 and each bit output of the 3-bit register DR.

The input of the selector MUL12 is connected to the output of the XOR circuit 12 and the output of the selector MUL2.
The output of the selector MUL12 is connected to the input of the shift register S2. The input of the selector MUL11 is
The output of the shift register S2 and the output of the selector MUL2 are connected, and the output of the selector MUL11 is connected to the input of the shift register S1. The input of the selector MUL10 is the output of the shift register S1 and the selector MUL2.
The output of the selector MUL10 is connected to the input of the shift register S0.

The control signal of the selector MUL12 is connected to the most significant bit of the 3-bit register DR. When the control bit is "0", the selector MUL12 sets the XOR circuit 12
When the output is selected and the control bit is 1, the selector MUL1
2 selects the selector MUL2 output. The control signal of the selector MUL11 is connected to the intermediate bit of the 3-bit register DR. When the control bit is 0, the selector MUL11 selects the output of the shift register S2, and when the control bit is 1, the selector MUL11 is Selector MUL
Select 2 outputs. Similarly, the control signal of the selector MUL10 is connected to the least significant bit of the 3-bit register DR. When the control bit is 0, the selector MUL10 selects the output of the shift register S1, and when the control bit is 1,
The selector MUL10 selects the output of the selector MUL2.

Hereinafter, the operation of M-sequence generation circuit 90 configured as described above will be described.

The basic operation of the M-sequence generation circuit 90 is the same as that of the first embodiment, and the operation of the characteristic portion will be described.

In FIG. 13, the code length of the PN code (M sequence) can be arbitrarily designated by the value in the 3-bit register DR. For example, in a 3-bit register DR, 000
Is written, the M-sequence generation circuit 90 generates the same M-sequence as in the first embodiment,
When 100 is written to R, the M-sequence generation circuit 90 can generate an M-sequence having a code length of 8.

As described above, the M-sequence generation circuit 90 according to the ninth embodiment includes an N-1 bit (3-bit) register (DR) 91 having a number one less than the shift register 11, and N N-1 selectors (MUL10 to MUL10) having a 1-bit register DR output as a control signal
MUL 12) 92, so that the M-sequence 1
The number of bits of the period can be arbitrarily selected by a power of two, and can be applied to CDMA systems having various spreading factors. Tenth Embodiment FIG. 14 is a block diagram showing a configuration of an M-sequence generation circuit according to a tenth embodiment of the present invention. In the present embodiment, the second
This is a combination of the M-sequence generation circuit according to the ninth embodiment and the M-sequence generation circuit according to the ninth embodiment. In the description of the M-sequence generation circuit according to the present embodiment, the same components as those in FIGS. 3 and 13 are denoted by the same reference numerals.

Referring to FIG. 14, M-sequence generation circuit 100
Are N-bit (4-bit) shift registers S0, S
1, a shift register 11 composed of S2 and S3, M XOR circuits 12 inserted between the shift registers 11 according to a generator polynomial, and an N-1 bit (3-bit) register having one less than the shift register 11 (DR)
91 and N-1 selectors (MUL10 to MUL12) having an N-1 bit register DR output as a control signal
92, an N-bit (4-bit) counter (COUNT) 14 for counting the number of clocks in one cycle of the M series, and an OR circuit 1 for taking the logical sum of the values of each bit of the N-bit counter 14
5 and an arbitrary value can be designated as the reset value.
It comprises a register (RST) 21 controlled by an output to output a reset signal, and a selector (MUL3) 22 controlled by the output of the OR circuit 15.

The input of the selector MUL12 is connected to the output of the XOR circuit 12 and the output of the selector MUL2.
The output of the selector MUL12 is connected to the input of the shift register S2. The input of the selector MUL11 is
The output of the shift register S2 and the output of the selector MUL2 are connected, and the output of the selector MUL11 is connected to the input of the shift register S1. The input of the selector MUL10 is the output of the shift register S1 and the selector MUL2.
The output of the selector MUL10 is connected to the input of the shift register S0.

The control signal of the selector MUL12 is connected to the most significant bit of the 3-bit register DR, and when the control bit is 0, the selector MUL12 is connected to the XOR circuit 12
When the output is selected and the control bit is 1, the selector MUL1
2 selects the output of the shift register S0. The control signal of the selector MUL11 is connected to the intermediate bit of the 3-bit register DR. When the control bit is 0, the selector MUL11 selects the output of the shift register S2, and when the control bit is 1, the selector MUL11 is Select the output of the shift register S0. Similarly, the control signal of the selector MUL10 is connected to the least significant bit of the 3-bit register DR, and when the control bit is 0, the selector MUL10
Selects the output of the shift register S1, and when the control bit is 1, the selector MUL10 selects the output of the shift register S0.

Hereinafter, the operation of M-sequence generation circuit 100 configured as described above will be described.

The basic operation of the M-sequence generation circuit 100 is the same as that of the second embodiment, and the operation of the characteristic portion will be described.

In FIG. 14, the code length of the PN code (M sequence) can be arbitrarily specified by the value in the 3-bit register DR. For example, in a 3-bit register DR, 000
Is written, the M-sequence generation circuit 100 generates the same M-sequence as in the second embodiment,
When 100 is written in R, the M-sequence generation circuit 100 can generate an M-sequence having a code length of 8.

As described above, the M-sequence generation circuit 100 according to the tenth embodiment further includes a shift register 1
N-1 bits (3 bits) having one less than one
Register (DR) 91 and N-1 selectors (MUL1) having an N-1 bit register DR output as a control signal.
0 to MUL12) 92, the number of bits in one cycle of the M sequence can be arbitrarily selected by a power of 2 and a register capable of specifying an arbitrary value as a reset value can be used. Can be realized with a smaller number of gates than in the ninth embodiment, and can be applied to CDMA systems with various spreading factors. Eleventh Embodiment FIG. 15 is a block diagram showing a configuration of an M-sequence generation circuit according to an eleventh embodiment of the present invention. In the present embodiment, the third
This is a combination of the M-sequence generation circuit according to the ninth embodiment and the M-sequence generation circuit according to the ninth embodiment. In the description of the M-sequence generation circuit according to the present embodiment, the same components as those in FIGS. 5 and 13 are denoted by the same reference numerals.

In FIG. 15, M-sequence generation circuit 110
Are N-bit (4-bit) shift registers S0, S
1, a shift register 11 composed of S2 and S3, M XOR circuits 12 inserted between the shift registers 11 according to a generator polynomial, and an N-1 bit (3-bit) register having one less than the shift register 11 (DR)
91 and N-1 selectors (MUL10 to MUL12) having an N-1 bit register DR output as a control signal
92, a register (register R) 13 which stores the value of the last stage of the shift register 11 and has an initial value 0, and an N-bit (4-bit) counter (COUNT) 14 for counting the number of clocks in one cycle of the M sequence. And N bit counter COU
An M-bit (4-bit) register (MASK) 31 having the same number of M bits as NT;
AND circuit 32 composed of M (four) AND circuits 10 to 13 which take the logical product of each bit of the N bit counter COUNT, an OR circuit 15 which takes the logical sum of the output of the AND circuit 32, and OR A register (register L) 16 for holding the value of the circuit 15; a NAND circuit 17 for negating the logical product of the output value of the OR circuit 15 held by the register L and the value output directly from the OR circuit 15;
Selector (MUL1) controlled by output of R circuit 15
18 and a selector (MUL2) 19 controlled by the output value of the OR circuit 15 held by the register L.

The N-bit register MASK is a 4-bit register, and its clock may be the same as or different from other registers. Also, an N-bit register MA
SK can be written from an external circuit (not shown).

An AND circuit 32 composed of AND circuits 10 to 13 is a logical sum, and an input of the AND circuit 10 has a 0-th bit (LS) of an N-bit counter COUNT.
B) and the 0th bit (LS) of the N-bit register MASK
B) is connected, and the output of the AND circuit 10 is connected to the OR circuit 1
5 inputs are connected. Similarly, the AND circuits 11 to 13 are connected to the same bit of the N-bit counter COUNT and the N-bit register MASK, and the output is connected to the input of the OR circuit 15.

Hereinafter, the operation of M-sequence generation circuit 110 configured as described above will be described.

The basic operation of the M-sequence generation circuit 110 is the same as that of the combination of the third and ninth embodiments.

In FIG. 15, shift registers S0, S1, S
When the initial values of S2 and S3 are set to 1, 1, 1, and 1, for example, and 100 is written in the 3-bit register DR, the M-sequence generation circuit 110 generates an M-sequence equivalent to that in the ninth embodiment. appear.

As described above, the M-sequence generation circuit 110 according to the eleventh embodiment includes the M-sequence generation circuit 110 according to the third embodiment.
Since the sequence generation circuit and the M-sequence generation circuit according to the ninth embodiment are combined, the number of bits in one cycle of the M-sequence can be arbitrarily selected by a power of 2, and 0 is inserted at an arbitrary position. Can be generated. Twelfth Embodiment FIG. 16 is a block diagram showing a configuration of an M-sequence generation circuit according to a twelfth embodiment of the present invention. In the present embodiment, the fourth
This is a combination of the M-sequence generation circuit according to the tenth embodiment and the M-sequence generation circuit according to the tenth embodiment. In the description of the M-sequence generation circuit according to the present embodiment, the same components as those in FIGS. 7 and 14 are denoted by the same reference numerals.

In FIG. 16, M-sequence generation circuit 120
Are N-bit (4-bit) shift registers S0, S
1, a shift register 11 composed of S2 and S3, M XOR circuits 12 inserted between the shift registers 11 according to a generator polynomial, and an N-1 bit (3-bit) register having one less than the shift register 11 (DR)
91 and N-1 selectors (MUL10 to MUL12) having an N-1 bit register DR output as a control signal
92, an N-bit (4-bit) counter (COUNT) 14 for counting the number of clocks in one cycle of the M sequence, an M-bit (4-bit) register (MASK) 31 having the same number of M bits as the N-bit counter COUNT, AND circuits 10 to AND circuit 1 which take the logical product of each bit of an M-bit register MASK and an N-bit counter COUNT
3, an OR circuit 15 that takes the logical sum of the outputs of the AND circuit 32, and a register (RST) that can specify an arbitrary value for the reset value and that is controlled by the output of the OR circuit 15 to output a reset signal 21 and the OR circuit 1
And a selector (MUL3) 22 controlled by five outputs.

N-bit register MASK is a 4-bit register, and its clock may be the same as or different from other registers. Also, an N-bit register MA
SK can be written from an external circuit (not shown).

An AND circuit 32 composed of AND circuits 10 to 13 is a logical sum, and the input of the AND circuit 10 has the 0th bit (LS) of the N-bit counter COUNT.
B) and the 0th bit (LS) of the N-bit register MASK
B) is connected, and the output of the AND circuit 10 is connected to the OR circuit 1
5 inputs are connected. Similarly, the AND circuits 11 to 13 are connected to the same bit of the N-bit counter COUNT and the N-bit register MASK, and the output is connected to the input of the OR circuit 15.

Hereinafter, the operation of M-sequence generation circuit 120 configured as described above will be described.

The basic operation of the M-sequence generation circuit 120 is the same as that obtained by combining the fourth and tenth embodiments.

In FIG. 16, shift registers S0, S1, S
When the initial values of S2 and S3 are set to 1, 1, 1, and 1, for example, when 100 is written to the 3-bit register DR,
The M-sequence generation circuit 120 generates an M-sequence equivalent to that of the tenth embodiment.

As described above, the M-sequence generation circuit 120 according to the twelfth embodiment is different from the M-sequence generation circuit 120 according to the fourth embodiment.
Since the sequence generation circuit and the M-sequence generation circuit according to the tenth embodiment are configured in combination, the number of bits in one cycle of the M-sequence can be arbitrarily selected by a power of 2, and 0 is inserted at an arbitrary position. Can be generated. This can be realized with a smaller number of gates than in the eleventh embodiment when a register capable of designating an arbitrary value as the reset value can be used. Thirteenth Embodiment FIG. 17 is a block diagram showing a configuration of an M-sequence generation circuit according to a thirteenth embodiment of the present invention. In the present embodiment, the fifth
This is a combination of the M-sequence generation circuit according to the ninth embodiment and the M-sequence generation circuit according to the ninth embodiment. In the description of the M-sequence generation circuit according to the present embodiment, the same components as those in FIGS. 9 and 13 are denoted by the same reference numerals.

In FIG. 17, M-sequence generating circuit 130
Are N-bit (4-bit) shift registers S0, S
, S2, S3, an N-1 bit register (GEN) 51 having one less number than the shift register 11, and an N-1 bit register GEN
N-1 AND circuits 52 having an output as one input
And N-1 ANs inserted between the shift registers 11
N-1 XOs having D circuit 52 output as one input
An R circuit 53 and an N-1 bit (3-bit) register (DR) 91 having one less number than the shift register 11
And N-1 selectors (MUL10 to MUL12) 92 having an N-1 bit register DR output as a control signal
A register (register R) 13 which stores the value of the last stage of the shift register 11 and has an initial value 0, and an N-bit (4-bit) counter (COUNT) 14 which counts the number of clocks in one cycle of the M series. , An OR circuit 15 for taking the logical sum of the values of the respective bits of the N-bit counter 14, and an OR circuit 15
(Register L) 16 for holding the value of the OR circuit 15 and NAN for negating the logical product of the output value of the OR circuit 15 held by the register L and the value output directly from the OR circuit 15
D circuit 17, selector (MUL 1) 18 controlled by output of OR circuit 15, and selector (MUL 1) controlled by output value of OR circuit 15 held by register L
2) 19).

The N-1 bit register DR is a 3-bit register, and its clock may be the same as or different from other registers. Also, a 3-bit register DR
Can be written from an external circuit (not shown).

The input of the selector MUL12 is connected to the output of the XOR circuit 12 and the output of the selector MUL2.
The output of the selector MUL12 is connected to the input of the shift register S2. The input of the selector MUL11 is
The output of the shift register S2 and the output of the selector MUL2 are connected, and the output of the selector MUL11 is connected to the input of the shift register S1. The input of the selector MUL10 is the output of the shift register S1 and the selector MUL2.
The output of the selector MUL10 is connected to the input of the shift register S0.

The control signal of the selector MUL12 is connected to the most significant bit of the 3-bit register DR. When the control bit is "0", the selector MUL12 sets the XOR circuit 12
When the output is selected and the control bit is 1, the selector MUL1
2 selects the selector MUL2 output. The control signal of the selector MUL11 is connected to the intermediate bit of the 3-bit register DR. When the control bit is 0, the selector MUL11 selects the output of the shift register S2, and when the control bit is 1, the selector MUL11 is Selector MUL
Select 2 outputs. Similarly, the control signal of the selector MUL10 is connected to the least significant bit of the 3-bit register DR. When the control bit is 0, the selector MUL10 selects the output of the shift register S1, and when the control bit is 1,
The selector MUL10 selects the output of the selector MUL2.

The operation of M-sequence generation circuit 130 having the above-described configuration will be described below.

The basic operation of the M-sequence generation circuit 130 is the same as that obtained by combining the fifth and ninth embodiments.

In FIG. 17, the code length of the PN code (M sequence) can be arbitrarily specified by the value in the 3-bit register DR. For example, when 000 is written in the 3-bit register DR, the present M-sequence generation circuit generates exactly the same M-sequence as in the fifth embodiment. An M-sequence having a length of 8 can be generated.

As described above, the M-sequence generation circuit 130 according to the thirteenth embodiment includes the M-sequence generation circuit 130 according to the fifth embodiment.
Since the sequence generation circuit and the M-sequence generation circuit according to the ninth embodiment are configured in combination, the number of bits in one cycle of the M-sequence can be arbitrarily selected by a power of 2, and an arbitrary generation polynomial 1 Can be generated, and can be applied to CDMA systems with various spreading factors. Fourteenth Embodiment FIG. 18 is a block diagram showing a configuration of an M-sequence generation circuit according to a fourteenth embodiment of the present invention. In the present embodiment, the sixth
This is a combination of the M-sequence generation circuit according to the tenth embodiment and the M-sequence generation circuit according to the tenth embodiment. In the description of the M-sequence generation circuit according to the present embodiment, the same components as those in FIGS. 10 and 14 are denoted by the same reference numerals.

In FIG. 18, M-sequence generation circuit 140
Are N-bit (4-bit) shift registers S0, S
, S2, S3, an N-1 bit register (GEN) 51 having one less number than the shift register 11, and an N-1 bit register GEN
N-1 AND circuits 52 having an output as one input
And N-1 ANs inserted between the shift registers 11
N-1 XOs having D circuit 52 output as one input
An R circuit 53 and an N-1 bit (3-bit) register (DR) 91 having one less number than the shift register 11
And N-1 selectors (MUL10 to MUL12) 92 having an N-1 bit register DR output as a control signal
And an N-bit (4-bit) counter (COUNT) 14 for counting the number of clocks in one cycle of the M series, and an OR circuit 1 for taking the logical sum of the values of each bit of the N-bit counter 14
5 and an arbitrary value can be designated as the reset value.
It comprises a register (RST) 21 controlled by an output to output a reset signal, and a selector (MUL3) 22 controlled by the output of the OR circuit 15.

The input of the selector MUL12 is connected to the output of the XOR circuit 12 and the output of the selector MUL2.
The output of the selector MUL12 is connected to the input of the shift register S2. The input of the selector MUL11 is
The output of the shift register S2 and the output of the selector MUL2 are connected, and the output of the selector MUL11 is connected to the input of the shift register S1. The input of the selector MUL10 is the output of the shift register S1 and the selector MUL2.
The output of the selector MUL10 is connected to the input of the shift register S0.

The control signal of the selector MUL12 is connected to the most significant bit of the 3-bit register DR. When the control bit is "0", the selector MUL12 sets the XOR circuit 12
When the output is selected and the control bit is 1, the selector MUL1
2 selects the selector MUL2 output. The control signal of the selector MUL11 is connected to the intermediate bit of the 3-bit register DR. When the control bit is 0, the selector MUL11 selects the output of the shift register S2, and when the control bit is 1, the selector MUL11 is Selector MUL
Select 2 outputs. Similarly, the control signal of the selector MUL10 is connected to the least significant bit of the 3-bit register DR. When the control bit is 0, the selector MUL10 selects the output of the shift register S1, and when the control bit is 1,
The selector MUL10 selects the output of the selector MUL2.

Hereinafter, the operation of M-sequence generation circuit 140 configured as described above will be described.

The basic operation of the M-sequence generation circuit 130 is the same as that obtained by combining the sixth and tenth embodiments.

In FIG. 18, the code length of the PN code (M sequence) can be arbitrarily specified by the value in the 3-bit register DR. For example, when 000 is written in the 3-bit register DR, the present M-sequence generation circuit generates exactly the same M-sequence as in the sixth embodiment. An M-sequence having a length of 8 can be generated.

As described above, the M-sequence generation circuit 140 according to the fourteenth embodiment is different from the M-sequence generation circuit 140 according to the sixth embodiment.
Since the sequence generation circuit and the M-sequence generation circuit according to the tenth embodiment are configured in combination, the number of bits in one cycle of the M-sequence can be arbitrarily selected by a power of 2, and can be expressed by an arbitrary generation polynomial. When a register capable of generating an M-sequence to be expressed and capable of specifying an arbitrary value as a reset value can be used, the present invention can be realized with a smaller number of gates than in the thirteenth embodiment. The present invention can be applied to CDMA systems with various spreading factors. Fifteenth Embodiment FIG. 19 is a block diagram showing a configuration of an M-sequence generation circuit according to a fifteenth embodiment of the present invention. In the present embodiment, the seventh
This is a combination of the M-sequence generation circuit according to the thirteenth embodiment and the M-sequence generation circuit according to the thirteenth embodiment. In the description of the M-sequence generation circuit according to the present embodiment, the same components as those in FIGS. 11 and 17 are denoted by the same reference numerals.

In FIG. 19, M-sequence generation circuit 150
Are N-bit (4-bit) shift registers S0, S
, S2, S3, an N-1 bit register (GEN) 51 having one less number than the shift register 11, and an N-1 bit register GEN
N-1 AND circuits 52 having an output as one input
And N-1 ANs inserted between the shift registers 11
N-1 XOs having D circuit 52 output as one input
An R circuit 53 and an N-1 bit (3-bit) register (DR) 91 having one less number than the shift register 11
And N-1 selectors (MUL10 to MUL12) 92 having an N-1 bit register DR output as a control signal
A register (register R) 13 which stores the value of the last stage of the shift register 11 and has an initial value 0, and an N-bit (4-bit) counter (COUNT) 14 which counts the number of clocks in one cycle of the M series. , N-bit counter COUNT
An M-bit (4-bit) register (MASK) 31 having the same number of M bits as M, and M-bit registers MASK and N
M which takes the logical product of each bit of the bit counter COUNT
An AND circuit 32 including four (four) AND circuits 10 to 13; an OR circuit 15 for obtaining a logical sum of outputs of the AND circuit 32; and a register (register L) 16 for holding the value of the OR circuit 15; , A NAND circuit 17 for negating the logical product of the output value of the OR circuit 15 held by the register L and the value output directly from the OR circuit 15, and a selector (MUL1) 18 controlled by the output of the OR circuit 15
And a selector (MUL2) 19 controlled by the output value of the OR circuit 15 held by the register L.

The N-1 bit register DR is a 3-bit register, and its clock may be the same as or different from other registers. Also, a 3-bit register DR
Can be written from an external circuit (not shown).

The input of the selector MUL12 is connected to the output of the XOR circuit 12 and the output of the selector MUL2.
The output of the selector MUL12 is connected to the input of the shift register S2. The input of the selector MUL11 is
The output of the shift register S2 and the output of the selector MUL2 are connected, and the output of the selector MUL11 is connected to the input of the shift register S1. The input of the selector MUL10 is the output of the shift register S1 and the selector MUL2.
The output of the selector MUL10 is connected to the input of the shift register S0.

The control signal of the selector MUL12 is connected to the most significant bit of the 3-bit register DR. When the control bit is "0", the selector MUL12 controls the XOR circuit 12
When the output is selected and the control bit is 1, the selector MUL1
2 selects the selector MUL2 output. The control signal of the selector MUL11 is connected to the intermediate bit of the 3-bit register DR. When the control bit is 0, the selector MUL11 selects the output of the shift register S2, and when the control bit is 1, the selector MUL11 is Selector MUL
Select 2 outputs. Similarly, the control signal of the selector MUL10 is connected to the least significant bit of the 3-bit register DR. When the control bit is 0, the selector MUL10 selects the output of the shift register S1, and when the control bit is 1,
The selector MUL10 selects the output of the selector MUL2.

The operation of M-sequence generation circuit 150 having the above-described configuration will be described below.

The basic operation of the M-sequence generation circuit 150 is the same as that of the seventh and thirteenth embodiments combined.

In FIG. 19, the code length of the PN code (M sequence) can be arbitrarily specified by the value in the 3-bit register DR. For example, when 000 is written in the 3-bit register DR, the M-sequence generation circuit 150 generates the same M-sequence as in the seventh embodiment, and 100
Is written, the M-sequence generation circuit 150
A sequence can be generated.

As described above, the M-sequence generation circuit 150 according to the fifteenth embodiment is different from the M-sequence generation circuit 150 according to the seventh embodiment.
Since the sequence generation circuit and the M-sequence generation circuit according to the thirteenth embodiment are configured in combination, the number of bits in one cycle of the M-sequence can be arbitrarily selected by a power of 2, and can be expressed by an arbitrary generation polynomial. In addition, an M sequence in which one bit of 0 is inserted at an arbitrary position in one cycle can be generated, and can be applied to CDMA systems having various spreading factors. Sixteenth Embodiment FIG. 20 is a block diagram showing a configuration of an M-sequence generation circuit according to a sixteenth embodiment of the present invention. In the present embodiment, the eighth
This is a combination of the M-sequence generation circuit according to the fourth embodiment and the M-sequence generation circuit according to the fourteenth embodiment. In the description of the M-sequence generation circuit according to the present embodiment, the same components as those in FIGS. 12 and 18 are denoted by the same reference numerals.

In FIG. 20, M-sequence generation circuit 160
Are N-bit (4-bit) shift registers S0, S
, S2, S3, an N-1 bit register (GEN) 51 having one less number than the shift register 11, and an N-1 bit register GEN
N-1 AND circuits 52 having an output as one input
And N-1 ANs inserted between the shift registers 11
N-1 XOs having D circuit 52 output as one input
An R circuit 53 and an N-1 bit (3-bit) register (DR) 91 having one less number than the shift register 11
And N-1 selectors (MUL10 to MUL12) 92 having an N-1 bit register DR output as a control signal
An N-bit (4-bit) counter (COUNT) 14 for counting the number of clocks in one cycle of the M series, an M-bit (4-bit) register (MASK) 31 having the same number of M bits as the N-bit counter COUNT, M AND circuits 10 to 1 for ANDing each bit of an M-bit register MASK and an N-bit counter COUNT
3, an OR circuit 15 that takes the logical sum of the outputs of the AND circuit 32, and a register (RST) that can specify an arbitrary value for the reset value and that is controlled by the output of the OR circuit 15 to output a reset signal 21 and the OR circuit 1
And a selector (MUL3) 22 controlled by five outputs.

The input of the selector MUL12 is connected to the output of the XOR circuit 12 and the output of the selector MUL2.
The output of the selector MUL12 is connected to the input of the shift register S2. The input of the selector MUL11 is
The output of the shift register S2 and the output of the selector MUL2 are connected, and the output of the selector MUL11 is connected to the input of the shift register S1. The input of the selector MUL10 is the output of the shift register S1 and the selector MUL2.
The output of the selector MUL10 is connected to the input of the shift register S0.

The control signal of the selector MUL12 is connected to the most significant bit of the 3-bit register DR. When the control bit is "0", the selector MUL12 sets the XOR circuit 12
When the output is selected and the control bit is 1, the selector MUL1
2 selects the selector MUL2 output. The control signal of the selector MUL11 is connected to the intermediate bit of the 3-bit register DR. When the control bit is 0, the selector MUL11 selects the output of the shift register S2, and when the control bit is 1, the selector MUL11 is Selector MUL
Select 2 outputs. Similarly, the control signal of the selector MUL10 is connected to the least significant bit of the 3-bit register DR. When the control bit is 0, the selector MUL10 selects the output of the shift register S1, and when the control bit is 1,
The selector MUL10 selects the output of the selector MUL2.

Hereinafter, the operation of M-sequence generation circuit 160 configured as described above will be described.

The basic operation of the M-sequence generation circuit 160 is the same as that of the combination of the eighth and fourteenth embodiments.

In FIG. 20, the code length of the PN code (M sequence) can be arbitrarily specified by the value in the 3-bit register DR. For example, when 000 is written in the 3-bit register DR, the present M-sequence generation circuit generates exactly the same M-sequence as in the sixth embodiment. An M-sequence having a length of 8 can be generated.

As described above, the M-sequence generation circuit 160 according to the sixteenth embodiment is different from the M-sequence generation circuit 160 according to the eighth embodiment.
Since the sequence generation circuit and the M-sequence generation circuit according to the fourteenth embodiment are configured in combination, the number of bits in one cycle of the M-sequence can be arbitrarily selected by a power of 2 and can be expressed by an arbitrary generation polynomial. It is possible to generate an M sequence in which one bit of 0 is inserted at an arbitrary position in one cycle. In the present embodiment, when an arbitrary register initial value is given, the M-sequence generator can be configured with a smaller number of gates than in the fifteenth embodiment, and CDMA with various spreading factors can be used.
It can be applied to the system.

Therefore, it is preferable to apply the M-sequence generation circuit having such features to a PN code generation circuit used in a mobile communication system using the CDMA communication system.

In each of the above embodiments, the case where one cycle of the M sequence is 16 bits or less has been described. However, the shift registers S0 to S3 are replaced with the shift registers S0 to SN-1 (N-1
Is an integer of 1 or more), whereby an M-sequence generator having a period of 2 ^N bits can be configured.

Further, in each of the above embodiments, the circuit configuration limited to the M-sequence generation circuit among the PN code generation circuits is described. However, two M-sequence generation circuits are prepared, and their PN_OUTs are mutually exclusive. A GOLD code generation circuit can be realized by connecting by logical OR. FIG. 21 shows a configuration diagram of the GOLD code generation circuit. In the figure, any of the M-sequence generation circuits according to the above-described embodiments can be used for the M-sequence generation circuit 1 and the M-sequence generation circuit 2.

The types, numbers, connection methods, and the like of the gate circuits, shift registers, selectors, and the like that constitute the M-sequence generation circuit are not limited to the above-described embodiments.

[0179]

In the M-sequence generation circuit according to the present invention, an N-bit shift register for shifting and storing each value, and M exclusive-OR operation means inserted between the shift registers according to the generator polynomial An N-bit counter for counting the number of clocks in one cycle of the M series, a first logical operation means for calculating the logic of each bit value of the N-bit counter, and a first logical operation inserted between the shift registers Since the apparatus is provided with the first selecting means for selecting the value of the shift register and the input value based on the output of the means, a PN code (M sequence) having a required code length can be easily generated.

Further, in the PN code generation circuit according to the present invention, the M sequence is generated by the M sequence generation circuit according to any one of claims 1 to 9, so that the above effect is obtained by the PN code generation circuit. Can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an M-sequence generation circuit according to a first embodiment to which the present invention has been applied.

FIG. 2 is a timing chart showing an operation of the M-sequence generation circuit.

FIG. 3 is a block diagram illustrating a configuration of an M-sequence generation circuit according to a second embodiment to which the present invention has been applied.

FIG. 4 is a timing chart showing an operation of the M-sequence generation circuit.

FIG. 5 is a block diagram illustrating a configuration of an M-sequence generation circuit according to a third embodiment to which the present invention has been applied.

FIG. 6 is a timing chart showing the operation of the M-sequence generation circuit.

FIG. 7 is a block diagram illustrating a configuration of an M-sequence generation circuit according to a fourth embodiment to which the present invention has been applied.

FIG. 8 is a timing chart showing the operation of the M-sequence generation circuit.

FIG. 9 is a block diagram illustrating a configuration of an M-sequence generation circuit according to a fifth embodiment to which the present invention has been applied.

FIG. 10 is a block diagram illustrating a configuration of an M-sequence generation circuit according to a sixth embodiment to which the present invention has been applied.

FIG. 11 is a block diagram illustrating a configuration of an M-sequence generation circuit according to a seventh embodiment to which the present invention has been applied.

FIG. 12 is a block diagram illustrating a configuration of an M-sequence generation circuit according to an eighth embodiment to which the present invention has been applied.

FIG. 13 is a block diagram illustrating a configuration of an M-sequence generation circuit according to a ninth embodiment to which the present invention has been applied.

FIG. 14 shows an M according to a tenth embodiment to which the present invention is applied.
FIG. 3 is a block diagram illustrating a configuration of a sequence generation circuit.

FIG. 15 shows an M according to an eleventh embodiment to which the present invention is applied.
FIG. 3 is a block diagram illustrating a configuration of a sequence generation circuit.

FIG. 16 is a diagram showing an M-th embodiment according to the present invention.
FIG. 3 is a block diagram illustrating a configuration of a sequence generation circuit.

FIG. 17 shows an M according to a thirteenth embodiment to which the present invention is applied.
FIG. 3 is a block diagram illustrating a configuration of a sequence generation circuit.

FIG. 18 is a diagram showing M according to a fourteenth embodiment to which the present invention is applied.
FIG. 3 is a block diagram illustrating a configuration of a sequence generation circuit.

FIG. 19 is a diagram showing M according to a fifteenth embodiment to which the present invention is applied.
FIG. 3 is a block diagram illustrating a configuration of a sequence generation circuit.

FIG. 20 is a diagram showing M according to a sixteenth embodiment to which the present invention is applied.
FIG. 3 is a block diagram illustrating a configuration of a sequence generation circuit.

FIG. 21 is a block diagram showing a configuration of a GOLD code generation circuit to which the present invention is applied.

FIG. 22 is a block diagram showing a configuration of a conventional circuit for generating an M-sequence.

[Explanation of symbols]

10, 20, 30, 40, 50, 60, 70, 80, 9
0,100,110,120,130,140,15
0,160 M-sequence generation circuit, 11 N-bit shift register, 12 XOR circuit (exclusive OR operation means), 13 register (register R), 14 N-bit counter (COUNT), 15 OR circuit, 16 register (register) L), 17 NAND circuits, 18 selectors (MUL1) (first selector, first selector), 19 selectors (MUL2) (second selector), 21 registers (RST), 22 selectors (M
UL3) (first selecting means, first selector), 31
M-bit register (MASK) (first register), 3
2 AND circuit (second logical operation means), 51 N-1
Bit register (GEN) (second register), 52
N-1 AND circuits (third logical operation means), 53
N-1 XOR circuits (exclusive OR operation means), 91
N-1 bit (3-bit) register (DR) (third register), 92 N-1 selectors (MUL10 to MUL10)
MUL12) (second selecting means)

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Yoshihito Shimazaki 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. F-term (reference) 5J049 AA00 AA17 AA18 AA21 CA08 CB01 CB06 5K022 EE00 EE02 EE23

Claims (11)

[Claims] 1. An M-sequence generation circuit that includes a plurality of shift registers and exclusive OR operation means and generates an M-sequence, an N-bit shift register that shifts and stores each value, M pieces of exclusive OR operation means inserted between registers according to a generator polynomial; an N-bit counter for counting the number of clocks in one cycle of the M sequence; and a logic for taking the logic of each bit value of the N-bit counter 1
M; and a first selector inserted between the shift registers and selecting a value of the shift register and an input value based on an output of the first logical operator. Series generation circuit. 2. A first register having the same number of bits as the N-bit counter and having an arbitrary value set from the outside, and a first register which takes logic of each bit of the N-bit counter and the first register. 2. The logic device according to claim 1, further comprising: two logic operation means, wherein the first logic operation means takes a logic of an output value of the second logic operation means. 3.
Series generation circuit. 3. A second register having a bit number one less than the shift register and having an arbitrary value set from the outside, and a third logical operation means for taking logic of each bit of the second register 2. The M-sequence generation according to claim 1, wherein said exclusive OR operation means performs an exclusive OR operation of a value of said shift register and an output value of said third logical operation means. circuit. 4. A third register having one less bit number than the shift register and having an arbitrary value set from the outside, and a control signal inserted between the shift register and an output of the third register. And a second selecting means for selecting whether to output the value of the shift register to the next stage or to output the value of the shift register as an arbitrary bit. 2. The M-sequence generation circuit according to claim 1, wherein: 5. An M-sequence generation circuit that includes a plurality of shift registers and an exclusive-OR circuit (hereinafter, referred to as an XOR circuit) and generates an M-sequence. A shift register; M XOR circuits inserted between the shift registers according to a generator polynomial; a register R storing a value of the last stage of the shift register and having an initial value of 0; An N-bit counter for counting the number; and O for taking the logical sum of the values of the respective bits of the N-bit counter
An R circuit; a register L for holding the value of the OR circuit; and a logical AND of a logical product of an output value of the OR circuit held by the register L and a value directly output from the OR circuit.
An M-sequence generation circuit comprising: an ND circuit; a first selector controlled by the output of the OR circuit; and a second selector controlled by an output value of the OR circuit held by the register L. . 6. An N-bit shift register, comprising a plurality of shift registers and an XOR circuit, for generating an M-sequence in an M-sequence generating circuit for shifting and storing respective values and giving an arbitrary initial value. And M XOR circuits inserted between the shift registers according to a generator polynomial; an N-bit counter for counting the number of clocks in one cycle of the M sequence; and taking a logical sum of the values of each bit of the N-bit counter O
An M-sequence generation circuit comprising: an R circuit; a register RST for holding a value of the OR circuit; and a first selector controlled by an output value of the OR circuit. 7. A logical register of a first register having the same number of bits as the N-bit counter and having an arbitrary value set from the outside, and a logical AND of each bit of the N-bit counter and the first register The M circuit according to claim 5, further comprising: M AND circuits, wherein the OR circuit calculates a logical sum of output values of the AND circuit.
Series generation circuit. 8. A second register having one less bit number than the shift register and having an arbitrary value set from the outside, and an N-type having an output of the second register as one input.
A single AND circuit, and N-1 XOR circuits having the N-1 AND circuit outputs as one input, wherein the N-1 XOR circuits are configured to store the shift register value and the 7. The M-sequence generation circuit according to claim 5, wherein an exclusive OR operation is performed on output values of the N-1 AND circuits. 9. A third register having one less bit number than the shift register and having an arbitrary value set from the outside, and a control signal inserted between the shift register and an output of the third register. N-1 selectors for selecting whether to output the value of the shift register to the next stage or output as an arbitrary bit shift register, and arbitrarily select the number of bits in one cycle of the M sequence 7. The M-sequence generation circuit according to claim 5, wherein the circuit is enabled. 10. A PN code generating circuit for generating a PN code (pseudo random code) using an M sequence, wherein the M sequence is generated by the M sequence generating circuit according to claim 1. PN code generation circuit characterized by the above-mentioned. 11. The PN code according to claim 10, wherein the PN code is a GOLD code sequence obtained by using two types of M-sequence generation circuits having the same period and adding their outputs. Sign generation circuit.