JPH0441533B2 - - Google Patents

Info

Publication number
JPH0441533B2
JPH0441533B2 JP21009683A JP21009683A JPH0441533B2 JP H0441533 B2 JPH0441533 B2 JP H0441533B2 JP 21009683 A JP21009683 A JP 21009683A JP 21009683 A JP21009683 A JP 21009683A JP H0441533 B2 JPH0441533 B2 JP H0441533B2
Authority
JP
Japan
Prior art keywords
transistors
differential pair
signal
phase
constant current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP21009683A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60102018A (ja
Inventor
Hideichiro Maruta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP21009683A priority Critical patent/JPS60102018A/ja
Publication of JPS60102018A publication Critical patent/JPS60102018A/ja
Publication of JPH0441533B2 publication Critical patent/JPH0441533B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
    • H03K5/15073—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using a plurality of comparators

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
JP21009683A 1983-11-09 1983-11-09 四相信号発生回路 Granted JPS60102018A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21009683A JPS60102018A (ja) 1983-11-09 1983-11-09 四相信号発生回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21009683A JPS60102018A (ja) 1983-11-09 1983-11-09 四相信号発生回路

Publications (2)

Publication Number Publication Date
JPS60102018A JPS60102018A (ja) 1985-06-06
JPH0441533B2 true JPH0441533B2 (enrdf_load_html_response) 1992-07-08

Family

ID=16583744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21009683A Granted JPS60102018A (ja) 1983-11-09 1983-11-09 四相信号発生回路

Country Status (1)

Country Link
JP (1) JPS60102018A (enrdf_load_html_response)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63280511A (ja) * 1987-05-13 1988-11-17 Fujitsu Ltd クロック生成方式

Also Published As

Publication number Publication date
JPS60102018A (ja) 1985-06-06

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