JPH0441508B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device using an insulated gate field effect transistor (MIST), which is used as a semiconductor memory device (IC memory) to store information in a logic processing device.

With the development of integrated circuit technology, LC memory used for information processing has become larger and more dense, and its characteristics have also improved significantly. Mainly used in recent years
IC memory is an integrated circuit device using MIST.
It has a MIST and a capacitive element as a memory cell,
The switching action of MIST stores and detects the amount of charge on the capacitive element as information. As the scale increases, it becomes necessary to improve the efficiency of the capacitance of capacitive elements, and in known technology, an electrode is provided on the semiconductor surface as a capacitive element via an insulated gate film, and a power supply voltage is applied to the electrode to connect the electrode and the semiconductor surface. The capacitive effect with the surface inversion layer induced by this is used as a capacitive element. However, since improving the efficiency of the capacitive element largely controls the area occupied by the memory cell, the capacitive effect simply by using an inversion layer is insufficient for the current large-scale trend.

The purpose of this invention is to create a capacitive element with high efficiency.
An object of the present invention is to provide a highly reliable integrated circuit device having a memory cell composed of MIST.

The present invention is characterized by: a thick insulating film selectively provided on one main surface of a semiconductor substrate of one conductivity type and partially embedded in the semiconductor substrate; and an active region of the semiconductor substrate adjacent to the thick insulating film. In an integrated circuit comprising an insulated gate field effect transistor section provided in the active region and a capacitive element section as a memory cell, the transistor section includes a gate electrode coupled to an address line, and one of the gate electrodes. A first opposite conductivity type region of a deep junction provided on the base portion on the other side of the gate electrode and coupled to the digit line, and a second region of a deep junction provided on the base portion on the other side of the gate electrode and coupled to the capacitive element portion. and a region of opposite conductivity type,
The capacitive element portion has a third opposite conductivity type region extending from the second opposite conductivity type region with a junction shallower than the first and second opposite conductivity type regions of the transistor and in contact with the thick insulating film. a third opposite conductivity type region, is formed shallower than the second opposite conductivity type region of the transistor, extends from the second opposite conductivity type region, and is in contact with the thick insulating film. from a region of one conductivity type having a higher concentration than the semiconductor substrate in contact with;
A thin insulating film that constitutes a PN junction capacitor is provided on the one principal surface, extends from the transistor section, and is in contact with the thick insulating film, and a thin insulating film is provided on the thin insulating film, extends from the transistor section side, and contacts the thick insulating film. The present invention provides an integrated circuit device in which a MOS type capacitor is formed from an electrode extending over a thick insulating film and the third region of opposite conductivity type. The bottom surface of this third opposite conductivity type region is 10
It is preferable to have a PN junction and a region of one conductivity type with a high concentration of ~10 ⁴ times. Furthermore, since both the MOS capacitance and the increased PN junction capacitance are used entirely between the transistor section and the thick insulating film, a capacitive element having an ideally large capacitance can be obtained. or,
In its formation, if one conductivity type region with a higher concentration than the third opposite conductivity type region protrudes toward the transistor part side, this part becomes offset and causes a problem in operation. Such concerns disappear due to the existence of Further, the capacitive element section occupies a larger area than the transistor section. Therefore, if the third opposite conductivity type region provided in this wide area is formed as deeply as the first and second opposite conductivity type regions of the transistor section, there will be a problem of linkage with the adjacent memory cell. . However, in the present invention, since the third opposite conductivity type region having a large area is shallow, the above problem does not occur. On the other hand, although the region of the opposite conductivity type in the transistor portion is deep, it generally occupies only a small area, so the probability that a problem of linkage with an adjacent memory cell will occur can be ignored.

Next, in order to better understand the characteristics of the present invention, embodiments of the present invention will be described using figures.

FIGS. 1A to 1D are cross-sectional views showing main manufacturing steps for realizing an embodiment of the present invention. In this embodiment, a silicon nitride film (not shown) is selectively formed in the active region of one main surface of a P-type silicon single crystal substrate 101 with a specific resistance of 10 Ω-cm, and the surface concentration is 10 ¹⁶ using the nitride film as a mask. A P-type region 102 is formed in the non-active region by introducing boron of about cm ^-3 , and at the same time a silicon oxide film 103 with a thickness of about 1.3 μm is grown in this region by thermal oxidation. The growth of a thick silicon oxide film 103 on the non-active region of the substrate using a silicon nitride film as a mask is called selective oxidation method or flat MOS technology, and the details can be found in, for example, Japanese Patent Publication No. 1379/1983. , the explanation here is omitted.

Next, the silicon nitride film is removed from the active region of the sample subjected to the selective oxidation method, and thermal oxidation treatment is performed again to form a silicon oxide film 104 of about 1500 μm in thickness in the active region. This thin silicon oxide film 104 is an insulating film called an insulating gate film. A part of the active region is covered with a photoresist 105 having a thickness of about 1.5μ as shown in FIG.
Then, double ion implantation is performed using the thick silicon oxide film 103 as a mask. In the ion implantation, boron is first implanted at a dose of 5×10 ¹³ cm ⁻² at 70 KeV, followed by phosphorus at a dose of 10 ¹⁴ cm ⁻² at 30 KeV.

After ion implantation, the substrate surface has a highly concentrated P-type region 106 and an N-type region 1 contained inside the P-type region.
07 is formed. These areas 106,1
Ions 07 are selectively formed in the active region through the thin silicon oxide film 104 by ion implantation through the same opening in the photoresist. thin silicon oxide film 10
Next, the electrode 108 of the capacitive element and the MIST are placed on the top surface of 4.
A gate electrode 109 is selectively formed (FIG. 1B).

These electrodes 108 and 109 face each other with a distance of 0.4μ. Moreover, the P type region 106 and the N type region 10
The end of 7 is between electrodes 108 and 109.

Electrodes 108 and 109 are used as a mask for introducing phosphorus into the active region between the electrodes. The thermal diffusion method is suitable for introducing phosphorus, and using the electrodes 108, 109 and the thick silicon oxide film 103 as a mask, an N-type region 110 with a surface concentration of 10 ²⁰ cm ^-3 and a junction depth of 1.5 μm and a digit line are formed on the substrate surface. N-type region 1
11 [Fig. 1C]. Here the electrode 108,
An N-type region 110 between 109 and 109 is one output region of MIST and is a coupling portion that couples to N-type region 107 . Further, the N-type region 111 is another output region of MIST. After the formation of the N-type regions 110 and 111, vapor phase growth is performed on the surface of the substrate to uniformly form an interlayer insulating film 112 having a thickness of about 0.5 μm and mainly composed of phosphorus glass.

Afterwards, using known photolithographic techniques, the sample was
As shown in FIG.
A base electrode 114 that applies a base bias (SB) is conductively coupled to the back surface of 01. In this embodiment, a negative voltage is applied.

The sample completed in this way has an N-type region 107 in parallel with the capacitance between the electrode 108 and the N-type region 107.
There is a capacitance between the PN junction and the base electrode 114 due to the PN junction. The capacitance of this PN junction is the PN junction capacitance between the N-type region 107 and the heavily doped P-type region 106, so the capacitive effect is large. In this embodiment, the capacitance using the silicon oxide film 104 is approximately 0.2×10 ^-15
F/μ ² , whereas the PN junction capacitance is approximately the same capacitance, approximately 0.2×10 ⁻¹⁵ F/μ ² . Since these capacitors are formed in the vertical direction with respect to the substrate surface, an efficient capacitive element with a small area occupied by the element can be obtained.

FIG. 2 is an equivalent circuit diagram of the above-described embodiment. That is, this embodiment has a transistor Q whose gate electrode is connected to the address line W and whose output region is connected to the digit line D, and a capacitor Co using an insulating film and a PN junction capacitor loaded to one output region. and a capacitive element consisting of _C. The capacitor Co connects the surface electrode to the low potential terminal GND of the power supply, and the PN junction capacitor _C
By coupling the substrate terminal SB to a substrate bias source, both are fixed at a DC potential, and highly efficient charge storage is performed as a capacitor for information storage.

Although a 1-bit memory cell is shown in this figure, this embodiment is an integrated circuit having multiple-bit memory cells on the surface of the same substrate. Further, in the above embodiment, by applying a substrate bias, the capacitance of, for example, a digit line is reduced, thereby reducing power consumption and increasing the speed of the integrated circuit device. When a substrate bias is applied, the PN junction capacitance of the capacitive portion of the memory cell also decreases, but in the present invention, since a high concentration region of one conductivity type is provided, this decrease can be kept to a minimum. Furthermore, in the present invention, even if a substrate bias is applied, the capacitance portion of the memory cell is not substantially affected, and the effect on the digit lines, etc. is much greater, and an integrated circuit device with a higher speed as a whole can be obtained. This was done in recognition of the fact that Furthermore, in the memory cell targeted by the present invention, drain leakage current in a state where the voltage of a part of the transistor is lower than the threshold voltage due to substrate bias is also reduced.

Although one embodiment of the present invention has been described above, the present invention can also be realized using other materials or conductivity type regions not shown in the embodiment.

[Brief explanation of drawings]

1A to 1D are sectional views showing the main manufacturing steps of an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the embodiment of FIG. 1. In the figure, 10
1 is a P-type silicon single crystal substrate, 104 is a thin silicon oxide film, 108 is an electrode of a capacitive element, 106 is a high concentration P-type region, 107 is an N-type region forming a capacitor, and 110 is a capacitive element and a transistor. This is an N-type region that connects the .

Claims (1)

[Claims] 1. A semiconductor substrate comprising: a thick insulating film selectively provided on one main surface of a semiconductor substrate of one conductivity type and partially embedded in the semiconductor substrate; and an active region of the semiconductor substrate adjacent to the thick insulating film; In an integrated circuit including an insulated gate field effect transistor section provided in an active region and a capacitive element section as a memory cell, the transistor section has a gate electrode coupled to an address line;
provided on the base portion on one side of the gate electrode,
a first opposite conductivity type region of a deep junction coupled to the digit line; and a second opposite conductivity type region of a deep junction provided on the base portion on the other side of the gate electrode and coupled to the capacitive element portion. , the capacitive element portion has a junction shallower than the first and second opposite conductivity type regions of the transistor, and extends from the second opposite conductivity type region and is in contact with the thick insulating film. a conductivity type region, and the thick insulating layer is in contact with the bottom surface of the third opposite conductivity type region, is formed shallower than the second opposite conductivity type region of the transistor, and extends from the second opposite conductivity type region. A PN junction capacitor is constituted by a region of one conductivity type higher in concentration than the semiconductor substrate in contact with the film, a thin insulating film provided on the one main surface, extending from the transistor portion and in contact with the thick insulating film, and An integrated circuit device characterized in that a MOS type capacitor is constituted by an electrode provided on a thin insulating film and extending from the transistor section side to reach the thick insulating film, and the third opposite conductivity type region.