TW463371B - Manufacturing method for DRAM cells - Google Patents

Abstract

A manufacturing method for DRAM cells includes the following steps: providing a semiconductor substrate whose surface comprises a gate area, a capacitor area and a first and a second predetermined doping area on both sides of the gate area respectively in which the second predetermined doping area is located between the gate area and the capacitor area; forming a dielectric and a conductive layer in the gate area and the semiconductor substrate surface in the capacitor area respectively; conducting a first ion implantation process so as to form a lightly doped ion implantation layer on the substrate surface in the first and the second predetermined doping area respectively; forming a spacer on the sidewalls of the conductive layer and the dielectric; forming a shielding layer covering the exposed surface area of the second predetermined doping area; and, conducting a second ion implantation process to form a heavily doped ion implantation layer on the exposed surface area of the first predetermined doping area.

Description

V. Description of the invention (1) The present invention relates to a method for manufacturing a forged URAM unit. In particular, a method for manufacturing a DRAM unit using a logic process includes a traditional dynamic random access memory. (Dynamic randc) ma / eess memory (DRAM) unit is composed of a transistor and a capacitor. 'Compared to static random access memory containing 4 ~ 6 transistors! (static random access memory, SRAM) unit, the DR AM unit of size j has a higher degree of integration. However, the data stored in the DRAM unit must be periodically re-fetched, which will consume the bandwidth of the memory and increase the data processing time. Therefore, in order to increase the processing speed of the memory unit at the same time As well as the accumulation degree, the structure of traditional DRAM cells has been applied to SRAM products, becoming a one-transistor SRAM (1T-SRAM) product, which can hide the replenishment action by providing an SRAM interface, and then Speed up their data access. 〃 The conventional method is to use logic process to make DRAM cells in 1T-SRAM products, which can reduce the production cost and meet the needs of high-speed data processing. Please refer to the figure], which shows a schematic cross-sectional view of a conventional 1T_SRAM memory cell. It is known that the memory cell array 10 of the IT-SRAM is a dual-cell structure formed on an active region of a semiconductor substrate 2 and includes a first DRAM cell 3 and a second DRAM cell 5. Each DRAM cell 3, 5 contains a transistor and a capacitor. The transistor includes a gate dielectric layer 12, a gate 1 4 ′, a gate region 16, and a source region 18 shared with adjacent transistors. With semiconductor substrate 2

4 633 71 V. Description of the invention (2) An N-type silicon substrate is taken as an example. Both the drain region 16 and the source region 18 are a P + doped region. In addition, in order to solve the hot electron effect of the short channel MOS, a lightly doped drain region 20 is formed near the channel between the drain region 16 and the source region 18, which is a P-doped region. The capacitor includes a capacitor dielectric layer 22 and a capacitor plate 24. When an external voltage is applied to the capacitor plate 24, an inversion layer is formed on the surface of the semiconductor substrate 12 under the capacitor dielectric layer 22, which is used for Used as the storage node of the capacitor. The memory cell array 10 further includes an interlayer dielectric layer 26 covering the first and second DRAM cells 3 and 5. A contact plug 28 penetrates the interlayer dielectric layer 26 and is formed at a source shared by the two transistors. On the region 18 ′ and the bit line 29 are electrically connected to the source region 18 through the contact plug 28. However, the P + doped region located near the storage node will generate a large junction leakage current with the N-type silicon substrate, which will shorten the data retention time in the memory cell. It seriously affects the operation of the memory agent. In view of this, the present invention proposes a manufacturing method of 疋 applied to 1T SRAM products, which can effectively reduce the joint leakage near the storage node ^ to improve the data retention time of the memory unit. The present invention proposes a method for manufacturing a dynamic random access memory cell in a side-by-side sequence: providing a semiconductor substrate having a first conductivity type. The semiconductor substrate includes a gate region, a capacitor region, and a first and a semiconductor chip. The regions are on both sides of the gate region, and the second pre-amplifier is located between _ Lanzhao ^ φ ^ h π a idle 棰 & and the capacitor region; respectively, in the gate

Page 5 4 633 71 V. Description of the invention (3) The semiconductor of the electrode region and the capacitor region is different from the gate region and a conductive layer of the capacitor region; proceed—the first ion on the substrate surface of the second predetermined doped region A implantation layer; forming a sidewall on the first one; forming a surface area exposed by the shielding area; and a second ion implantation layer on the surface exposed by the first predetermined doped area. The depth of the layer larger than the first ion implantation process is larger than that of the first ion. According to the manufacturing method of the present invention, the memory unit includes a half gate region, a capacitor region, and a first gate region. On both sides, between the region and the capacitor region; a gate electrode is disposed in the capacitor region; a lightly doped ion-doped region and an ion implantation layer near the gate electrode are formed outside the first layer Area. Brief Description of Drawings Figure 1 shows the conventional 1T-figure. A dielectric layer is formed on the substrate surface; a first and a first implantation process are formed on the dielectric layer to form a first and a second conductive layer and a dielectric having a second conductivity type on the first and the second, respectively. The sidewall shielding layer of the electrical layer covers the second predetermined doping line and a second ion implantation process, and a doping concentration of the second ion implantation process having a second conductivity type is formed in the region. The depth of the second ion implanted implant layer. The invention proposes a dynamic random access conductor substrate, which includes a first and a second predetermined doped region on the surface. The second predetermined doped region is located on the gate electrode and is disposed on the gate electrode region. A capacitor plate is provided. A system implanting layer is formed in the second predetermined-pre-doped region; and a cross-sectional schematic diagram of a key element of a lightly doped doped ion implanted SRAM that is heavily doped with a predetermined dopant d, showing the present invention. Of the 1T-SRAM products

4 6 33 71 V. Description of the invention (4) Schematic diagram. Figures 3A to 3E are not intended to show the cross section of the method of manufacturing the memory cell shown in Figure 2. [Symbols] DRAM memory unit ~ 30; semiconductor substrate ~ 4; first DRAM unit ~ 7; second DRAM unit ~ 9; gate dielectric layer ~ 3 2; gate ~ 3 4; side wall ~ 3 5: Drain region ~ 36; Source region ~ 38; Lightly doped drain region ~ 40; Capacitance dielectric layer ~ 42; Capacitor plate ~ 44; Interlayer dielectric layer ~ 4 6; Contact plug ~ 48; Bit Line ~ 49; first predetermined doped region ~ I; second predetermined doped region ~ Π; gate region ~ G; capacitor region ~ C; N-type silicon substrate ~ 50; dielectric layer ~ 52; conductive layer ~ 54; P-ion implant layer ~ 56; side wall ~ 5 5; shielding layer ~ 5 8; P + ion implant layer ~ 60; metal oxide layer ~ 62. For an embodiment, please refer to FIG. 2, which shows a schematic cross-sectional view of a DRAM memory unit 30 of a 1T-SRAM product of the present invention. The memory cell array 30 of the present invention applicable to 1T-SRAM products is a dual-cell structure formed on an active area of a semiconductor substrate 4 and includes a first DRAM cell 7 and a second DRAM cell 9. Each DRAM cell 7, 9 contains a transistor and a transistor

0503-569011.pld Page 7 4633 71 Description of the invention (5) Transistors include-open-pole dielectric ㈣ _ ask pole%, one pole; 62 and one source region shared with adjacent transistors 38 . Taking a semiconductor substrate: a type silicon substrate as an example, 'the common source region 38 is a _p + doped region, and the drain terminal is a -P- doped region. In addition, in order to solve the thermal electron effect of a short channel, a gate is used. Below the side wall 35 of the pole 34, that is, a lightly doped drain is made in the common source region 38 1 near the gate 34, which is a P-doped region. The capacitor includes a capacitor dielectric. Layer 42 and a capacitor plate 44. After the capacitor plate 44 is connected to a voltage, an inversion layer is formed on the surface of the semiconductive soil ^ 4 below the capacitor dielectric layer 42 and is used as a storage node for the capacitor. The array 30 further includes an interlayer dielectric layer 46, which covers the first and second DRAM cells 7, g. A contact plug 48 penetrates the interlayer dielectric layer 26 and is formed as a source shared by the two transistors. The region 18 and a bit line 49 are electrically connected to the source region 38 through the contact plug 48. The present invention improves the structure of the conventional drain region, and only the drain region 36 is made into P Doped region, in this way, can effectively reduce the junction leakage caused by the conventional P + doped region near the storage node and the N-type silicon substrate Stream, thereby effectively improving the retention time of data in the memory cell ten, will help to remember the operation. &Quot; w Please refer to Figs. 3A to 3E ', which is a schematic cross-sectional view showing a method of manufacturing the DRAM unit of the present invention. The manufacturing method of the unit is performed on the active area of the N-type sand substrate 50. As shown in FIG. 3A, the active area sequentially includes a first predetermined doped area I, a gate area G, and a A second predetermined doped region Π and a capacitor region C, wherein the second predetermined doped region

4633 71 V. Description of the invention (6) I I is located between the gate region G and the capacitor region c. First, as shown in FIG. 3A, a dielectric layer 52 and a conductive layer 54 are formed on the surface of the N-type silicon substrate 50, and then the pattern of the transistor and the capacitor is defined by the lithography and etching process to remove the gate electrode. The dielectric layer 52 and the conductive layer 54 outside the region G and the capacitor region ^. The dielectric layer 52 in the gate region G is used as the gate dielectric layer, and the first conductive layer 54 in the gate region G is used as the gate; the dielectric layer 52 in the capacitor region C is used as the gate. The second conductive layer 542 serving as a capacitor dielectric layer and located in the capacitor region C is used as a capacitor plate. As shown in FIG. 3B, the engraving process is carried out. The ion implantation process, which is a slight impurity, is a main impurity, and can be used in the first predetermined doping region I. The second predetermined doped region 50 is formed on the surface of the silicon substrate 50. The P-ion implant layer 56 ° is then formed as shown in FIG. 3C before the first conductive layer is formed. 541, a second conductive layer 542 is formed on the sidewall thereof. The side wall 55 is then filled with a shielding layer 58 in the gap between the second and second conductive layers 541 and 542 to cover the exposed surface of the P-ion implant layer 56 in the second predetermined doped region II. As shown in FIG. 3D, the second ion implantation process is performed by using the side wall 55 and the mask curtain. The second ion implantation process is a heavily doped m implantation process. Area I and the surface of the silicon substrate 50 that is not covered by the side wall 55-P + ion implantation at the same time, when the first and second conductive layers 541 and 542 are polycrystalline: the material phytoplasm layer is 6 ° and the second ion implantation process is also The first and second conductive layers 541 and 542 can be formed into a P + doped polycrystalline silicon layer 'to reduce its resistance value' and used to adjust the thickness of the metal silicide to be produced later and the problem of joint leakage current.

A633 71 V. Description of the invention (7) In addition, in order to reduce the sheet resistance of the source / sink and electrode and to maintain the integrity of the shallow junction between the metal and the transistor, a self-aligned metal can be used The silicide process reacts with the polycrystalline silicon of the gate on the silicon surface of the source / drain to form a metal silicide. As shown in FIG. 3E, before the shielding layer 58 is removed, a metal silicide layer 62 may be formed on the surfaces of the P + ion implantation layer 60, the first conductive layer 541, and the second conductive layer 542. Since the shielding layer 58 covers the P-ion implanted layer 56, the metal silicide layer 62 is not formed on the P-ion implanted layer 5 6 ', which can further prevent the problem of joint leakage current near the storage node. Compared with the conventional technology, the present invention makes a dram unit in accordance with a logical process. The second predetermined doped region can be made into a p-ion implant layer by the masking of the masking layer, so as to effectively improve the bonding generated near the storage node. Leakage current issues, which significantly improve data retention. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. "

0503-569QTf-ptd

Claims (1)

4633 71 VI. Scope of patent application 1. A dynamic random memory courage DpAMx „_ 5 dynamic random aCeess memory (DKAM) early generation system (a) Provide one with the following steps: Contains-gate Regions, 1 ~ i of the semiconductor substrate, the regions on the surface are respectively in the inter electrode region: η: two :, the second predetermined doping is located in the inter electrode region and the capacitance =;:; "the second predetermined doping" The heterogeneous system (b) forms a dielectric layer on the semiconductor substrate of the gate region and the capacitor region, respectively; and makes the surface of the Qianling body substrate (C) on the gate region | ν β 4 ^ —The first and second conductive layers are formed on the dielectric layer in the (...) region (d) A $ ion implantation process is performed to form on the substrate surfaces of the first and second predetermined doped regions, respectively-with a second conductivity The first ion implantation layer of the type; the four main guards (e) form a side wall on the first and the third place respectively; the shape (f) on the side wall of the first conductive layer and the dielectric layer forms a A masking layer to cover the exposed surface area of the second predetermined doped region, and (g) performing a second ion implantation Forming a second ion implantation layer with a second conductivity type on the exposed surface area of the first predetermined doped region; wherein the doping concentration of the second ion implantation process is greater than the first ion implantation process Doping concentration 'and the depth of the second ion implanted layer is greater than the depth of the first ion implanted layer. "2. The manufacturing method described in item 1 of the scope of patent application, in which step 463371 Step (f) of the patent scope is to perform the second ion implantation process on the first and second conductive layers at the same time. 3. The manufacturing method described in item 1 of the patent scope, wherein the manufacturing method further includes steps ( g), is formed on the surface of the second ion implanted layer, the first conductive layer and the second conductive layer ~ metal; ε evening layer. 4. The manufacturing method as described in item 1 of the scope of patent application, wherein The first conductivity type is N type. 5. The manufacturing method as described in item 4 of the patent application scope, wherein the second conductivity type is P type. 6 · The manufacturing method as described in item 1 of the patent application scope , Wherein the first conductive type is? Type. 7. The manufacturing method described in item 6 of the scope of patent application, wherein the second conductivity type is N type. 8. A dynamic random access memory (DRAM) unit, which includes: a semiconductor substrate 'Its surface includes a gate region, a capacitor region, and a first and a second predetermined doped region are on both sides of the gate region', wherein the second predetermined doped region is located in the gate region And the capacitor region; a gate electrode is disposed in the gate electrode region; a capacitor plate is disposed in the capacitor region; a doped ion implantation layer is formed in the second predetermined doped region and near the gate electrode; A first predetermined doped region; and a heavily doped sub-planted layer is lighter than the Y-I fixed doped region 463371 VI 'Application Profiles®' Outside the doped ion implant layer. ^ 9 The dynamic random access memory unit described in item 8 of the scope of the patent application further includes a dielectric layer, which is disposed at the bottom of the gate and the bottom of the capacitor plate, respectively. 10. The dynamic random access memory unit described in item 9 of the scope of the patent application, further comprising a sidewall subsystem formed on the sidewalls of the gate electrode, the capacitor plate, and the dielectric layer, respectively. 1 1. The dynamic random access memory cell 'as described in item 10 of the patent scope of Shensing Patent, wherein the heavily doped ion implantation layer is formed in a first predetermined doped region which is not covered by the sidewall spacer. 12. The dynamic random access memory unit according to item 9 of the scope of the patent application, wherein a metal silicide layer is formed on the heavily doped ion implantation layer, the gate and the surface of the capacitor plate. 1 3. The dynamic random access memory cell according to item 9 of the scope of the patent application, wherein the gate is a heavily doped polycrystalline silicon layer. 14. The dynamic random access memory cell according to item 9 of the scope of the patent application, wherein the capacitor plate is a heavily doped polycrystalline silicon layer. 〇503-569〇Tfpt (i p. 13