JPH04320036A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device having MISFETs suitable for high reliability and high current driving capacity. CONSTITUTION:A source/drain has an LDD structure provided with a high- dielectric side wall spacer 6 in a vicinity of the gate electrode side wall on top of a low-doped diffusion layer 2, and with another tunneling thin film insulating film 7 between the side wall spacer and the diffusion layer 2. A gate fringe field effect to the diffusion layer 2 is improved, and hot carrier deterioration special to the LDD structure is made hard to occur; therefore, improvement in reliability of field relaxation and improvement in current driving power can be realized simultaneously.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, a semiconductor device having an insulated gate type (hereinafter abbreviated as MIS type) field effect transistor suitable for achieving high reliability and high current drive capability. and its manufacturing method.

0002

2. Description of the Related Art In order to increase the reliability of MIS type field effect transistors, it is effective to alleviate the electric field inside the device by improving the drain structure.

[0003] As a conventional MIS type field effect transistor with a highly reliable structure, for example, Japanese Patent Laid-Open No. 54-44482
lightly doped drain structures, as discussed in
So-called LDD (Lightly Doped Dra)
In) structure, or as an improved type of the above-mentioned LDD structure as discussed in JP-A-54-44482, the sidewall spacer is made of a high dielectric constant insulator (hereinafter abbreviated as high dielectric material). can give. The latter of these is shown in FIG. 1 is a silicon substrate, 2 is a source and drain diffusion layer with a high impurity concentration (hereinafter referred to as a high concentration diffusion layer), and 3 is a source and drain diffusion layer with a low impurity concentration (
4 is a gate insulating film, 5 is a gate electrode, and 6 is a sidewall spacer made of a high dielectric constant insulating film.

0004

[Problems to be Solved by the Invention] In the above prior art, the low concentration diffusion layer 3 of the former LDD structure alleviates the internal electric field of the device and improves the long-term operational reliability of the transistor, but it Acts as a resistor and causes a decrease in current drive ability. Also, even with this LDD structure, when the gate length becomes 0.5 μm or less, the conventional power supply voltage
It is becoming difficult to use it in V.

On the other hand, an LDD structure with a high dielectric spacer 6 as shown in FIG. 2 can be expected to have higher reliability and higher current drive capability than the above-mentioned LDD structure. In general, if there is an insulator with a sufficiently larger dielectric constant than the gate insulating film between the low concentration diffusion layer and the sidewall of the gate electrode in the LDD structure, this low concentration diffusion layer will be affected by the fringe electric field of the gate electrode, which is similar to that of a normal transistor. Like the channel part, it is subject to a large electric field effect. Therefore, if the dielectric constant of the spacer material is sufficiently large, it is expected that a transistor with higher reliability than the conventional LDD structure can be obtained. However, in the case of the LDD structure, the actual reliability does not show improvement in accordance with its electric field relaxation ability. This is because a hot carrier effect unique to the LDD structure occurs.

[0006] This is an ordinary n-type film formed on a silicon substrate.
The case of a channel LDD structure MOS transistor will be explained using FIG. 3(a) as an example. Note that this figure is an enlarged view of only the vicinity of the drain. This is because the hot carriers injected into the spacer 8 are captured in the spacer 8 on the drain side or at the interface with the low concentration diffusion layer, increasing the resistance of the low concentration diffusion layer. It is a dependent phenomenon. This generally limits the ability to increase the reliability of the LDD structure. 10 in the figure indicates electrons captured in the spacer. Similarly, when a high dielectric spacer is used, the fringe electric field is large, so the above effect becomes even stronger. For example, when a silicon nitride film is used as a spacer, the fringe electric field is somewhat larger because the silicon nitride film has a dielectric constant about twice as large as that of a silicon oxide film, but there are many traps in the film and at the interface. For this reason, there is a problem in that electron capture due to hot carrier injection occurs significantly, resulting in significant characteristic fluctuations and canceling out the electric field relaxation effect. Furthermore, in the case of a silicon nitride film, if the silicon oxide film below the spacer is made thinner, carriers are more easily injected into the film, so it is necessary to make the film thicker to some extent, which also poses the problem of weakening the electric field effect due to fringes.

[0007] Furthermore, when forming a high dielectric spacer,
There is also the problem that if there are defects such as weak spots or cracks in the corners of the spacer where the maximum electric field is applied, the dielectric strength between the gate electrode and the low concentration diffusion layer decreases.

In other words, in the above-mentioned conventional technology, no consideration was given to the material, shape, formation method, etc. of the high dielectric spacer, which greatly affect the reliability.

An object of the present invention is to provide an MIS type field effect transistor that can be formed by an easy process and has high reliability and high current drive ability without being subject to the above limitations, as a basic device for 0.5 μm process or later. It is in.

0010

[Means for Solving the Problems] The above object is to provide a source and a drain having the above-mentioned LDD structure, and providing a side wall spacer of a high dielectric material such as a tantalum oxide film near the side wall of the gate electrode above the low concentration diffusion layer, and This is achieved by providing a tunneling thin film insulating film having good interface characteristics between the spacer and the low concentration diffusion layer.

Another object of the above is to coat a thin film made of a high dielectric material for a spacer after forming a gate electrode in the process of forming a sidewall spacer of an LDD structure, and then to increase its high dielectric strength by heat treatment in a dry oxidizing atmosphere. By including the steps of forming a thermally oxidized thin film between the dielectric film and the low concentration diffusion layer, then coating the high dielectric material again to a desired thickness and forming sidewall spacers on the side walls of the gate electrode by anisotropic dry etching. achieved.

0012

[Operation] In the above means, by providing a sidewall spacer made of a high dielectric material on the sidewall of the gate electrode,
A large fringe electric field can be applied to the low concentration diffusion layer, and the internal electric field of the device can be relaxed. This greatly reduces the amount of hot carriers generated.

This will be explained in more detail using FIG. This figure is a computer simulation of the dependence of the maximum value of the electric field in the channel direction on the dielectric constant of the spacer material in the LDD structure. The dielectric constant is expressed as a ratio to the dielectric constant of the gate insulating film material (silicon oxide film in this case), and if this value is 1, the spacer and the gate insulating film are made of the same material and usually L
It becomes a DD structure. As a result, it was found that as the dielectric constant of the spacer material increases, the internal electric field sharply decreases when the ratio is 3 or more. In other words, it is desirable that the dielectric constant of the high dielectric film is three times or more that of the gate insulating film material, and if it is less than twice that of the gate insulating film material (for example, a silicon nitride film), the effect is small.

Furthermore, by providing a thin insulating film with good interface characteristics between the high dielectric sidewall spacer and the low concentration diffusion layer, it is possible to avoid the hot carrier deterioration phenomenon inherent in LDDs, and to improve the characteristics of the LDD structure. Reliability can be improved according to the original electric field relaxation effect. This will be explained with reference to FIG. 3(b). Even when hot carriers are injected into the spacer 6, the carriers easily tunnel through the thin insulating film 7, so that they are not captured in the thin insulating film or at the interface with other films. The injected carriers are then attracted by the fringe electric field from the gate electrode 5 and are injected into the electrode. Therefore, deterioration phenomena specific to LDDs hardly occur. For example, if the thin insulating film 7 is a silicon oxide film, it is desirable that the thickness is 4 nm or less. However, since the film interface and film quality are important, if it is a silicon oxide film, a film formed by thermal oxidation is preferable.

At this time, the film quality of the material of the high dielectric spacer 6 itself is also important. If there are many traps in the film, the above effect will be canceled out. Therefore, the high dielectric material for the spacer must be a high quality material with few traps in the film. This material is preferably selected from the group consisting of tantalum oxide, titanium oxide, hafnium oxide, neobium oxide, and zirconium oxide.

Therefore, the dielectric constant of the high dielectric spacer material is three times or more that of the gate insulating film material, and the existence of a good quality tunneling thin film insulating film between the high dielectric spacer and the low concentration diffusion layer reduces the electric field. It is possible to obtain operational reliability commensurate with the effect.

Furthermore, in the above method, by forming the sidewall spacer using the above method, the dielectric breakdown voltage between the gate and the source/drain can be improved. This will be explained using FIG. 3(c). When a thin high dielectric constant film 13 is coated in advance and then a thermally oxidized thin film 7 is formed between the high dielectric constant film and the low concentration diffusion layer by heat treatment in a dry oxidizing atmosphere, a thin film 7 is formed in the high dielectric constant film. If there are thin areas, so-called weak spots,
On the contrary, the thermal oxide film in that part becomes thicker than in other parts. This improves reliability such as withstand voltage. In addition, since a thermal oxide film is later formed between the low concentration layer and the high dielectric constant film,
A spacer with excellent interfacial properties can be formed. The atmosphere in which the above heat treatment is performed has a water vapor content of approximately 1000p.
It is desirable that it is below pm. If the amount of water vapor in the atmosphere is large, a thick oxide film will be formed in areas other than the defective areas, but if the amount is 1000 ppm or less, favorable results can be obtained.

[0018]

[Embodiments] [Embodiment 1] A first embodiment of the present invention will be described below with reference to FIG. Figure 1 shows the present invention in n-channel M
The results are shown when applied to an OS type field effect transistor. A tantalum oxide film (Ta2O5) was used as the high dielectric sidewall spacer 6, and a silicon dioxide film formed by thermal oxidation was used as the thin insulating film 7 below the spacer. At this time, the spacer width is approximately 0.1
The thickness of the silicon dioxide film was approximately 3 nm. Further, the gate insulating film 4 is a silicon dioxide film with a thickness of about 15 nm.
The surface impurity concentration of the n-type low concentration diffusion layer 2 is approximately 1×101
It was 8/cm3. Since the dielectric constant of the tantalum oxide film is about seven times as large as that of the silicon dioxide film, the electric field relaxation effect is sufficiently large as shown in FIG.

As a result, compared to a normal LDD structure MOS field effect transistor in which the sidewall spacers are also made of silicon dioxide, the hot carrier withstand voltage (transfer conductance Gm, which is an indicator of reliability) is lower than 10% in 10 years.
% fluctuating drain voltage) could be improved by about 2 V by increasing the gate fringe electric field and reducing the hot carrier deterioration phenomenon inherent to LDDs. Furthermore, in this example, since the highly doped diffusion layer 3 extends to the bottom of the sidewall spacer, the current driving ability was also improved by about 15% compared to the normal LDD structure.

[0020] Although the above embodiments are for n-channels, the same electric field relaxation effect can be obtained also for p-channels by reversing the conductivity types. Further, the high dielectric constant material is not limited to tantalum oxide film. Further, the gate electrode material may be a metal, a multilayer film of metal and silicon, or the like, and the gate oxide film material may be another high dielectric film. In particular, as silicon oxide film thickness approaches its thinning limit in the future, it is conceivable that other high dielectric materials (silicon nitride film, tantalum oxide film, etc.) will be used, and in that case, the spacer material will also be a high dielectric material. Better characteristics can be obtained by changing to moreover,
The high concentration diffusion layer 3 does not need to reach the bottom of the high dielectric sidewall spacer. In this case, although the improvement in current drive capability is small, the improvement in reliability such as electric field relaxation effect is the same. This applies when the second spacer or the like is formed after forming the spacer and while forming the high concentration diffusion layer 3. In other words, the high dielectric constant film only needs to be located in a portion above the low concentration layer, particularly in the vicinity of the gate electrode. Also, high dielectric films are not limited to sidewall spacers.
If it is located at the above position, it may be a part of the interlayer insulating film. In particular, the latter is suitable for high dielectric materials with poor coating properties, so-called coverage.

[Embodiment 2] Next, a second embodiment of the present invention will be explained using FIGS. 5 and 6. FIG. 5 is a diagram schematically showing a manufacturing process for forming an n-channel MOS field effect transistor as a typical structure of the present invention. A case will be described in which a tantalum oxide film is used as the high dielectric constant film.

FIG. 5(a) shows that after an element isolation region is formed on a p-type 10 Ω-cm silicon substrate 1, a gate insulating film 4 made of silicon dioxide, a gate electrode 5 made of polycrystalline silicon, and phosphorus ions are implanted. and subsequent heat treatment
A cross-sectional view after forming the low concentration diffusion layer 2 of the mold is shown. Here, the gate insulating film 4 has a thickness of 8 to 15 nm,
The dose of phosphorus is 1 to 2 x 1013/cm2. Further, the silicon dioxide film on the low concentration diffusion layer 2 is removed after processing the polycrystalline silicon film for the gate electrode.

Next, as shown in FIG. 5(b), a first tantalum oxide thin film 13 of 5 to 10 nm is coated as a high dielectric film. Subsequently, by heat treatment in an oxidizing atmosphere as shown in (c), a thin film 15 of silicon dioxide with a thickness of 3 to 4 nm is formed at the interface between the tantalum oxide film and the silicon substrate. At this time, if there is a thin part in the tantalum oxide film, the silicon dioxide film grows thicker there than in other parts. Therefore, even if this portion is formed at the end of the gate electrode, the withstand voltage will not decrease.

Further, as shown in FIG. 5(d), a second tantalum oxide film 14 is formed to a thickness of 100 to 150 nm. At this time,
Adjustment is made so that the total thickness of the first and second tantalum oxide films becomes the desired length of the sidewall spacer. Subsequently, the tantalum oxide films 13 and 14 are processed by anisotropic dry etching to the thickness of the film. As a result, a sidewall spacer mainly made of tantalum oxide film can be formed on the sidewall of the gate electrode 5 as shown in (e). At this time, the width of the sidewall spacer was 100 to 150 nm. Finally, as shown in (f), a thin film 16 of silicon dioxide of about 10 nm is coated as a protective film during ion implantation, and 2 to 5
x1015/cm2 doping to form a high concentration diffusion layer 3.

As described above, an LDD structure having high dielectric sidewall spacers can be formed in a self-aligned manner without changing the conventional LDD structure formation process. As a result, it was possible to form a highly reliable structure in which the hot carrier phenomenon inherent in LDDs is less likely to occur, without lowering the dielectric breakdown voltage between the gate and drain. Further, in this example as well, the high concentration diffusion layer 3 reaches the lower part of the high dielectric sidewall spacer, so that the current driving ability is greatly improved. Further, in this embodiment, a tunneling thin film insulating film exists not only under the sidewall spacer but also between the spacer and the gate electrode. In order for hot carriers injected into the spacer to quickly flow to the gate electrode, it is better that there is no insulating film on the gate electrode side. Even if formed, it is desirable that the thickness is sufficient to allow the carrier to tunnel, as in this embodiment.

Furthermore, in this embodiment, the silicon dioxide film on the low concentration diffusion layer 2 is also removed after the gate electrode is processed, as shown in FIG. 5(a). At this time, there is a concern that damage to the silicon substrate may occur depending on the removal method. In this case, after processing the gate electrode, the silicon dioxide film 17 on the low concentration diffusion layer 2 is not completely removed, and as shown in FIG.
It is good to leave some amount. Furthermore, the film thickness may be controlled to 2 to 3 nm by wet etching using sufficiently diluted hydrofluoric acid or the like. After that, as shown in FIGS. 6(b) and 6(c), a first tantalum oxide film 13 is coated, and then heat treatment is performed in an oxidizing atmosphere to form a silicon dioxide film between the tantalum oxide film and the silicon dioxide film. 15 is newly formed to a thickness of 1 to 2 nm. Afterwards, as in FIG. 5, the second tantalum oxide film 14 is coated to a desired thickness to form sidewall spacers.
Use LDD structure.

As a result, it is possible to form a sidewall spacer with better characteristics at the interface between the silicon substrate and the silicon dioxide film than in the embodiment shown in FIG. However, in this case, it is necessary to prevent the silicon dioxide film 15 below the spacer from becoming too thick. In order for the injected hot carriers to tunnel sufficiently, the thickness is preferably 4 nm or less.

[Embodiment 3] Next, a third embodiment of the present invention will be described using FIGS. 7, 8, and 9. First, the embodiment shown in FIG. 7 is a modification of the first embodiment in which the source, drain, etc. are arranged three-dimensionally to reduce the area occupied by the transistor and improve performance. .

First, FIG. 7(a) shows a structure in which the source and drain of FIG. 5(f) are laminated by selective epitaxial growth of single crystal silicon or selective growth of polycrystalline silicon. In this embodiment, the high concentration diffusion layer 31 is formed only in the laminated portion to increase the length of the low concentration diffusion layer three-dimensionally, so that reliability can be further improved without increasing the area occupied by the transistor. was completed. In particular, since the sidewall spacers 6 are made of a high dielectric material, a sufficient fringe electric field is also applied to the low concentration diffusion layer 30 in the laminated portion. Therefore, the decrease in current drive capability was slight.

Further, FIG. 7(b) shows a configuration in which the shape of the sidewall spacer is further changed from that in FIG. 7(a). In FIG. 7A, since the length of the low concentration diffusion layer can be ensured in the laminated portion, the width of the spacer can be reduced. However, when the distance between the low concentration diffusion layer 30 and the gate electrode 5 in the laminated portion shown in (a) becomes small, the electric field concentration at the end of the high concentration diffusion layer 31 becomes visible, so there is a limit to the improvement in reliability. For this reason, the shape of the spacer was formed obliquely as shown in (b). As a result, the electric field effect gradually reaches the end of the high concentration diffusion layer 31, so that reliability can be greatly improved compared to (a). In other words, the design should be such that the influence of the fringe electric field gradually decreases as it approaches the high concentration diffusion layer.

Furthermore, in FIG. 7(c), contrary to FIG. 7(a), the gate electrode 36 is buried in the silicon substrate, thereby making the source and drain three-dimensional. This example is (
Similarly to a), the area occupied by the transistor can be reduced while maintaining the length of the low concentration diffusion layer 2, etc.

FIG. 7(d) shows another embodiment in which the source and drain are stacked. In this embodiment, the method for forming the element isolation region is further changed from that shown in FIG. 7A, and a window in the silicon substrate is processed in the thick silicon oxide film 37. In the MOS process in which conventional MOS field effect transistors are used, a local oxidation method (LOCOS) is used as a method for forming element isolation regions.
oxidation of Silicon) is used. However, in the local oxidation method, the isolation region width cannot be reduced much due to the presence of bird's beaks. On the other hand, if source/drain stacking is applied as in this embodiment, planarization can be achieved by this, so it is sufficient to simply open a window in a thick insulating film as in this embodiment. This allows the width of the element isolation region to be reduced.

The diagram shown in FIG. 8 also shows that the present invention is
M of OI (Silicon Insulator)
This is an example applied to an OS type field effect transistor. In this embodiment, the silicon substrate 39 has a thickness of 100 nm or less, and 38 in the figure is a thick silicon oxide film. This silicon substrate was crystallized into short lengths by a known method. As a result, in addition to the same improvements in reliability and current drive capability as in the first embodiment, a new thinning effect was produced. This is due to the fact that there is no neutral region in the silicon substrate of the transistor and the transistor is completely depleted, resulting in mitigation of short channel effects and improvement of subthreshold characteristics. (a) is a typical example, and (b) is further shown in FIG. 6(a).
Similarly to the above, the source and drain are layered. In particular, the latter (b) is very effective in reducing parasitic resistance, since when a thin film SOI element is used, the silicon thin film other than the transistor portion has a large resistance. In addition, normal S
The OI silicon substrate is single crystal, but may be polycrystalline. In particular, the latter is SRAM (Static Random
(Access Memory) This is effective because it can be easily stacked on top of a transistor on a substrate as a load transistor of a memory cell.

[Embodiment 4] Next, another embodiment of the present invention will be described using FIG. 9. First, FIG. 9(a) shows the high dielectric sidewall spacer of the present invention applied to a single drain structure. It is expected that future MOS field effect transistors will be used under low power supply voltages. At this time, depending on the set voltage, the margin for reliability increases, so there may be a case where it is not necessary to use a high reliability structure such as an LDD structure. At this time, the issues are reducing short channel effects and improving current drive capability.

FIG. 9(a) shows this realized by a p-channel MOS type field effect transistor. 6 in the figure is a sidewall spacer made of tantalum oxide film, 15
is a thin insulating film made of silicon dioxide, and 40 is a high concentration diffusion layer made of boron. This high concentration diffusion layer was formed by ion implantation after sidewall spacer formation and subsequent heat treatment. As a result, the effective channel length could be increased because the boron diffusion end was separated from the gate electrode end by the length of the spacer. Furthermore, when a large diffusion layer is formed from the end of the spacer, the impurity concentration of the heavily doped diffusion layer decreases near the end of the gate electrode, and the resistance usually increases. However, in this example, since a high dielectric material is used for the spacer to increase the fringe electric field from the gate electrode, the surface of the diffusion layer is also sufficiently accumulated, and the resistance can be greatly reduced. Although this example used p-channel, similar effects were obtained when phosphorus was used in n-channel as well. especially,
Considering the CMOS process, it is difficult to change the spacer length between the n and p channels, so it is preferable to use phosphorus and boron, which have similar diffusion coefficients, for the n and p channels rather than using arsenic for the n channels. Furthermore, in this embodiment, even if the highly doped diffusion layer is removed from the end of the gate electrode, a large electric field effect is exerted on the substrate surface, so that the decrease in current is small. This results in
Process tolerance against variations in spacer length increases.

Furthermore, the structure shown in FIG. 9(b) is as follows: (a)
In this example, the high concentration diffusion layer was formed by oblique ion implantation. As a result, the junction depth can be extended in the lateral direction rather than in the inside direction of the substrate, so that the short channel effect can be suppressed more than in the above embodiment. The current drive capability was almost the same as in (a) due to the large fringe field effect.

As described above, when there is a region with a low impurity concentration in the source/drain as in this embodiment, the magnitude of the electric field effect from the gate electrode exerted thereon can be increased. Therefore, the present invention is suitable for improving the current driving ability of a transistor.

[Example 5] Finally, the fifth example is shown in FIG.
, 11 will be used for explanation. FIG. 10 shows the present invention in a DRAM (
Dynamic Random Access Mem
FIG. 11 is an example of application to an SRAM memory cell.

FIG. 10 shows a cross-sectional view of a DRAM memory cell. In DRAM, attempts have been made to make the capacitor section three-dimensional in order to ensure information storage capacity while reducing the memory cell area. In this embodiment, one of them is a stacked capacitive memory cell (STC).
Stacked Capacitor Cell). 51 in the figure is an information storage electrode, 52 is its counter electrode,
53 is a capacitor thin film insulating film, 56 is a bit line metal wiring,
And 54 is an interlayer insulating film. When the sidewall spacer 6 made of a high dielectric material of the present invention is applied to a charge transfer transistor in a memory cell, the electric field from the gate electrode is applied not only to the low concentration diffusion layer 2 but also to the storage electrode 5 of the laminated capacitor section.
It even reaches 1. Therefore, the amount of information storage charge can be greatly increased. At this time, it is better to increase the capacitance only in the information storage section, and it is better not to increase the parasitic capacitance of the information reading bit lines 55 and 56. For this reason, it is preferable that the sidewall spacer of the transfer transistor has the structure of the present invention on the information storage section and a silicon oxide film or the like on the bit line side.

FIG. 11(a) is a plan layout diagram of a high resistance type SRAM memory cell, FIG. 11(b) is a circuit diagram of the memory cell, and FIG. 11(c) is a cross-sectional view taken along line A-B in the layout diagram of the memory cell. This is what is shown. Note that the layout diagram mainly shows the active transistor region 60 and gate electrode layer 61 of the substrate, and omits the high resistance part and wiring in the upper layer. In addition, 62 in the figure is a contact hole that directly connects the diffusion layer of the substrate and the gate electrode, and 63 is a contact hole that connects the substrate diffusion layer and the wiring layer. Further, 64 is a high resistance load made of polycrystalline silicon, and 65 and 66 are connection wiring portions thereof.

[0041] In addition to reducing the occupied area, SRAM memory cells have to be improved in soft error resistance. The latter is dealt with by forming normal capacity in the information storage nodes corresponding to N1 and N2 in (b). Therefore, the transistor of the present invention can be used as a transfer transistor QT in a memory cell.
, and the drive transistor QD, the parasitic capacitance can be increased, so a capacitor formation process is not particularly required.

Further, in order to stabilize the operation of the SRAM memory cell, the current drive capability ratio of the drive transistor QD to the transfer transistor QT is required to be 2.5 to 3 or more. This is usually ensured by changing the gate widths of both transistors. Therefore, the gate width of the drive transistor becomes particularly large. Therefore, if the sidewall spacer of the present invention is applied only to the drive transistor, and the transfer transistor is made of silicon dioxide, which is the same as the gate insulating film, the current drive capability ratio can be secured without increasing the gate width, and the occupied area can be reduced. realizable. In other words, it is better to change the material of the sidewall spacer depending on the transistor. This is particularly suitable when the transfer transistor and the drive transistor are formed in separate layers. In this case, other parameters such as the thickness of the gate insulating film can be changed, and the distance between both transistors can be further reduced, so the effect of reducing the occupied area is very large.

[0043]

Effects of the Invention According to the present invention, a MIS field effect transistor having high reliability and high current drive ability can be formed using an easy formation method even at a level of 0.5 μm or less. , a semiconductor device that operates at high speed can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a first embodiment of the invention.

FIG. 2 is a sectional view of a conventional example.

FIG. 3 is a diagram showing the problems of the prior art and the effects of the present invention.

FIG. 4 is a diagram showing the electric field relaxation effect of a high dielectric constant spacer.

FIG. 5 is a process diagram for forming a second embodiment.

FIG. 6 is another process diagram for forming the second embodiment.

FIG. 7 is an example of application to a structure in which sources/drains are formed three-dimensionally.

FIG. 8 is an example of application to a thin film SOI structure.

FIG. 9 is a sectional view of the fourth embodiment.

FIG. 10 is an example of application to a DRAM memory cell.

FIG. 11 is an example of application to an SRAM memory cell.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Low concentration diffusion layer, 3, 40... High concentration diffusion layer, 4... Gate insulating film, 5... Gate electrode, 6... Side wall spacer made of high dielectric material, 7... Tunneling thin film insulating film , 8...Side wall spacer made of silicon dioxide, 12...Weak spot, 13, 14,
34... Tantalum oxide film, 15, 16, 17... Silicon dioxide thin film.

Claims (19)

[Claims] 1. A semiconductor device having an insulated gate field effect transistor having a source region and a drain region provided on a semiconductor substrate, a channel formed between them, and a gate electrode that exerts a field effect on the channel. At least one of the source and drain of the transistor has a high concentration impurity region separated from the gate electrode, and a low concentration impurity region in contact with the high concentration impurity region and extending directly below the gate electrode, and under the gate electrode. A high dielectric constant insulator exists on the low concentration impurity region near the sidewalls of the gate electrode so that the fringe electric field effect of the gate electrode can be sufficiently exerted on the low concentration impurity region, and the high dielectric constant insulator and a second insulator of a tunneling thin film between the low concentration impurity region. 2. The semiconductor device according to claim 1, wherein the high dielectric constant insulator is a part of a sidewall spacer formed on a sidewall of the gate electrode. 3. The semiconductor device according to claim 1, wherein the dielectric constant of the high dielectric constant insulator is three times or more the dielectric constant of the gate insulating film material. 4. The high dielectric constant insulator is tantalum oxide,
4. The semiconductor device according to claim 3, wherein the material is selected from the group consisting of titanium oxide, hafnium oxide, neobium oxide, and zirconium oxide. 5. The semiconductor device according to claim 1, wherein the second insulator of the tunneling thin film is a silicon oxide film having a thickness of 4 nanometers or less. 6. The semiconductor device according to claim 1, further comprising a third insulator in the form of a tunneling thin film between the high dielectric constant insulator and the gate electrode. 7. The semiconductor device according to claim 1, wherein the thickness of the semiconductor substrate is 0.1 micrometer or less. 8. The semiconductor device according to claim 7, wherein the semiconductor substrate is made of a thin film of polycrystalline silicon. 9. The semiconductor device according to claim 1, wherein at least one of a source and a drain of the semiconductor device is laminated on a semiconductor substrate. 10. The semiconductor device according to claim 9, wherein at least the drain of the source and drain high concentration impurity regions is present only in the laminated portion and not in the semiconductor substrate. 11. A method for forming a semiconductor device having an insulated gate field effect transistor as described above, which includes the step of forming the low concentration impurity region after forming the gate electrode of the transistor; A process of coating a thin film made of an insulator, followed by a process of forming a thermally oxidized thin film by heat treatment in a dry oxidizing atmosphere, a process of coating a high dielectric constant insulating film again, and then an anisotropic process. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the steps of leaving the insulating film on the sidewalls of the gate electrode by chemical etching, and then forming the high concentration impurity region. Claim 12: The water vapor content in the oxidizing atmosphere is 1
Claim 11 characterized in that the amount is 000 ppm or less.
A method of manufacturing the semiconductor device described above. 13. The sidewall formed in the steep stepped portion is characterized in that the material is made of an insulator with a high dielectric constant, and there is another thin insulating film in a part of the periphery of the sidewall. semiconductor devices. 14. A semiconductor device having an insulated gate field effect transistor having a source region and a drain region provided on a semiconductor substrate, a channel formed between them, and a gate electrode that exerts a field effect on the channel. A sidewall spacer made of a high dielectric constant insulator near the gate electrode of the transistor, and having a sidewall spacer with another thin film insulating film partially around the insulator, and near the gate electrode of the transistor but not directly below the gate. A semiconductor device characterized by having a low concentration impurity region in part of the source and drain. 15. The semiconductor device according to claim 14, wherein at least one of the source and drain of the transistor is a high concentration impurity region diffused from a location away from the gate. 16. The method of manufacturing a semiconductor device according to claim 15, wherein the high concentration impurity region of the transistor is formed by oblique ion implantation. 17. The semiconductor device according to claim 1, wherein the transistor is a transistor in a memory cell of a dynamic random access memory. 18. The semiconductor device according to claim 1, wherein the transistor is a transistor in a memory cell of a static random access memory. 19. The semiconductor device according to claim 18, wherein the transistor is a driving transistor in a memory cell.