JPH03166735A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To form a MIS type field-effect transistor having high-current driving capacity and high reliability by employing LDD structure in at least one of a source or a drain and forming a spacer insulating film, which is composed of two kinds or more of insulators having a high dielectric constant, as a multilayer film near the sidewall of a gate electrode in the upper section of a low impurity-concentration diffusion layer. CONSTITUTION:High-concentration impurity regions 2 separate from a gate electrode 5 and low-concentration impurity regions 3 brought into contact with the high-concentration impurity regions 2 and extended just under the gate electrode 5 are provided at least one of the source and drain of a transistor. Two kinds or more of high dielectric-constant insulators 6, 7 exerting a field effect in the same extent as the lower section of the gate electrode 5 are formed onto the low-concentration impurity regions 3 in the vicinity of the sidewalls of the gate electrode in at least one parts of the low-concentration impurity regions 3 not located under the gate electrode 5. Accordingly, an electric field in an element is relaxed, and a MIS type field-effect transistor having the high- current driving capacity of high reliability can be acquired.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular an insulated gate type (hereinafter abbreviated as MIS type) suitable for achieving high reliability and high current drive capability. The present invention relates to a semiconductor device having a field effect transistor and a method for manufacturing the same.

[Conventional technology]

In order to increase the reliability of MIS type field effect transistors, it is effective to alleviate the electric field inside the device by improving the source and drain structures.

Conventionally, as a highly reliable structure of MIS type field effect transistor, a low concentration drain structure, so-called L
D D (Lightly Doped Drain)
An improved structure of the above-mentioned LDD structure as discussed in JP-A-54-44482 is one in which the side wall spacers are made of a high dielectric constant insulating film. The latter of these is shown in Figure 2. 1 is a silicon substrate, 2 is a source and drain diffusion layer with high impurity concentration,
3 is a source and drain diffusion layer with a low impurity concentration, 4 is a gate insulating film, 5 is a gate electrode, and 6 is a sidewall spacer made of a high dielectric constant insulating film.

[Problem to be solved by the invention]

In the above conventional technology, the low impurity concentration source and drain diffusion layers (low concentration diffusion M) 3 of the former LDD structure alleviate the internal electric field of the device and improve reliability, but they also act as a resistor connected in series with the transistor. , resulting in a decrease in current drive capability. Also, in this LDD structure, the gate length is 0.5
When the diameter becomes less than μm, it becomes difficult to use the conventional electric current with a voltage of 5V.

On the other hand, the LDD structure with the high dielectric spacer 6 shown in FIG. 2 can be expected to have higher reliability and higher current drive capability than the above-mentioned LDD structure. Generally, if there is an insulator with a sufficiently larger dielectric constant than the gate insulating film between the low impurity concentration diffusion layer and the sidewall of the gate electrode in the LDD structure, this low impurity concentration diffusion layer will be affected by the fringe effect of the gate electrode. Like the channel portion of a transistor, it is subject to a large field effect.

This is because the thickness of the insulating film between the gate electrode sidewall and the low impurity concentration diffusion layer can be considered to be as thin as the gate insulating film, and this also means that the gate electrode is placed above the low impurity concentration diffusion layer. It can also be considered as an overlapping structure. This will be explained using FIG. This figure is a computer simulation of the dependence of the maximum electric field in the channel direction on the spacer permittivity in a typical structure. The dielectric constant is expressed as a ratio to the silicon oxide film,
When this value is 1, the spacer is also a silicon oxide film and usually has an LDD structure. Further, the parameter in this case is the spacer length. It can be seen from this figure that the dielectric constant of the spacer material has an optimum value that provides the minimum value of the electric field for each structure. This is because if the dielectric constant is small, the electric field effect on the low concentration layer away from the gate electrode is small, and if it is too large, the electric field concentration becomes visible in the high concentration layer. For this reason, when the spacer is formed of a single material, the high dielectric constant material to be used is largely limited.

Further, when using a tantalum oxide film as one of the high dielectric materials, for example, it is difficult to form a thick film due to problems such as cracking due to the process. For this reason, even if the material has a large dielectric constant and is expected to have good properties, it is difficult to make a spacer made of a single material as shown in FIG. 2.

An object of the present invention is to provide an MIS type field effect transistor that can be formed by an easy process and has high reliability and high current drive ability without being subject to the above-mentioned limitations, as a basic device for a 0.5 μm process or later.

[Means to solve the problem]

The above object is to provide a side surface in which at least one of the source and the drain has the above-mentioned LDD structure and is made of a multilayer film of two or more layers of insulators having two or more types of dielectric constants in the vicinity of the sidewall of the gate electrode above the low impurity concentration diffusion layer. This is achieved by providing wall spacers.

[Effect]

In the above means, by making the spacer insulating film, which provides a sufficient fringe effect, a multilayer film using two or more types of materials, a spacer having an arbitrary average dielectric constant can be formed. For example, if we consider a multilayer film of tantalum oxide film (the dielectric constant is about 7 times that of silicon oxide film) and silicon nitride film (the dielectric constant is about twice that of silicon oxide film) as one material, the ratio of the two films will depend on the ratio of the two films. A spacer having an average dielectric constant of any intermediate value between 2 and 7 times that of a silicon oxide film can be formed. This makes it possible to form a dielectric constant material that provides the minimum value of the electric field shown in FIG.

Further, by forming the side all spacer with a thin multilayer film, it becomes effective when using a material that is difficult to thicken due to the process, such as a tantalum oxide film.

〔Example〕

Example 1> A first example of the present invention will be described below with reference to FIGS. 1 and 4.

In the structure shown in Figure 1, a high dielectric multilayer film is deposited after the gate electrode is formed, and a high dielectric spacer made of the multilayer film is formed in a self-aligned manner using anisotropic dry etching on the side walls of the gate electrode. The structure of the present invention was formed in the same formation process as the LDD structure. In the figure, 1 is a p-type silicon substrate, 2 is an n-type high concentration diffusion layer, 3 is an n-type low concentration diffusion layer, 4 is a silicon oxide film, and 5 is polycrystalline silicon into which phosphorus is introduced at a high concentration. The gate electrodes 6 and 7 are high dielectric thin films. In this embodiment, a tantalum oxide film 7 was used as a high dielectric constant sidewall insulating film 6, and a silicon nitride film was used. In this example, each film thickness is constant and 5
It is a layered film. Further, the spacer length is approximately 0.1 μm. The dielectric constant of tantalum oxide film is about 7 that of silicon oxide film.
It is about twice as large for silicon nitride film. Therefore, the average dielectric constant of the spacer in this example is about 4 that of the silicon oxide film.
It was double that. This provides a condition that provides approximately the minimum value of the electric field as shown in FIG.

In addition, in this example, the above-mentioned high dielectric multilayer film is used as a conventional LDD.
Since it is used as a self-aligned sidewall spacer similar to the structure, it can be easily formed without increasing the number of steps. Note that each film needs to be sufficiently thin in order for the dielectric constant of the spacer to be considered as the average value of the multi-M films.

Further, FIG. 4 shows another embodiment. This embodiment differs from the embodiment shown in FIG. 1 in that the material and film thickness of the spacer made of a multilayer film are changed. First, Figure 4(a) shows
A material with a higher dielectric constant is used for the film farther away from the gate electrode or the surface of the low concentration diffusion layer. Here, 8 is a silicon oxide film, 7 is a silicon nitride film, and 6 is a tantalum oxide film. When using a spacer whose dielectric constant is generally considered to be approximately uniform, the electric field effect becomes smaller as the low concentration diffusion layer is farther away from the gate electrode. This reduces the effect of increasing drive capability rather than increasing reliability. As in this example,
By intentionally giving a distribution to the dielectric constant in the spacer, it is possible to give the same electric field effect to the low concentration diffusion layer distant from the gate electrode as in the vicinity of the gate electrode. Similarly to FIG. 4(a), FIG. 4(b) shows another method of giving an intentional distribution to the dielectric constant within the spacer. This was achieved using only two types of films, and the films farther away from the gate electrode are thicker. Here, 8 is a silicon oxide film and 6 is a tantalum oxide film. As a result, (a)
You can get the same effect as .

As described above, in the concept of the structure of the present invention, the thickness of each film constituting the high dielectric sidewall spacer need not be constant, and the order and number of films may be arbitrary.

Optimum values may be used for the film thickness, the number of calendars, the number of materials, and their ratios depending on the impurity concentration of the low concentration diffusion layer, structural conditions such as spacer length, or the environment in which it is used. Furthermore, although the above description has been given for the case of an n-channel, it can also be applied to a p-channel by reversing the conduction type of each region.

Example 2 Next, a second embodiment of the present invention will be described using FIG.

First, the structure shown in FIGS. 5(a) and 5(b) is the same as the structure shown in FIG. An insulating film 9, IQ, which is the same as that of the gate electrode, is provided on the gate electrode. When forming sidewall spacers made of the above-mentioned high dielectric constant insulating film, depending on the material of the insulating film, there may not be a selectivity when processing it with the underlying silicon substrate, or there is a possibility of contamination if it is formed directly on the silicon substrate. This embodiment is effective when there are concerns about process-related problems. In this embodiment, when the sidewall spacer made of a high dielectric constant insulating film is formed of a tantalum oxide film or a silicon nitride film, for example, a silicon oxide film may be used as the insulating film of 9 and IO. In this case, by making the silicon oxide film as thin as possible, all of the above effects can be achieved. Note that (a) is better in terms of reliability.

This is because carriers injected into the spacer easily reach the gate electrode without remaining in the spacer film.

Furthermore, the structure shown in FIG. 5(c) is also a method for overcoming process problems. If there is no selectivity with respect to the gate electrode when forming sidewall spacers made of a high dielectric constant insulating film, the gate electrode itself will be scraped. For this purpose, another insulating film 1l may be formed in advance over the gate electrode as shown in FIG. 5(c). Note that the above-mentioned high dielectric constant film may be used as the material. In addition, (c) is especially the source,
This is effective when forming a self-aligned contact with the drain. In other words, if the sidewall spacer material 6 made of a high dielectric constant has a sufficient selectivity with respect to the silicon substrate or silicon oxide film, this self-aligned contact formation becomes very easy. Further, the structure shown in (d) is an effective embodiment in the case of a material having poor coating properties at the stepped portion of the high dielectric constant film. After coating this high dielectric constant film, an insulating film material with very good coating properties, such as spin,
On, glass (SOG) film is applied. The figure shows a case where a diffusion layer is formed in advance.

Further, although not shown here, the gate electrode material may be any material, and may be a multilayer film such as a polycide gate electrode.

Furthermore, the impurity distribution within the substrate may be arbitrary; for example, to further increase reliability, a low concentration diffusion layer may be formed deep within the substrate, or a high concentration buried layer of the same conductivity type as the substrate may be formed deep within the substrate. It may also be formed as a punch-through stop.

This makes it possible to achieve even higher reliability as well as a reduction in junction capacitance or short channel effect.

Embodiment 3> Furthermore, a third embodiment of the present invention will be described using FIG. 6.

In the embodiment shown in FIGS. 6(a) and 6(b), the method of forming the high dielectric multilayer film for the spacer was changed to realize a shape different from that of the previous embodiments. In both cases, the spacer is a 3M film made of three kinds of materials, and in both cases, the spacer is formed by depositing a silicon oxide film as the first insulating film and anisotropic etching, and then forming the spacer as the second insulating film. A third insulating film such as a silicon nitride film is deposited and anisotropically etched, and a third insulating film such as a tantalum oxide film is again deposited and anisotropically etched to form a spacer shape as shown in the figure. The difference between (a) and (b) is the amount of overetching during the anisotropic etching. (a)
The amount of overetching is increased compared to (b). In this case, the outer material has a larger dielectric constant.

As a result, especially when a spacer is used as shown in (a), the electric field effect on the low concentration diffusion layer remote from the gate electrode can be efficiently strengthened. The structure according to this embodiment can be formed into a multilayer film of three or more layers or into an arbitrary shape by repeating the deposition of a thin film and anisotropic etching of the film in the above-described forming method.

<Embodiment 4> Furthermore, a fourth embodiment of the present invention will be described using FIGS. 7 and 8.

First, in the embodiment shown in FIG. 7, the high concentration diffusion layer in the first embodiment does not reach the lower part of the high dielectric spacer.
The dependence of the internal electric field on the spacer length l in a structure in a separated state is shown. The internal electric field has a spacer length of 0.15μ.
m or more, it is almost saturated. This means that for the electric field relaxation effect, it is sufficient that the spacer length is a certain length relative to the low-concentration diffusion layer, and it is not necessary that the high-concentration diffusion layer reaches the bottom of the spacer. . According to this embodiment, although the current driving ability is somewhat reduced due to the resistance of the lightly doped diffusion layer having no spacer above, the reliability is further improved accordingly.

Further, the embodiment shown in FIG. 8 is an example of a structure in which the electric field effect on the low concentration diffusion layer is further improved.

The electric field effects in the examples shown so far were all due to the fringe electric field from the Ga1 electrode, but
In this embodiment, a drain electric field is added to this. For example, the structure shown in FIG. 8(a) is a direct version of the polycrystalline silicon film into which impurities are introduced at a high concentration above the high concentration diffusion layer on the drain side of the first embodiment. As a result, the low concentration diffusion layer receives sufficient electric field effects not only from the gate electrode but also from the drain electrode. Therefore, a larger electric field effect can be obtained than in the second embodiment, which is particularly effective when the spacer length is long. In addition, (b) shows an example in which single crystal or polycrystalline silicon is formed on the source and drain of the first embodiment using the selective epitaxial method, and one side of this silicon is used as a drain high performance diffusion layer. By this, the above effect can be obtained. In the case of (b), it is not necessary to form a particularly high concentration diffusion layer on the substrate, so that higher reliability can be achieved.

Furthermore, a low concentration diffusion layer is formed above the main surface of the substrate,
By shortening the spacer length by the length of the low concentration layer, even higher integration can be achieved.

Embodiment 5> Next, a fifth embodiment of the present invention will be described using FIG. 9.

FIG. 9 is a diagram showing the case where the structure of the present invention is used in a memory cell of a static random access memory (SRAM) and a transistor in a peripheral circuit. (a) is an SRAM memory cell, and (b) is an SRAM memory cell.
FIG. 2 is a diagram showing a RAM circuit block; In this case, of course, the peripheral circuit can operate at higher voltages and at higher speeds, but it can also increase the parasitic capacitance of the information storage nodes of the memory cells (corresponding to D and D in the figure), resulting in soft errors caused by alpha rays. rate can be reduced. In particular, the structure shown in Figure 8 has a large parasitic capacitance attached to the drain, and since the length of the low concentration diffusion layer can be effectively lengthened, the spacer length can be shortened and the cell area can be reduced. 16M
It is suitable for use in a memory cell of an SRAM having a degree of integration higher than bits.

Also. When the structure of the present invention is used in an LSI, the spacer length or average dielectric constant can be changed relatively easily for each arbitrary circuit block.

For example, in the structure shown in the drawing, by removing part of the film by photo-etching during the deposition of the spacer multilayer film, only that part has a short spacer length and the average permittivity is different. The part that has been removed is created. SAR
In a memory such as M, the voltage stress on the transistor within the cell is usually relatively light, so a short spacer length is sufficient to increase the degree of integration. In such a case, the length of the spacer in the peripheral circuit and memory cell can be easily changed. This is SRAM
It is effective not only for DRAM or logic LSI. Further, when the structure shown in FIG. 8 is used, the parasitic capacitance within the cell increases, so it is very effective in a memory LSI.

〔Effect of the invention〕

According to the present invention, it is possible to form a MIS field effect transistor with high reliability and high current drive capability even at a level of 0.5 μm or less, particularly 0.3 μm or less, using an easy formation method, so that it can be used in future ULSI as well. A semiconductor device that operates at high speed using a conventional power source can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a typical structure of the present invention, FIG. 2 is a sectional view of a typical structure of the prior art, and FIGS. 3 and 7 are diagrams showing the internal electric field of the structure of the present invention. 4 to 6, FIG. 8, and FIG. 9 are diagrams showing the structure of other embodiments of the present invention. 1... Silicon substrate, 2... High concentration diffusion layer, 3...
・Low concentration diffusion layer, 4... Gate insulating film, 5... Gate electrode, 6, l1... Tantalum oxide film, 7... Silicon nitride film, 8, 9, 10.15... Silicon Oxide film, 14... Polycrystalline silicon film, 16... Evitaxial silicon Figure 3 Fan 2 Figure 3 Mouth closed φ (2) 6 1 drop of Ecy 9 (drops) Figure

Claims (1)

[Claims] 1. A semiconductor device having an insulated gate field effect transistor having a source region and a drain region provided on a semiconductor substrate, a channel formed between them, and a gate electrode that exerts a field effect on the channel. wherein at least one of the source and drain of the transistor has a high concentration impurity region remote from the gate electrode and a low concentration impurity region in contact with the high concentration impurity region and extending directly below the gate electrode; Two or more types of high dielectric constant insulators are used to cover the low concentration impurity region near the side walls of the gate electrode so that an electric field effect similar to that under the gate electrode can be exerted on at least a part of the low concentration impurity region that is not under the electrode. A semiconductor device characterized by existing on a region. 2. The semiconductor device according to claim 1, wherein the high dielectric constant insulator is a part of a sidewall spacer insulating film formed on a side wall of the gate electrode. 3. In a semiconductor device having an insulated gate field effect transistor having a source region and a drain region provided in a semiconductor substrate, a channel formed between them, and a gate electrode that exerts a field effect on the channel, the source of the transistor is , at least one of the drains has a high concentration impurity region remote from the gate electrode, and a low concentration impurity region in contact with the high concentration impurity region and extending directly below the gate electrode, and a two-layer film is formed on the side wall of the gate electrode. A semiconductor device characterized by the presence of a sidewall spacer insulating film made of the above multilayer film. 4. The semiconductor device according to claim 3, wherein the dielectric constant of at least one of the high dielectric constant insulators is three times or more greater than the dielectric constant of the gate insulating film of the transistor. 5. The semiconductor device according to claim 3, wherein one of the high dielectric constant insulators is a tantalum oxide film. 6. In the method for forming a semiconductor device having an insulated gate field effect transistor, after forming the gate electrode of the transistor, forming the low concentration impurity region, and then applying two or more types of dielectric constants to the entire surface. A claim comprising the steps of coating a multilayer insulating film, then leaving the multilayer insulating film on the side wall of the gate electrode by anisotropic etching, and then forming the high concentration impurity region. Item 3. A method for manufacturing a semiconductor device according to item 3. 7. The above manufacturing method may include the step of forming an insulating film having the same dielectric constant as the gate insulating film on the surface of the semiconductor substrate after forming the gate electrode of the transistor and before coating the high dielectric constant insulating film. 7. The method of manufacturing a semiconductor device according to claim 6. 8. A semiconductor device, wherein at least one of the transistors constituting the static random access memory is made of the semiconductor device according to claim 3. 9. The semiconductor device according to claim 8, wherein the static random access memory has a degree of integration of 16 Mbits or more.