KR940001893B1 - Semiconductor memory device having a buried capacitor and method for fabricating thereof - Google Patents
Semiconductor memory device having a buried capacitor and method for fabricating thereof Download PDFInfo
- Publication number
- KR940001893B1 KR940001893B1 KR1019910007705A KR910007705A KR940001893B1 KR 940001893 B1 KR940001893 B1 KR 940001893B1 KR 1019910007705 A KR1019910007705 A KR 1019910007705A KR 910007705 A KR910007705 A KR 910007705A KR 940001893 B1 KR940001893 B1 KR 940001893B1
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- South Korea
- Prior art keywords
- insulating film
- capacitor
- layer
- conductive
- epitaxial layer
- Prior art date
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title description 5
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/036—Making the capacitor or connections thereto the capacitor extending under the transistor
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
제1a도-제1c도는 본 발명의 1실시예에 따른 제조공정도이다.1a to 1c is a manufacturing process diagram according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : P형기판 2 : 절연막1: P-type substrate 2: Insulation film
3 : n형 에피택셜층 4 : P형웰3: n-type epitaxial layer 4: P-type well
5 : 게이트산화막 6 : 폴리실리콘5: gate oxide film 6: polysilicon
7 : 측벽 8 : 소오스 및 드레인영역7 sidewall 8 source and drain region
9 : LTO 및 BPSG막 10a, 10b, 10c, 10d, 10e : 금속전극9: LTO and BPSG film 10a, 10b, 10c, 10d, 10e: metal electrode
본 발명은 반도체 장치에 관한 것으로, 특히 커패시터를 트렌지스터 아래에 형성시킨 배리드(Buried)절연막 커패시터를 갖는 반도체 메모리 장치 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device having a buried insulating film capacitor in which a capacitor is formed under a transistor, and a manufacturing method thereof.
통상, 하나의 트랜지스터와 하나의 커패시터로 구성되는 DRAM(Dynamic Random Access Memory)에 있어서 커패시터는 적층형, 트랜치형, 혼합형이 사용되고 있으며, 요구되는 커패시턴스는 대략 20-50fF/cell 정도이다.In general, in a DRAM (Dynamic Random Access Memory) composed of one transistor and one capacitor, a capacitor, a stacked type, a trench type, and a mixed type are used, and a required capacitance is about 20-50 fF / cell.
현재, 반도체 메모리 소자의 고집적화 추세에 따라 평면단위 면적에 탑재되는 소자의 수가 증가되고 커패시터로 이용되는 면적이 축소되어 이를 개선하기 위한 연가 활발히 진행중에 있다.Currently, according to the trend of higher integration of semiconductor memory devices, the number of devices mounted on a planar unit area is increased and the area used as a capacitor is reduced, which is actively progressing to improve this.
또한, 트랜치형 및 절충형 커패시터는 모두 공정이 복잡하고 공정난이도가 높아 콘트롤이 힘들며 토폴로지가 좋지 않아 소자의 다른 특성에 악영향을 미치게 된다.In addition, both trench-type and compromise capacitors are complex, difficult to control due to high process difficulty, and have a poor topology and adversely affect other characteristics of the device.
더욱이, 커패시터가 옆 또는 비스듬히 존재하므로 셀사이즈를 줄이는데 큰 장애 요소가 되었다.Moreover, the presence of capacitors next to or obliquely poses a major obstacle to reducing cell size.
본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 본 발명의 목적은 전하를 축적시키기 위한 배리드 절연막 커패시터를 가지고 그 위에 트랜지스터가 형성된 반도체메모리 장치를 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor memory device having a buried insulating film capacitor for accumulating charge and a transistor formed thereon.
본 발명의 다른 목적은 상술한 반도체 메모리 장치를 제조하는 방법을 제공하는 것이다.Another object of the present invention is to provide a method of manufacturing the above-described semiconductor memory device.
이하, 본 발명을 첨부도면에 의하여 상세히 설명한다.Hereinafter, the present invention will be described in detail by the accompanying drawings.
제1a도-제1c도는 본 발명의 1실시예에 따른 제조공정도로서, 우선 P형 기판(1)상에 절연막(2)을 형성시키고 SEC(Selective Epi Growth)방법으로 n형 에피택셜층(3)을 성장시킨 후 n형 에피택셜층(3)의 일정부분에 불순물의 이온주입으로 P형 웰(4)을 형성하고, P형 웰(4)을 포함하며 일측에 n형 에피택셜층(3)의 상부 표면의 일부가 노출되는 범위로 그 양측에 P형 기판(1)의 내부까지의 깊이로 트랜치를 형성한다.1A to 1C are manufacturing process diagrams according to an embodiment of the present invention. First, an insulating film 2 is formed on a P-type substrate 1, and an n-type epitaxial layer 3 is formed by a selective epi growth (SEC) method. After the growth, the P-type well 4 is formed by implanting impurities into a portion of the n-type epitaxial layer 3, and includes the P-type well 4 and the n-type epitaxial layer 3 on one side. A trench is formed to a depth to the inside of the P-type substrate 1 on both sides thereof in a range where a portion of the upper surface of the substrate is exposed.
여기서, 절연막(2)은 금속계 절연물이나 질소계 절연물을 사용한다.Here, the insulating film 2 uses a metal-based insulator or a nitrogen-based insulator.
그후, 제1b도와 같이 전면에 게이트 산화막(5)을 성정시키고 폴리실리콘(6)을 도포한 후 P형웰(4)상의 게이트 영역을 한정하여 폴리실리콘(6)을 식각하고 그 측면에 산화막으로 된 측벽(7)과 P형 웰(4)에 불순물 주입에 따른 LDD(Lightly Doped Drain)구조의 소오스 및 드레인영역(8)을 형성한다.After that, the gate oxide film 5 is formed on the entire surface as shown in FIG. Source and drain regions 8 of LDD (Lightly Doped Drain) structures are formed in sidewalls 7 and P-type wells 4 by impurity implantation.
그후, 제1c도에 도시한 바와 같이 그위에 LTO(Low Temperature Oxide)막 및 BPSG막(9)을 도포하고 소오스 및 드레인영역과 게이트, P형 웰영역, 에피택셜층등에 콘택을 낸 후 금속을 증착하고 불필요한 부분을 제거하여 소오스 전극(10a), 게이트전극(10b), 드레인전극(10c), 벌크전극(10d), 커패시터 제2전극(10e)을 형성한다.Thereafter, as shown in FIG. 1C, a low temperature oxide (LTO) film and a BPSG film 9 are coated thereon, and the source and drain regions, the gate, the P-type well region, the epitaxial layer, and the like are contacted with each other. The source electrode 10a, the gate electrode 10b, the drain electrode 10c, the bulk electrode 10d, and the capacitor second electrode 10e are formed by depositing and removing unnecessary portions.
그리하여 본 발명에 따른 배리드 절연막 커패시터를 갖는 반도체 메모리 장치를 얻을 수 있게 된다.Thus, the semiconductor memory device having the buried insulating film capacitor according to the present invention can be obtained.
본 발명의 반도체 메모리 장치는 P형 기판(1)위에 절연막(2)을 성장시킨 후 에피택셜층(3)을 성장시키는 SEG 방법에 의해 기판/절연막/에피택셜층의 구조를 갖게 한 다음 트랜지스터를 형성시키는 것으로 소오스 및 드레인영역과 게이트 및 벌크영역으로 트랜지스터가 형성되고 기판을 그라운드(GND)하면, 기판(1)과 절연막(2), 에피택셜층(3)으로 커패시터가 형성되어 배리드 절연막 커패시터에 의해 전하가 축적되고 그위에 트랜지스터가 형성된다.The semiconductor memory device of the present invention has a structure of a substrate / insulation film / epitaxial layer by a SEG method in which an insulating film 2 is grown on a P-type substrate 1 and then an epitaxial layer 3 is grown. When the transistor is formed in the source and drain regions, the gate and the bulk region, and the substrate is grounded (GND), a capacitor is formed in the substrate 1, the insulating film 2, and the epitaxial layer 3 to form a buried insulating film capacitor. By this charge is accumulated and a transistor is formed thereon.
이때, 절연막(2)의 두께는 임의로 조정할 수 있으며 P형 기판(1)도 역시 임의로 선택할 수 있다.At this time, the thickness of the insulating film 2 can be arbitrarily adjusted, and the P-type substrate 1 can also be arbitrarily selected.
이상 설명한 바와 같이, 본 발명에 따르면 셀과 셀 사이의 누설전류를 없앨 수 있으며, 절연막 위에 트랜지스터가 존재하므로 α입자에 의한 소프트 에러가 적어지게 된다.As described above, according to the present invention, the leakage current between the cell can be eliminated, and since the transistor exists on the insulating film, the soft error caused by the? Particles is reduced.
또한, 커패시터가 트랜지스터 하부에 존재하므로 커패시터를 위한 별도의 면적이 필요치 않아 셀 사이즈를 감소시킬 수 있으며, 공정이 간단하고 공정 콘트롤이 쉬우므로 제작이 용이하다.In addition, since the capacitor is located below the transistor, a separate area for the capacitor is not required, so that the cell size can be reduced, and the manufacturing process is easy because the process is simple and the process control is easy.
더욱이, 토풀로지가 개선되어 디지인이 용이하며 래치현상도 방지할 수 있는 효과가 있다.In addition, the topology is improved, so it is easy to design, and there is an effect of preventing the latch phenomenon.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910007705A KR940001893B1 (en) | 1991-05-13 | 1991-05-13 | Semiconductor memory device having a buried capacitor and method for fabricating thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910007705A KR940001893B1 (en) | 1991-05-13 | 1991-05-13 | Semiconductor memory device having a buried capacitor and method for fabricating thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920022515A KR920022515A (en) | 1992-12-19 |
| KR940001893B1 true KR940001893B1 (en) | 1994-03-10 |
Family
ID=19314367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910007705A KR940001893B1 (en) | 1991-05-13 | 1991-05-13 | Semiconductor memory device having a buried capacitor and method for fabricating thereof |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940001893B1 (en) |
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1991
- 1991-05-13 KR KR1019910007705A patent/KR940001893B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR920022515A (en) | 1992-12-19 |
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