KR910006750B1 - Trench capacitor semiconductor device and manufacturing method - Google Patents

Abstract

The trench capacitor with SDT for DRAM is manufactured by; forming a trench with polysilicon storaging a charge by reactive ion etching; forming a Pt-region by deposition the doped oxide in the inner side of the trench; forming a drain region on the upper side of the trench, followed by forming a source region isolated with fixed space; forming a titanium salicide layer to connect the charge storage electrode with the gate; forming a field oxide layer at residual part of the trench; forming a gate electrode with a first polycide layer followed by deposition the oxide layer on the electrode to insulate; forming a second polycide layer followed by forming oxide layer and protective layer.

Description

Trench capacitor cell composed of SDT cell structure and manufacturing method thereof

1 is a cross-sectional view of a trench capacitor formed on an SDT which is a unit cell of a D RAM according to the present invention.

2 is a 20,000 magnification of the layout of an SDT cell according to the present invention.

3 is a trench structure diagram for calculating the trench capacitor capacity of the SDT cell structure of FIG.

4 is a process final impurity distribution diagram of the SDT cell according to the present invention.

* Explanation of symbols for main parts of the drawings

1: SDT Cell 2: Trench

3: capacitor oxide film 4: P ⁺ doped region

5: drain area 6: source area

7 spacer SPACE 8 field oxide layer (FOX)

9: titanium salicide layer 10: LTO insulating layer

11 and 11 ': first and second polyside layers 12: dope oxide film

13: protective film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trench capacitor cell in which a capacitor region of a semiconductor highly integrated memory device is formed of a SDT cell structure. In particular, a trench capacitor comprising an SDT cell structure having an three-dimensional structure by anisotropically etching a silicon substrate. It is about.

In the conventional C RAM device, since the capacitor region is formed in a planar cell structure, it is difficult to manufacture an effective D RAM device due to the large cell size. Accordingly, in order to solve this problem, a trench capacitor or a stacked capacitor cell structure having a three-dimensional structure of a capacitor was developed and manufactured using a CCC structure, a BSE structure, or an SPT structure. Is too large and the P-WELL concentration is too high, so the BODY EFFECT has a big disadvantage among the electrical characteristics of N MOSFET.In the BSE structure, which solves this disadvantage, the doped polysilicon acts as a storage electrode. CHARGE STORAGE) Principle is that there is little leakage current between cell and cell size is small, but because it is formed by N MOSFET, power loss is very large and epitaxial layer structure should be used, and as BURRIE CONTACT There was a problem in the process. In addition, in the SPT structure, which improves the disadvantages of the BSE structure, a capacitor is formed even in an insulating region by using a T-type trench, thereby minimizing the distance between the capacitors, reducing the SER, and reducing noise. Although there was an advantage in this structure, it was not economical because there was a problem of using an expensive impurity ion implantation equipment and an epitaxial substrate.

Therefore, the present invention eliminates the above disadvantages and effectively reduces the cell size, and instead of using an epitaxial substrate, an P ⁺ region is formed in the lower portion of the trench to increase the effective capacitance value and to store the charge in the trench. The purpose is to provide a trench capacitor cell.

According to the capacitor cell of the D RAM device according to the present invention, first, since the charge storage form uses an internal charge storage method that can be stored in the polysilicon in the trench, it can be used in D RAM products of 4M BITS or more. CMOS processing is used to reduce power consumption. Third, in case of a cell structure that satisfies the above two conditions, high energy performance equipment must be used to form N-WELL without losing effective capacity. In order to solve the problem by the invention, and fourthly, in order to enable CMOS processing without loss of effective capacity and high energy performance equipment, only the trench sidewall portion that determines the effective capacity is selected as high concentration BORON. The doping process by the conventional method, and fifthly, the drain region and the trench cache of the transfer gate. In order to connect the storage electrodes of the sheeter and to improve the speed of the MOSFET device, the salicide process was used. Sixth, to maximize the effective area of the trench capacitor, a trench capacitor was formed up to the insulating region. Soft error IMMUNITY is good because it uses.

On the other hand, in the doping treatment by the above-mentioned selective method, the BORON DOPANT SOURCE used for the method of doping the trench sidewall portion which determines the effective capacitance value by the high concentration of BORON is BSG (BOROSILICA GLASS). Film or BN (BORN-NITRIDE) wafer can be used. Which of the two dope sources is better should be determined according to the degree that BORON concentration can be easily controlled and uniformly doped.

However, the most important problem when using the sidewall doping method by the selective method is that the high concentration of the trench sidewall doped BORON can be continuously diffused by heat treatment and affect the characteristics of the moving gate (especially the drain region and sidewall doping of the moving gate). REACH-THROUGH breakdown with the area) Only the desired sidewall portions should be selectively doped when doping sidewalls.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a cross-sectional view of a capacitor having an SDT cell structure formed on a D RAM according to the present invention. First, a trench 2 is formed on a P-type silicon substrate by RIE etching, and a P ⁺ substrate 4 electrode region is formed on the trench wall by selective impurity doping using a photoresist etch back technique.

Next, after the trench capacitor oxide film 3 is grown, the N-doped polysilicon is filled to form a charge storage electrode, and the surface is planarized by a planarization technique, and then a field oxide which is an insulating region by LOCOS technique. The layer 8 was formed to make a moving gate of LDD structure. At this time, the titanium salicide layer 9 was formed in this region in order to connect the drain region of the moving gate and the charge storage electrode, reduce the resistance of the gate electrode, and reduce the resistance of the source and drain regions. The LTO insulating layer 10 is deposited to form an insulating layer with the polyline layer 11 ′, which is a bit line, and a tungsten polyside layer is formed. Then, the doped oxide layer 12 is deposited, and finally, the protective layer 13. Was formed.

According to the SDT cell structure of the present invention configured as described above, the cell structure of the trench capacitor which can be used for 4M D RAM class or more memory device has the following characteristics.

1) It is possible to reduce the CAP TO CAP LEAKAGE because the charge storage type is stored in polysilicon in the trench. 2) The trench storage capacity can be increased without using the EPI / P ⁺ substrate structure. 3) CMOS process can be done without using high energy ion implantation equipment to reduce power consumption. 4) BSG thin film technology and photosensitive material (PSG) containing high concentration of impurities to selectively diffuse high concentration region of trench outer wall. / R) using etching back technology, and 5) using the Ti salicide process to connect the gate and the polysilicon electrode in the trench. N-type polysilicon may be connected to the doped polysilicon and the drain region in the interior.

2 is a layout of the SDT cell 1 according to the present invention, which is enlarged at a magnification of 20,000 times. If you look at the design rules,

ｏACTIVE: Width = 1.8㎛, Space = 1.0㎛, TO POLY2 = 0.1㎛

Poly 2: width = 1.2 μm, space = 1.0 μm

DC: Size = 1 × 1 μm ² , TO ACTIVE = 0.4 μm, TO POLYCIDE = 0.5 μm, TO POLY2 = 0.5 μm

BNC: Size = 1 × 1 μm ² , TO TRENCH = 0.3 μm, TO POLY = 0.3 μm, TO ACTIVE = 0.1 μm

Polyside: width = 1.4 × 2 μm ² , space = 1.1 μm

ｏ trench: Size = 1.4 × 2.1㎛ ² , TO ACTIVE OVERLAP = 0.8㎛, TO TRENCH = 1㎛

FIG. 3 is an enlarged view of the trench 2 of FIG. 1, which is assumed as a cuboid trench capacitor structure in order to analytically calculate its storage capacity. Referring to the specification, the storage voltage and the surface concentration of the field region of the trench 2 structure illustrated in the present invention for reference as follows.

Trench (2): Size = 1.4 × 2.1㎛ ²

CAP and OX thickness = 180 mm

Voltage of storage electrode = 5V

Voltage of board electrode = -2V

Trench (2) depth = 5㎛

Surface concentration of field area = 5 E 16cm ^-3

P ⁺ sidewall surface concentration = 2 E 19cm ^-3

N ⁺ POLY-SI concentration = 1 E 20 cm ^-3

Therefore, the storage capacity value Cs of the cell 1 of FIG. 1 is given as follows.

Where C1 is the capacity of the side-well doped region d, C2 is the capacity of the side-well doped region 4, Cj is generated in the drain region 6 of the moving gate. When the applied capacitance is applied, but C1 and C2 values are defined as the effective capacitance as follows.

The Cnp value is a depletion capacity value depleted toward n ⁺ dope polysilicon when a voltage is applied, the Cox value is a capacitance value due to the capacitor oxide thickness Dd, and the value of Cd is a depletion capacity value generated toward the bulk side.

Taken together, these expressions are given by the following equations, but Cj is ignored:

In the above formula,,, and values are obtained as follows.

Therefore, the storage capacity value Cs

이 된다.

Becomes

Therefore, the storage capacitance of the structure of the SDT cell 1 according to the present invention is about 50 pF when the junction capacitance of the drain region 6 is ignored.

Next, as a description of the process simulation of the structure of the SDT cell 1, the biggest problem of the structure of the SDT cell 1 is a method of selectively doping a high concentration of BORON on the sidewall of the trench capacitor. In order to set the process conditions, the selective etch back and point value of the BSG film 12 is determined using SUPREM3, a one-dimensional process simulator, and SUPRA, a two-dimensional process simulator. Deposition and drive-in optimum process conditions were simulated.

First, considering the junction breakdown voltage, as shown in the cross-sectional view of the structure of the SDT cell 1 of FIG. 1, the high voltage BORON of the drain region 6 and the sidewalls of the trench 2 of the moving gate are opposite to each other. Since this is applied, there is a fear that blackdown will occur at the junction of this site. The condition in which blackdown occurred in Si is a condition when the electric field E reaches an Ecrit value in the depletion region if the impurity concentration in Si is Na (assuming flat plate junction). The Ecrit value can be obtained from the following equation.

If the sidewall-doped BORON did not diffuse to the junction with the drain 6, the Na value in the equation above is P-WELL concentration 2 × 10 ¹⁶ cm ^-3 , resulting in Ecrit = 4.4 × 10 ⁵ V / cm. When the sidewall-doped BORON influenced the junction, Na = 1 E 18cm ^-3, so Ecrit = 1.2 × 10 ⁶ V / cm.

Then, the minimum depletion width to maintain the bladder voltage value of 14 V (to set above the junction bladder voltage) at 2 E 16cm ^-3 and 1 E 18cm ^-3 is 0.32㎛ and 0.12㎛, respectively. In order to maintain the bladder voltage of the junction between the drain region 6 and the sidewall doping region at 14 V or more, a distance of 2E 16 cm ^-3 concentration distribution needs to be at least 0.4 µm or more.

Next, considering the drain junction depth, since the source-to-drain regions 5 and 6 use salicide treatment in the mobile gate NMOSFET of the SDT cell 1 structure, Si and Ti react with each other in the formation of salicide. As the erosion of the Si region by the ratio (VOLUME RATIO), too small junction depth can weaken the bladder voltage value of the source-to-drain junction, so that the source-to-drain region junction by As is so small that As + Ph is used to form a GRADED JUNDTION with Xj = 0.35 μm

Xj = 0.35 mu m. … … … … … … … … … … … … … … … … (13).

On the other hand, the other problems in the sidewall diffusion, using the SUPREM3 and SUPRA simulation program to investigate the BSG film 12, the optimal concentration of the BORON, the optimum drive-in conditions and the impurity distribution of the final trench sidewall doped BORON, etc. The optimal determination of the final impurity distribution of BORON must satisfy the following two conditions. Firstly, to increase the effective capacitance value, the final BORON at the interface of the trench sidewall should be 2 E 19 cm ^-3 , and secondly, the minimum spread from the BSG etch back end point.

The above two conditions are determined by the concentration of BORON contained in the BSG film 12 deposition process and the temperature and time of the BSG film 12 drive-in treatment. The optimum conditions of the simulation result are as follows.

When the BSG membrane 12 is fixed, the BORON content is about 1 E 21 to 5 E 21 cm ^-3 , where too low results in a reduction of the effective capacity, and when too high, the final diffusion distance after the drive-in treatment becomes too large. Therefore, the junction breakdown voltage characteristic is weakened. In addition, the BSG film 12 drive-in conditions may be about 30 minutes in the temperature range of 920 degreeC-950 degreeC.

Under these conditions, the diffusion distance of the sidewalls of the final trench 2 is 0.8-1.1 μm upward, and the use of P-WELL can further reduce the diffusion distance upward.

For reference, the process optimum target on the test wafer irradiated to adjust the concentration of BORON during the BSG film 12 drive-in treatment may be 100-250 Ω and 0.2-0.3 μm of the junction depth.

As the optimum conditions of the above-mentioned process, the three-dimensional picture of the final impurity distribution of the unit CELL according to the present invention simulated using SUPRA is shown in FIG.

Therefore, in the light of the above-described matters, it is possible to determine the value of the BSG film 12 etch back end point required for selective sidewall doping of the BSG film 12 in the actual process.

End point value = Xjn + Wd + Ds

Where Xjn: drain junction depth

Wd: width of depletion to achieve a breakdown voltage of 14V or higher

Ds: Upper distance of sidewall diffusion determined by process conditions

In the best case, the end point value is 0.35 + 0.4 + (0.8 or 1.1), so it is about 1.5-1.8 μm. Thus, the value of the BSG film etch back end point is approximately 1.5-1.8 μm.

It goes without saying that the values set in this way are set based on the analytical calculations and simulator results, and are calculated to explain the gist of the present invention.

Claims (2)

In a trench capacitor cell of a D RAM semiconductor highly integrated device, a trench is formed on the silicon substrate by RIE etching to store a polysilicon storing charge therein, and a dope oxide is deposited inside the trench to form a P ⁺ region. Forming a drain region of a gate on the outer upper wall of the trench while forming a source region on a side spaced at regular intervals in this region, and connecting the charge storage electrode and the gate by the titanium salicide deposition. A titanium salicide layer is formed on the trench upper middle portion and the drain region of the gate, while a field oxide layer is formed on the remaining upper portion of the trench as an insulating layer, and the field oxide layer is spaced apart from the drain and source regions. Titanium salicide layer is formed on the upper portion of the first poly yarn An SDT cell structure formed by forming a gate electrode, which is a rare layer, and a second polyside layer formed with the first polyside layer insulated from the oxide layer, and formed of a dope oxide layer and a protective layer thereon. Trench capacitor cell consisting of. A trench capacitor cell manufacturing process of a D RAM semiconductor integrated device, comprising: forming a trench on a semiconductor substrate by RIE etching, forming a P ⁺ region in the trench by photolithography, and then forming a charge storage electrode material in the trench Filling a gap; forming a source region on a gate drain region and a side surface spaced apart from the trench upper outer wall; and a titanium sally on the trench and drain regions to connect the charge storage electrode and the gate. Forming a side layer, forming a field oxide scavenger layer on the remaining portion of the trench, and forming a first polyside layer on the spaced portion of the field oxide layer and the drain and source region, and forming an oxide insulating layer. And then forming a second polyside layer to form a dope oxide thereon to form a protective layer. A trench capacitor cell manufacturing process of an SDT cell structure, comprising the steps of:

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