JPH0439229B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for producing a material for a solid state relay that allows a plurality of different elements constituting the solid state relay to be formed on the same chip (substrate).

[Background technology]

When manufacturing a solid-state relay made up of multiple different elements, each individual element is mounted on a printed wiring board.
Conventionally, methods similar to those for hybrid ICs were used.
It has been done. However, with this method, not only the number of parts increases, but the mounting process is also complicated, and miniaturization is not possible. Therefore, it may be possible to form these elements on the same chip to reduce the size, but in that case, a very large number of elements must be formed on the same very small chip. For example, in the case of the solid-state relay mentioned above, the silicon photo diode formed on the chip can only generate an electromotive force of about 0.7V at maximum, whereas the MOS transistor formed on the same chip cannot operate. A voltage of 6V or more is required to operate this MOS transistor, and if you want to operate this MOS transistor with the photodiode, as shown in Figure 3, you will need a photodiode consisting of 12 or more photodiodes connected in series. - Must be a diode array. In this way, when devices such as the solid state relay are fabricated on the same chip, more elements are required than when forming the same circuit using independent elements. Furthermore, these elements must be formed completely separately and independently on the same chip.
For example, when forming elements that require a single crystal silicon layer and elements that do not require a single crystal silicon layer on an isolated island of a DI substrate, it is necessary to form these elements with as few steps as possible and with high precision. has been done. Therefore, recently, as a method of manufacturing devices that require a single-crystal silicon layer and devices that do not, a method has been developed to create devices on the surface of isolated islands of single-crystal silicon.
Masking with SiO ₂ removes only the SiO ₂ on the isolation island that requires a single crystal silicon layer,
A method for selective epitaxial crystal growth using a mixed gas of SiH ₂ Cl ₂ and HCl under reduced pressure has been developed. In this method, a single crystal silicon layer grows in areas where SiO ₂ masking is not formed, but polysilicon is generated in areas where SiO ₂ is formed, and this polysilicon is absorbed by the gas mixture.
The aim is to grow only a single crystal silicon layer on the substrate by etching away it with the HCl component. However, with this method, HCl slightly etches the single-crystal silicon layer, which slows down the growth rate of the single-crystal silicon layer.Also, this crystal growth must be performed under reduced pressure, which requires equipment. However, they have also become expensive, which has become a problem.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a material for a solid-state relay, which allows a plurality of different elements to be easily formed on the same chip with fewer steps. .

[Disclosure of the invention]

In order to achieve the above objectives, this invention
Epitaxial crystal growth is performed by masking the substrate surface into a predetermined shape without considering selectivity, and a single crystal silicon layer is formed on the unmasked isolated islands, while a polysilicon layer is formed on the other parts. After that, the surface of the single crystal silicon layer is masked and etched to leave the single crystal silicon layer on a predetermined isolated island on the substrate, and a part of the polysilicon layer is also masked and etched. The gist of this work is to create a material for solid-state relays that leaves this portion of the polysilicon layer on the substrate.

The present invention will be explained below based on the drawings showing one embodiment thereof.

In this invention, the substrate is of DI type (Dielectric type).
Isolation type). Because D.I.
This is because by using a substrate, it becomes possible to completely insulate each element formed on the same chip.

First, a method for manufacturing the material for a solid state relay of the present invention will be explained based on FIGS. 1a to 1.

Grooves 2 are formed on the surface of a single crystal silicon wafer 1 by etching or the like. At this time, the shape of the groove 2 is not limited to the V-shape as in the illustrated embodiment, but may be U-shape or other shapes (FIG. 1a).

An insulating layer 3 is formed by deposition or growth on the surface of the silicon wafer 1 on the side where the grooves 2 are formed [FIG. 1b].

A polysilicon layer 4 is formed on the insulating layer 3 to form the groove 2.
Fill in [Figure 1 c].

Polishing silicon wafer 1 from the opposite side,
The silicon wafer 1 is formed into a plurality of isolated islands 1 by the grooves 2.
Continue polishing until the DI board 5 is separated into a...
[Figure 1 d].

A masking 6 having a crystal plane different from the surface of the separation island 1a is formed on the entire surface of the separation island 1a of the DI substrate 5. The material of masking 6 is
Separation island 1a... Although there is no particular limitation as long as it has a crystal plane different from the surface, for example, separation island 1
When a is single-crystal silicon, it is preferable to use silicon oxide (SiO ₂ ) as the material for the masking 6 because it is easy to manufacture and the main components are the same as those of the isolation island 1a. [Figure 1 e].

The masking 6 on a predetermined portion of the DI substrate 5 (the surface of the isolation island 1a in the figure) is removed so as to have a predetermined shape [FIG. 1f].

Silicon crystals are grown on the entire surface of the DI substrate 5. At this time, in the part where the masking 6 has been removed, that is, in the part where the isolation island 1a is exposed, a single crystal silicon layer 7 is epitaxially grown on the single crystal plane of the surface of the isolation island 1a, and in other parts. ,
That is, a polysilicon layer 8 is grown on the masking 6 having a crystal plane different from that of the isolation island 1a [FIG. 1g].

Single crystal silicon layer 7 and polysilicon layer 8
A masking 9 is formed on a part of (in this case, the polysilicon layer 8a on the isolation island 1a' adjacent to the isolation island 1a on which the single crystal silicon layer 7 is formed). The material of this masking is not particularly limited, but for the same reason as masking 6 mentioned above,
Preferably, SiO ₂ is used (FIG. 1h).

Etching is performed to remove portions of the polysilicon layer 8 other than the masked single crystal silicon layer 7 and polysilicon layer 8a. The etching method is not particularly limited, but plasma etching is preferably used from the viewpoint of etching accuracy, ease of automation, and pollution control issues.
Various reactive gases can be used for plasma etching, but masking 9
When the material is SiO ₂ as mentioned above, for example, a mixed gas of CF ₄ +O ₂ is generally used, which etches single crystal silicon and polysilicon but hardly etches SiO ₂ . . Although the component ratio of the mixed gas is not particularly limited, it is generally used at a ratio of, for example, 96% CF ₄ and 4% O ₂ [Figure 1i].

Impurities are diffused into the solid-state relay material obtained as described above as shown in FIG. 1 j to l, and then electrode formation, wiring, etc. Create an element as shown in . FIG. 2 shows the elements of the solid state relay shown in FIG. 3, which are surrounded by two-dot chain lines, and their wiring.

An example of a process for forming the element shown in FIG. 2 is shown below.

By the steps shown in FIGS. 1a to 1i described above, n-type single crystal silicon layer 7 and polysilicon layer 8a are formed on p-type isolation islands 1a, 1a', . . . on substrate 5.

Next, the masking layers 6 and 9 on the substrate 5 are removed, and p-type impurities are diffused into both ends of the single-crystal silicon layer 7 to form a p-type layer 10 that will serve as a back gate (FIG. 1j).

A p-type impurity is diffused into the center of the single-crystal silicon layer 7 to form a p-type layer 11 that will become the gate V _G [FIG. 1k].

In the single-crystal silicon layer 7, an n-type impurity is diffused between the p-type layers 10 and 11 so as not to contact the p-type layers 10 and 11, and an n-type impurity is diffused into the single-crystal silicon layer 7, which becomes the drain V _D and the source V _S. The layers 12 and 13 are formed to create a junction FET 14.

In the polysilicon layer 8a, an n-type impurity is diffused into both ends thereof to form n-type layers 15, 15 which will serve as terminal portions, thereby creating a resistor 16. Various methods can be considered to adjust the resistance value of this resistor 16, but the polysilicon layer 8 formed on the isolation island 1a'
The resistance value can also be adjusted by adjusting the shape of a during its formation or by diffusing impurities into the completed polysilicon layer 8a. For example, if the shape of the polysilicon layer 8a is made such that the width at the center is narrower than the width at both ends, both terminal portions 15, 15
It is possible to increase the resistance value between. Furthermore, if the polysilicon layer 8a is n-type (for example, P-doped), the resistance value can be reduced by doping the same impurity into the polysilicon layer 8a by ion implantation or the like. [Figure 1 l].

When the junction FET 14 and the resistor 16 created in this way are wired as shown in FIG.
The part surrounded by the two-dot chain line in the figure is completed.

Furthermore, although not shown, light receiving elements (photo diodes) are created on a plurality of isolated islands on the same DI substrate 5 on which a single crystal silicon layer and a polysilicon layer are not formed, and are connected to each other. A first photo diode array 17 and a second photo diode array 18 are formed.

After wiring this as shown in Figure 3 and performing passivation, the junction type FET14
If the resistor 16 is shielded from light using an Al thin film or the like, the junction FET 14, the resistor 16, the first photo diode array 17 and the second photo diode array
The discharge circuit portion of the solid state relay consisting of the diode array 18 can be manufactured in one chip.

FIG. 4 shows an example of a solid state relay manufactured using the solid state relay material manufactured by the manufacturing method of the present invention.

As mentioned above, the substrate 20 disposed on the output side lead frame 19 is made of a bonding type using the manufacturing method of the solid state relay material of the present invention.
A FET 14, a resistor 16, and first and second photo diode arrays 17 and 18 are formed in one chip. A light emitting diode 21, which is an input element of the solid state relay, is supported by a lead frame 22 on the input side and is arranged so as to face the substrate 20. On the output side lead frame 19, a MOS transistor 23 is formed on another substrate, and its gate
V _G and source V _S are connected to the previous substrate 20 and output side lead frame 19 by wire bonding. After that, as shown by the dashed line in the figure, the circuit part (circuit shown in Figure 3) consisting of the substrate 20, MOS transistor 23 and light emitting diode 21 is sealed with resin, and the output and input sides are sealed. By cutting the respective connecting portions 19a, 21a, . . . of the lead frames 19, 21, a solid state relay made into a monolithic IC is completed.

The solid state relay manufactured in this way has a switching MOS transistor 23.
Photo diode array 1 as a discharge circuit
7, 18, resistance 16, normally ion junction type
It uses FET (hereinafter abbreviated as JFET)14. In this circuit, a current is passed through the light emitting diode 21 to cause it to emit light, and photo diode arrays 17 and 18 receive this light and convert it into current.
The JFET 14 is always in an on state, but when light is applied to the photodiode arrays 17 and 18, a potential difference is generated between the gate and source, so the JFET 14 becomes an off state, and in that state, the switching MOS transistor 23 electricity storage begins.
In other words, if such a circuit is used for discharging, the circuit will be in an open state when light is irradiated and will be in a short-circuited state when light is interrupted, so that the switching speed can be increased (the turn-on time can be shortened).
Furthermore, it is also possible to prevent the MOS transistor 23 from being neither on nor off when light irradiation is insufficient.

In the above embodiments, the case where the polysilicon layer left on the substrate is used as a resistor has been explained, but the polysilicon layer formed in this invention can also be used as other elements (for example, gate electrodes, etc.). It is also possible to do so.

As described above, in the manufacturing method of the solid state relay material of the present invention, a single crystal silicon layer and a polysilicon layer can be easily formed on a predetermined portion of the same substrate by epitaxial crystal growth without consideration of selectivity. This reduces the amount of solid-state relay materials used to manufacture solid-state relays, in which elements that require these single-crystal silicon layers and polysilicon layers are mixed with elements that do not. It can be made through a process. In addition, in this invention, by using a DI substrate, it is possible to completely insulate each element formed on the same chip, so it can be used for driving the gate of a MOS transistor.
It can also generate high voltages.

〔Effect of the invention〕

The manufacturing method of the solid state relay material of the present invention is constructed as described above, and requires a single crystal silicon layer and a polysilicon layer on the same chip by epitaxial crystal growth without consideration of selectivity. Because it is possible to easily separate the elements that are needed and the elements that are not needed in a few steps,
It becomes possible to easily manufacture materials for solid state relays consisting of a plurality of different elements with fewer steps.

[Brief explanation of drawings]

Figures 1a to 1 are explanatory diagrams showing each process of an embodiment of the present invention, and Figure 2 is an example of a solid state relay manufactured using the material for a solid state relay according to the present invention. FIG. 3 is a circuit diagram showing an example of the circuit of this solid state relay, and FIG. 4 is a plan view showing the mounting state of this solid state relay. 5... Substrate, 6, 9... Masking, 7... Single crystal silicon layer, 8, 8a... Polysilicon layer.

Claims (1)

[Claims] 1 Epitaxial crystal growth is performed by masking the DI substrate surface into a predetermined shape without considering selectivity, and a single crystal silicon layer is formed on the unmasked isolation islands, and other A polysilicon layer is formed in the area, and then the surface of the single crystal silicon layer is masked and etched to leave the single crystal silicon layer on a predetermined isolated island on the substrate, and the surface of the polysilicon layer is etched. A manufacturing method for materials for solid state relays in which a portion of the polysilicon layer is masked and etched, leaving this portion of the polysilicon layer on the substrate. 2. The method for producing a material for a solid state relay according to claim 1, wherein the remaining polysilicon layer is used as a resistor. 3. The method for producing a material for a solid state relay according to claim 2, which also includes the step of adjusting the resistance value by implanting ions into the remaining polysilicon layer. 4. The method for producing a material for a solid state relay according to any one of claims 1 to 3, wherein the etching is plasma etching using a reactive gas. 5 The single-crystal silicon layer is used as a junction FET, and the rest of the substrate surface is equipped with a photo film.
5. A method for producing a material for a solid state relay according to claim 2, wherein a diode is formed and, together with a resistor made of a polysilicon layer, a solid state relay is formed.