JPH0438005A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To reduce an arithmetic time of a FIR filter having a symmetrical coefficient by providing 1st and 2nd internal data buses, connecting input and output of 1st and 2nd RAMs respectively and interconnecting the 1st and 2nd internal data buses via a temporary register. CONSTITUTION:As soon as an input data of a FIR filter is written in a 1st RAM 2, the data is inputted to a 1st adder 5. On the other hand, a data delayed by 2N is read from a 2nd RAM 3 and inputted to the adder 5. The result of sum is inputted to a multiplier 6 and further inputted to a 2nd adder 7, in which the data is stored and operated After the product-sum operation by (N-1) times is implemented, as soon as the data after N-sample delay is inputted to the adder 5 and a temporary register 4, data after (N+1) sample delay is inputted to the adder 5 and the 2nd RAM 3. Then output data from the FIR filter is obtained as an output of an accumulator 8 by the product sum operation for N times.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing circuit, and particularly to an architecture suitable for high-speed calculation of an FIR filter with symmetrical multiplication coefficients.

[Conventional technology]

An example of a conventional digital signal processing circuit is shown in FIG. As shown in the figure, a ROM 1 that stores coefficients, a RAM 2 that stores calculation data, an internal data bus 9 that is connected to the input/output of this RAM 2, and an internal data bus 9 and RO
A multiplier 6 whose input terminals are connected to the outputs of the MI, an adder 7 whose inputs are the output of the multiplier 6 and the output of the Achiemulator 8, and an Achiemulator 8 which receives the output of the adder 7. It is constructed by connecting the output of the accumulator 8 and the internal data bus 9.

Next, the operation of the coefficient-symmetrical FIR filter using this conventional digital signal circuit will be explained.

Now, the transfer function H-monitor of the FIR filter with 2N taps is Let (Z) be the following formula.

H(Z) = h(, + hIZ +h2z
+...+h)1-Hz-""+hN-I Z-N
+00. + h2Z-2N"+ h IZ-""
'+ h6 Z- At this time, ROMIK is each coefficient. ,h□,hl,...
thN-1rhN-1p”・phl phl
+ hO are stored in order. Input data of the FIR filter is input to the multiplier 6 via the internal data bus 9, and a coefficient h0 is read from the ROM 1 and input to the multiplier 6 for multiplication. The result is input to the adder 7 and accumulated. Note that the Achiemulator 8 has been reset by this first operation.

At this time, at the same time, the input data is written to the RAM 2 in the 0th order, the input data after one sample time delay is read out from 8λM2 and inputted to the multiplier 6 via the internal data bus 9, and the coefficient h1 is inputted from the ROMI. is read out and multiplier 6
The result is input to the adder 7 and is subjected to an accumulation operation.

In this manner, the output data of the FIR filter is obtained via the internal data bus 9 as the output of the Achiem filter by performing 2N times of product-sum operations.

[Problem to be solved by the invention]

In this conventional digital signal processing circuit, for example, two
When calculating an FIR filter having N symmetrical coefficients, there is a problem in that 2N product-sum calculations are required, which increases the calculation time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital signal processing circuit that solves the table problem and reduces calculation time.

[Means to solve the problem]

The configuration of the digital signal processing circuit of the present invention includes a ROM that stores each coefficient of a transfer function of an FIR filter, a RAM that stores calculation data, a first adder that adds two inputs and obtains a result, and a first adder that adds two inputs to obtain a result. a multiplier that obtains a result by multiplying the output of the first adder by the value in the ROM; a second adder that obtains the result by adding the output of this multiplier and the accumulation addition output; an accumulator that connects the output of the second adder to its input to obtain the accumulated addition output, and the RAM is connected to the first
and a second RAM, the input and output of these first and second RAMs are connected to first and second internal data buses, respectively, and the input of the first adder is connected to the first and second internal data buses, respectively. , and the first and second internal data buses are connected via a tempo 2 register.

In the present invention, a register may be provided between each connection between the first adder and the multiplier and between the multiplier and the second adder.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In this digital signal processing circuit, ROM1 has:
For example, the coefficients of the filter are stored in RAM 2.3.
contains filter delay data. here,
Assume that the transfer function H(Z) of an FIR filter with symmetric coefficients of 2N taps is given by the following equation.

H(Z)-h0+h1z +h2Z +-,+
hN, Z-””+h Z +・・-+h Z
+hlZ+ h oZ-2N The @ calculation process at this time will be explained. First of all, ROMz has ho
, h, hl, .
Next, 1, 2, 3 . ...N delayed data is also transferred to the second) LAM3 by N+1°N
+2, N+3, . . . 2N delayed data is stored.

The input data of the FIR filter is written to the first RAM 2 via the first internal data bus 9.
is input to the adder 5. On the other hand, the delayed data is read from the second pasteboard 3 to the second internal data bus 1.
It is input to the first adder 5 via 0t-. The addition result is input to the multiplier 6 and is also multiplied by a coefficient from the ROMI. is read out and input to the multiplier 6. Further, the multiplication result is input to the second adder 7, and is subjected to a savings operation. The accumulator 8 has been reset by this first operation.

Next, the input data after one sample delay is stored in the first RAM2.
At the same time, data after 2N-1 sample delay is read from the second RAM 3 and inputted to the first adder 5 via the first internal data bus 9. input to the first adder 5; The addition result is input to the multiplier 6, and the coefficient h□ is read from the ROMI and input to the multiplier 6. Furthermore, the multiplication result is input to the second adder 7 and accumulated. After N-1 product-sum operations have been performed in this way, the data after the N-sample delay is read out from the first AM 2 and sent to the first adder 5 and temporary register 8 via the first internal data bus 9. At the same time, the data after N11 samples are outputted from the temporary register 8 to the second internal data bus 10 and inputted to the first adder 5 and the second RAM 3. The addition result is input to the multiplier 6, and the coefficient hN-1 is read from the ROM 1 and input to the multiplier 6. Furthermore, the 1 multiplication result is input to the second adder 7 and is subjected to an accumulation operation. As described above, the output data of the FIR filter is transferred to the first or second internal data bus 9, 10 as the output of the accumulator 8 by N times of product-sum operations.
obtained through.

Although the above example shows the case where the input data of the FIR filter is input to the first internal data bus 9, it is easy to see that the same process can be performed when the input data is input to the second internal data bus 10.

It is also possible to provide a register between the input and output of the first adder 9 multiplier and the second adder shown above to reduce the calculation speed required for each calculation unit.

〔Effect of the invention〕

As explained above, the present invention provides first and second internal data buses, and provides first and second internal data buses. The input and output of the second RAM are connected respectively, and the input and output of the second RAM are connected respectively. By connecting the second internal data bus through a temporary register, F
This has the effect that the calculation time of the IB-filter can be reduced to 1/2 of that of the conventional method.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional digital signal processing circuit. 1...90M12.3...RAM, 4...temporary register, 5.7...adder, 6...multiplier,
8...Accumulator, 9.10...Internal data bus. Agent: Susumu Uchihara, patent attorney Figure 1 Figure 2

Claims (1)

[Claims] 1. RO that stores each coefficient of the transfer function of the FIR filter
M, a RAM that stores calculation data, a first adder that adds two inputs to obtain a result, and a multiplier that multiplies the output of the first adder and the value in the ROM to obtain a result. a second adder that obtains a result by adding the output of this multiplier and an accumulation addition output, and an accumulator that connects the output of this second adder to an input and obtains the accumulation addition output, The RAM includes first and second RAMs, inputs and outputs of the first and second RAMs are connected to first and second internal data buses, respectively, and inputs of the first adder are connected to the first and second internal data buses, respectively. 1. A digital signal processing circuit connected to first and second internal data buses, the first and second internal data buses being connected via a temporary register. 2. The digital signal processing circuit according to claim 1, further comprising registers provided between each connection between the first adder and the multiplier and between the multiplier and the second adder.