JPH01284009A - Digital filter processing unit, digital protection relay device and digital differential relay device - Google Patents

Abstract

PURPOSE:To attain fast discrimination of relay operation with high accuracy by obtaining an input data required for the calculation of a protection relay at a frequency (density) being N times the sampling frequency and constituting a protection relay device through the use of the processing unit of such data. CONSTITUTION:An input data representing the state variable such as an inputted voltage or current is subjected to A/D conversion (4) for each sampling period Ts. Then filter processing by digital filter calculation is applied. The filter processing is repeated based on the preset filter coefficient for a period TF being 1/N of the sampling period Ts and it is possible to offer the input data required for the calculation of the protection relay at a frequency higher than the sampling frequency thereby attaining high speed operation discrimination and highly accurate operation of the protection relay. Furthermore, the frequency characteristic in the filter calculation operation is a characteristic passing the fundamental wave frequency component of the input data while eliminating a high frequency, and even if filter processing is applied to a simulated input data in place of a true input data, the fundamental wave data equal to the processing of sampling substantially at a short pitch of the frequency being a multiple of N is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital filter processing device, a digital protection relay device and a digital differential relay device using the same.

[Conventional technology]

Conventional digital protection relays are described in the Journal of the Institute of Electrical Engineers of Japan, Vol. 105, 1.
No. 2, page 12 (1986) and Hitachi Review Vol. 1.61. N
The input filter consists of an RC active filter as discussed in J.D. o1l (1979-11). In addition, protection relay calculations are generally performed at 12 points of the fundamental wave.
Input data filtered at twice the frequency is sampled, and this data is used for the calculation.

[Problem to be solved by the invention]

However, the above-mentioned conventional technology has the following problems to be solved.

In other words, the sampling frequency of the input data is 12 times the fundamental wave frequency of the input data (30
Because of the pitch, relay operation determination related to protection relay calculation cannot be made shorter than 30' pitch, which limits high-speed determination and impedes high accuracy.

Further, since the input filter is an analog filter using an RC active filter, variations in characteristics of elements such as resistors, capacitors, and operational amplifiers that constitute the filter cannot be avoided. Therefore, in order to filter multiple input data at the same time, multiple RC
When active filters are provided in parallel, there is a problem that variations in characteristics occur among them, resulting in a decrease in accuracy.

An object of the present invention is to solve the above-mentioned conventional problems, in other words, to provide a filter processing device that can contribute to high accuracy and high-speed determination of protection relays, and to provide a protection relay device and a device using the filter processing device. An object of the present invention is to provide a differential relay device.

[Means to solve the problem]

In order to achieve the above object, the filter processing device of the present invention includes an A/D conversion means that captures input data at a constant sampling period Ts and converts it into digital data, and this A/D conversion means.
The digital filter means is equipped with a digital filter means for performing a filter operation process on the D-converted input data. A digital filter processing device configured to perform a filter operation on the input data when A/D converted input data is input, and execute a filter operation on predetermined pseudo input data when the input data is not input. That's what I did.

Note that it is preferable that the filter calculation process is performed based on several consecutive past input data including pseudo input data.

On the other hand, the protection relay device of the present invention has the above-mentioned digital filter processing device which takes the state quantity of the electric power system as input data, and filter processing is performed in synchronization with the execution period Tp of the digital filter means in the execution period. This is a digital protection relay device that includes a protection relay means that performs protection relay calculation processing based on input data.

Note that it is preferable that the digital filter means and the protection relay means are integrally configured using the same digital signal processor, and the filter operation and the protection relay operation are executed in a time-sharing manner within the execution period Tp.

Further, the differential relay calculation device of the present invention includes the digital protection relay devices described above at at least two points in the power system, and input data A/D converted by the protection relay devices is mutually transmitted via a communication line. This is a digital differential protection relay device configured to transmit data and perform differential relay calculations.

In addition, the above pseudo input data includes: (i) data that uses the latest input data (in other words, it is assumed that there is no change in the input data), (i) interpolated data obtained from input data that includes several consecutive past points of pseudo input data. (2) A method in which the pseudo input data is zero and a filter calculation execution period TF that is 1/2 of the sampling period Ts; (2) A method in which the latest A/D converted input data is multiplied by a predetermined coefficient. , etc. can be applied.

[Effect]

According to the present invention, the object is achieved by the following actions.

According to the protective relay device having the above configuration, input data indicating state quantities such as voltage and current are first A/D converted at every sampling period Ts. After that, filter processing is performed by digital filter calculation.

This filtering process is repeated at a period TF that is 1/N of the sampling period Ts based on a preset filter coefficient. Therefore, it becomes possible to provide the input data necessary for the protection relay calculation at a frequency higher than the sampling frequency. This makes it possible to speed up operation determination and contribute to higher accuracy of the protection relay.

It goes without saying that the filter calculation process has a frequency characteristic that allows the fundamental frequency component of the input data to pass while removing high frequencies. Therefore, even if filter processing is performed on pseudo input data instead of real input data, high frequency components caused by the pseudo input data will be removed.
Fundamental wave data equivalent to the throat sampled at a short pitch with substantially N times the frequency can be obtained.

In addition, by digitizing the filter processing, it is possible to eliminate the problems inherent in analog filters such as RC active filters, such as variations due to changes in element characteristics, and high accuracy is achieved in this aspect as well. .

On the other hand, according to the protection relay device having the digital filter processing device configured as described above, the pitch of the protection relay arithmetic processing is shortened, the speed of operation determination is improved, and it is possible to perform highly accurate determination.

Moreover, if applied to a differential relay, it is possible to lengthen the transmission period of one communication line, and the load on the communication line can be reduced.

〔Example〕

The present invention will be explained below using examples. FIG. 1 shows an embodiment of a digital protection relay device to which the present invention is applied, and particularly shows a block configuration centered on an analog input section.

In the figure, aliasing error prevention filters IA, 1B...
IM is a filter for removing signals having a frequency component of 1/2 or more of the sampling frequency fs in each input data D to Dm. The output of these is the multiplexer (MP
The data is sequentially stored in the sample/hold circuit (S/H) 3 via the X) 2, and simultaneously converted into digital input data in the A/D converter 4 and stored in the buffer memory 5. The contents of the buffer memory 5 are input to a digital signal processor (DSP) 7 via an internal bus 6. Further, the DSP 7 is connected via an internal bus 6 to a ROM 8 in which a DSP instruction program is stored, and a dual-port RAM 9 that can be accessed from both directions. The RAM 9 can be connected to other processing devices via an interface circuit 1° and a standardized bus 11. Further, the timing control circuit is configured to output synchronization signals necessary for each of the above-mentioned constituent blocks.

Here, a schematic configuration of the DSP 7 is shown in FIG.

As shown in the figure, DSP7 is an instruction ROM
21. m-bit x m-bit high-speed parallel multiplier (MPY)
22, a data RAM 23, an address register (AR) 24 that specifies the address of the external memory of the DSP 7, a data register (DR) 25, an ALU (Arithmetic Logic
c Unit) 26, Accumulator (ACC) 27
, a timing control circuit 28, and an internal bus (data bus, address bus) 29 of the DSP 7. The high-speed parallel multiplier MPY22 multiplies the input data inA and inB during one instruction cycle, and the result ou
It outputs tC. DS configured like this
The P7 features MPY22, which enables multiply-accumulate operations in one instruction cycle, and pipeline processing, which allows for high-speed processing of fixed and floating point data. It is known that numerical calculations can be realized.

For this reason, it is suitable for digital filter operations that require repeating product-sum operations on fixed and floating point data at high speed. Furthermore, digital filters have advantages over analog filters, such as not requiring mounting adjustments, no aging, easy changes in specifications and characteristics, and the ability to be made smaller.

FIG. 3 shows a conceptual block diagram of the digital filter. Needless to say, this configuration is realized by a program of the DSP7. In the same figure (a), I I R (I n
finite extent I pulse Re
5ponse) type filter, the same figure (b) is F I R (
Finite extent I a+pulse R
This is a block configuration of an e5ponse) type filter.

In the same figure (a), Xn is an input signal, numeral 31 is each coefficient block, gain coefficients, A□, A2 . B and B2 are filter coefficients.

Reference numeral 32 is a delay block, which is a block (Wn-8) that delays the signal Wn by one time of the filtering period TF.
Similarly, there is a block (Wn-2) that is delayed by two times. Reference numeral 33 is an addition block, and Yn is filter output data. Expressing (,) in the figure as a formula, the following formula (1), (
2) will be processed.

Wn=−Xn+B□・Wn−□+B, ・Wn−z”
' (1) Yn=Wn+A, ・Wn-, +Az ・W
n−z ·−···(2) K gain coefficient Al, A2. Bl, B2: Filter coefficients is stored in the internal RAM 23 of the DSP 7. On the other hand, in the same figure (b), X'n input data Y'n
indicates output data. Reference numeral 34 is a delay block;
x'n-1 is a block delayed by one time as described above,
X'n-2 indicates a block delayed by two times. code 3
5 is a filter coefficient block, each filter coefficient A'
o, A'□.

A'2 is set. Reference numeral 36 is an addition block.

This diagram can be expressed by the following equation (3).

Y'n=A'.・X'n+A'□・X'nyu+A'・
X'n1 (3) Note that the configuration of the filter is not limited to the one described above, and it goes without saying that different types of filters and filters of different orders can be arbitrarily configured and changed using software.

Taking the above IIR type digital filter as an example, with the same configuration, as shown in the following equations (4) to (), a low pass filter, a band pass filter, a bypass filter, a notch filter, a low pass filter, a bypass notch filter, etc. and all-pass filter can be realized only by changing the filter coefficients. Note that H(z) is a transfer function, and Z corresponds to S in an analog system.

(low pass filter) (bandpass filter) (Bypass filter) (Notchi filter) Here, r=2・cos2πfo−T T: sampling period fo: blocking frequency (all pass filter) A frequency characteristic diagram of these filters is shown in FIG.

(a) is a low-pass filter, (b) is a band-pass filter, (C) is a bypass filter, (d) is a notch filter, (e) is a low-pass notch filter, ( f) is a bypass notch filter, and (g) in the figure is an all-pass filter.

The operation of the embodiment configured as described above will be explained with reference to the flowcharts of the processing procedure shown in FIGS. 1 and 5.

System state quantity data Dm detected by voltage transformers and current transformers provided in the power system are input to MPX2 via foldback error prevention filters IA to IM. The aliasing error prevention filters IA to iM remove aliasing errors associated with sampling and also operate as an input cover sofa.

The MPX 2 periodically and sequentially switches the input data D to Dm and inputs them to the S/H circuit 3. This S/H circuit 3 is an A/D
While the converter 4 is operating, analog input data D at the same time
□ to Dm are held, thereby increasing the A/D conversion accuracy. The A/D converted input data is stored in the buffer memory 5. The DSP 7 takes in input data stored in the buffer memory 5 via an internal bus 9 and performs arithmetic processing based on a program stored in an instruction ROM 8.

The DSP 7 writes the calculated result to the multi-board RAM 8 via the internal bus 9 again. Since the RAM 8 is a dual-port RAM and can be accessed from both directions, output data can be output via the interface circuit 10 from a port different from the one written from the DSP 7 side.

Here, the procedure of arithmetic processing in the DSP 7 shown in FIG. 5 will be explained. Step 101 is an initial process in which the memory, registers, etc. inside the DSP 7 are cleared and the equation (1) is executed.

The digital filter coefficients related to (2) and the like are input to the data RAM 23 inside the DSP 7. Note that the coefficient of the digital filter is calculated by multiplying the frequency fp of the execution cycle of the filter operation by N times the sampling frequency fs of the input data (N: integer).
Design as.

In step 102, periodization processing is performed and the system is placed in an interrupt standby state. Then, in step 103, input data is read from the buffer memory 5 and taken into the data RAM 23 according to a command based on the execution period TP of the filter calculation. For this imported input data, step 104
The filter calculation process according to the above equations (1) and (2) is executed. The next step 105 is to execute a protection relay calculation for detecting an accident in the power system according to a preset procedure based on the filtered input data. For example, in the case of a distance relay that calculates the distance to an accident point, the calculation shown in linear equation (9) is executed.

X (I-Z-V) I ・Z>a--(9) ■ = Current value ■ = Voltage value Z: Setting value α: Comparison value In step 106, the results of operation judgment etc. obtained by protective relay calculation is output to the dual port RAM 9.

Next, in step 107, it is determined whether the number of executions of the filter calculation and the protection relay calculation in the sampling period Ts has reached N. If affirmative, the process returns to the synchronization process of step 102, which proceeds to the process of the next sampling period Ts. If the determination is negative, the process proceeds to step 108, which is a pseudo input data calculation, in which pseudo data of the input data to be subjected to the next filtering process is set, and based on this, the processes of steps 104 and 105 are repeated.

As mentioned above, the following methods can be applied to create this pseudo input data: 6 ■ Method using the latest input data (i.e., it is assumed that there is no change in the input data), ■ Past continuity A method using interpolated data obtained from input data including several points of pseudo input data, ■ A method in which the pseudo input data is set to zero and the execution period TF of the filter operation is set to 1/2 of the sampling period Ts, ■ A/D A method in which the latest converted input data is multiplied by a predetermined coefficient.

Here, the above-mentioned processing procedure will be explained using a time chart.

FIG. 6 shows the ratio of the above periods N = T s / T p
This is a time chart when (= fp/f s) is set to 2. Figure (a) shows the timing of the sample and hold command signal given to the S/H circuit 3.
At time s, input data D to Dm at m points are held at times a1 to am. The figure (b) shows the A/D converter 4.
It shows the timing of the command signal given to the input data D1 to Dm at the same period as the sampling period Ts, and the digital input data X to Xm at times b1 to bm.
is converted to

Then, as shown in FIG. 3(c), the data are sequentially stored in the buffer memory 5 at times C-cm. At the timing when this storage is completed, the process of the DPS 7 shown in FIG. 2(d) is started. Input data X1 to Xm of the buffer memory 5 are taken in during time periods d1□, and first filter calculation processing is performed on these input data X to Xm during time periods d and 2, respectively. Next time d□,
performs a protection relay operation based on each filtered data X. Then, at time d14, the result of the protection relay calculation is output. Following this output, the second filter calculation and protection relay calculation are started. First, in the time period d2□, pseudo input data is determined by calculation or the like using any of the methods described above.

In the next time period d2□ and d23, filter calculation and protection relay calculation are performed in the same way as the first time, and the results are used in time period d2□ and d23.
Output and exit. In this way, the sampling period T
Execution period of filter processing etc. within one period of s is T s /
Do it twice with 2.

FIGS. 7 to 9 show a method for setting pseudo input data and a filtered output waveform in comparison therewith. Both are examples where N=2, and their figures (a) show the sampling period Ts, figure (b) shows the waveform to be filtered including pseudo input data (indicated by the dotted line in the figure), and figure ( c)
shows the waveform of the filtered result.

FIG. 7 is an example of method (2) described above. At time t 'tt 'zt... when true input data cannot be obtained, it is assumed that there is no change in the input data, and the immediately preceding true value is This is an example of processing using input data as is. According to this, it is possible to obtain a signal containing only the fundamental wave component, as shown in FIG. 2(c). First, high-frequency components are removed in the stopband of filter calculation processing, and highly accurate input data can be obtained. Thereby, protection relay calculation can be performed at a frequency fp that is twice the sampling frequency fs.

FIG. 8 shows an example of the method (2) described above.

Time t '11 t 'a when true input data is not obtained
When executing t..., pseudo input data is set by interpolating from the slope of the input data at the previous t step or t2. In this example as well, it is possible to obtain a signal containing only the fundamental wave component as in FIG. 7.

FIG. 9 is an example of the above-mentioned method (2), in which when executing at time t '11 '27 . In this example as well, a signal containing only the fundamental wave component can be obtained as in FIG.

Although not shown in FIG. 1, it can be easily understood from the examples of FIGS. 7 to 9 that similar results can be obtained with the method (2) described above.

Here, the frequency characteristics of the filter obtained by setting the frequency fp of the execution cycle of filter processing to N times the frequency fs of the sampling cycle of input data will be explained.

FIG. 10 shows an example of the frequency characteristics of the bandpass filter of the digital filter processing device of this embodiment. The horizontal axis in the figure represents frequency, and the vertical axis represents gain. In the figure, curve 41 is the target characteristic, and curve 42 is the characteristic 1 curve 43 of this embodiment.
is the characteristic when fs and fp are made equal.

Generally, a bandpass filter has a zero point frequency of ○Hz and 1
Since it is set to /2fp (1/2 of the filter execution frequency), when fs=fp, the characteristic deviates significantly from the target curve 41, as shown in the characteristic curve 43. On the other hand, according to this embodiment, since the filter execution frequency fp is twice the sampling frequency fs, the zero point frequency is twice the curve 43, and the error with the target characteristic 41 is reduced, resulting in high precision. That will happen.

Also, since digital filters are discrete signal processing, S
/H circuit 3 is preceded by a filter LA- for preventing aliasing errors.
M is required, and it is necessary to cut off frequencies equal to or higher than 1/2 of the sampling frequency fs.

In this respect, according to this embodiment, since the processing execution frequency fp of the digital filter becomes high, a filter with a gentle attenuation is sufficient as the characteristic of the filter LA-M for preventing aliasing errors. This allows the aliasing error prevention filter to be made smaller.

FIG. 11 shows an embodiment in which a differential relay device is constructed using the digital filter processing device according to the present invention. As shown in the figure, protective relay devices 52A and 52B with the same configuration are installed at two distant points on a power transmission line 51, and system status quantities (current data) are exchanged between them via a signal transmission line 53, and the difference between them is This is an attempt to determine system accidents using dynamic calculations. Each protection relay device 52A, 52
B is an A/D including a current transformer 54, a transformer 55, and an S/H circuit.
Converters 56A, B, digital filters 57A, B, C1
It is configured to include a communication terminal 58 and a protection relay calculation block 59.

In such a differential relay device, it is desirable for accuracy to increase the sampling frequency fs of current data. However, there are cases where fs cannot be increased due to limitations due to the transmission capacity of the transmission line 53. In this regard, according to the digital filter processing device of the present invention.

Even if the sampling frequency fs of the input data to be transmitted is low, it is possible to obtain input data processed at N times the frequency by filtering, and it is possible to perform highly accurate protection relay calculations.

〔Effect of the invention〕

As explained above, according to the digital filter processing device of the present invention, input data necessary for protection relay calculation can be obtained at a frequency (density) that is N times higher than the sampling frequency. By configuring a protective relay device using this, relay operation determination can be made at high speed and with high accuracy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of a digital protection relay device according to an embodiment of the present invention, FIG. 2 is a block diagram of a DSP according to the embodiment of FIG. 1, and FIG. 3 is a concrete diagram of the digital filter according to the embodiment of FIG. The conceptual configuration diagram of the example, Figure 4 is the filter characteristic diagram, and Figure 5 is the filter characteristic diagram.
FIG. 6 is a time chart showing the operation of the embodiment of FIG. 1; FIGS. 7 to 9 show the operation of the pseudo input data embodiment. A waveform diagram, FIG. 10 is a diagram explaining the effect of the frequency characteristics of the embodiment in FIG. 1, and FIG. 11 is a configuration diagram of a differential relay device according to an embodiment of the present invention. 3... Sample hold circuit, 4... A/D converter, 7... Digital signal processor, 52A, 52
B...Protective relay device, 53... Signal transmission path.

Claims (1)

[Claims] 1. A/D conversion means that captures input data at a constant sampling period Ts and converts it into digital data;
/D-converted input data, and the digital filter means executes the filter operation at a period Tp having a frequency that is an integer N times the sampling period Ts. A digital filter configured to perform a filter operation on the input data when the A/D converted input data is input, and perform a filter operation on predetermined pseudo input data when the input data is not input. Processing equipment. 2. The digital filter processing device according to claim 1, wherein the filter calculation process is performed based on several past consecutive input data including pseudo input data. 3. The digital filter processing device according to claim 1 or 2, wherein the pseudo input data is the latest input data subjected to A/D conversion. 4. The digital filter processing device according to claim 1 or 2, wherein the pseudo input data is interpolated data obtained from input data including past several consecutive points of pseudo input data. 5. The digital filter processing device according to claim 1 or 2, wherein the execution period Tp of the filter calculation is 1/2 of the sampling period Ts, and the pseudo input data is zero. 6. The digital filter processing device according to claim 1 or 2, wherein the pseudo input data is obtained by multiplying the latest A/D converted input data by a predetermined coefficient. 7. A digital filter processing device according to any one of claims 1 to 6, wherein the input data is a state quantity of an electric power system,
A digital protection relay device comprising a protection relay unit that performs protection relay arithmetic processing based on input data filtered in the execution cycle in synchronization with the execution cycle Tp of the digital filter unit. 8. The digital filter according to claim 7, wherein the digital filter means and the protection relay means are integrally configured using the same digital signal processor, and the filter operation and the protection relay operation are executed in a time-sharing manner within an execution period Tp. relay device. 9. The digital protection relay device according to claim 7 or 8 is provided at at least two points in the power system, and the input data A/D converted by each protection relay device is mutually transmitted via a communication line to generate a differential signal. A digital differential relay device configured to perform relay calculations.