JPH04197018A - Digital arithmetic processing unit - Google Patents

Abstract

PURPOSE:To determine the size of an input signal with high accuracy by changing the sampling frequency according to the input signal frequency, and changing the input signal so that it may be the center frequency at all times the filter characteristic. CONSTITUTION:When an external cyclic signal Sp is applied to the clear terminals CLRs of a counter 1 and a counter 2, both the counter 1 and the counter 2 get in initial conditions, and the output signals are all cleared, and the output of a decoder 2d also gets in initial condition. Accordingly, by the external signal Sp, the cycle of the output signal (S/H, DSP interrupt signal) of the decoder 2d can be made variable. That is, the center frequency changes in proportion to the frequency of the external synchronous signal Sp. Accordingly, if one changes the external synchronous signal Sp according to the system frequency of the power system, from the characteristic of a filter, the system frequency can always be made the center frequency of the band pass filter.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a power system digital control protection device, and in particular to a method for sampling and digital filtering an input signal according to the system frequency of the power system, and its method. Regarding circuit configuration.

[Conventional technology]

Conventional digital control protection devices are described in Hitachi Review Vol. 6.
1. The input signal was asynchronously sampled at a sampling frequency of 600 Hz or 720 Hz (as shown in Nα11).
First, the frequency of the input signal was determined by sampling at an electrical angle of 30°, and this frequency was used to perform frequency correction calculations to determine the effective value of the voltage required for protection calculations.

The frequency calculation algorithm first samples an alternating current input signal at a constant period, and takes advantage of the fact that the polarity of data near the zero point changes linearly. Furthermore, in order to improve calculation accuracy, intermediate data is obtained from the sampling data at the rising and falling points to obtain the frequency.

In order to obtain the effective value of voltage, etc., the frequency obtained as described above is used and calculated by substituting it into the effective value calculation formula.

Further, the input filter was configured with an RC active filter, and A/D conversion was performed after filtering.

[Problem to be solved by the invention]

The above conventional technology transmits grid signals from the power grid at 600Hz.
Alternatively, it is necessary to sample at 720 Hz, approximate the frequency, and perform complicated correction calculations based on this frequency. As a result, the amount of calculation increases, making it necessary to add many calculation units, resulting in an increase in the scale of the device and a decrease in reliability.

There were problems such as increased power consumption and cost, and there was also a limit to accuracy.

Furthermore, since the input filter in the above conventional technology is constituted by an RC active filter, (1) characteristic deterioration occurs due to element variations, temperature characteristics, and aging.

(2) There are many steps such as adjustment work, resulting in high costs.

There were other problems.

In addition, since A/D conversion is performed after filtering with an input filter, the error of A/D conversion remains unchanged during calculation (
(For example, voltage detection), there were naturally limits to accuracy.

An object of the present invention is to digitize the conventional input filter, which is composed of an RC active filter, using a digital signal processor (DSP) and to sample at a higher frequency than the conventional sampling frequency. The aim is to achieve high precision.

Furthermore, by changing the sampling frequency of the digital filter according to the frequency of the input signal and changing the filter characteristics so that the input signal always has the center frequency, conventional complicated frequency correction calculations are no longer necessary. The goal is to simplify the algorithm.

Another object of the present invention is to provide a method for highly accurately synchronizing a unit that performs high-speed sampling and digital filtering and an arithmetic processing unit having a different arithmetic cycle.

Furthermore, another object of the present invention is to provide a method for checking abnormalities in a sampling signal according to the above-mentioned input signal.

[Means to solve the problem]

In order to achieve the above objectives, (1) sampling input data faster than before;
/D conversion, and after conversion, constitutes an analog input unit that performs digital filtering using a DSP.

(2) The sampling signal in (1) is changed at the same rate according to the frequency of the input signal and is applied to the analog input unit in (1) above.

As described above, even if the frequency of the input signal changes somewhat, the center frequency of the filter characteristic changes, so that the amplitude of the filter output can always be made the same with respect to the input signal. That is, the magnitude of the input signal can be determined accurately.

In addition, in order to achieve the other objectives mentioned above, for a calculation unit that performs calculations at a cycle of 600Hz or 720Hz,
Digital filtering is performed at n times the calculation cycle (n is an integer), and the digital filter calculation output is thinned out before data is transmitted.

Furthermore, in order to achieve another object of the present invention, an analog input unit that performs digital filter calculations is provided with an oscillation circuit, and when there is no external sampling signal, the clock signal of the oscillation circuit within the unit is transmitted. use The frequency at this time is l/m times the external sampling frequency (m is an integer m = 2.3...),
The coefficients of the filter are set in advance so that the input signal becomes zero due to this sampling signal. This is achieved by constantly monitoring the ratio of the filter output to the input signal with respect to this input signal.

[Effect]

According to the digital arithmetic processing device configured as described above, input data is first A/D converted and then filtered by a digital filter operation by a digital signal processor. This filtering process is repeated every sampling period based on preset filter coefficients. Since the sampling period is changed according to the input signal frequency, the filter characteristics change so that the input signal always has the center frequency, for example. That is, if the amplitude of the center frequency is 1.0 P, U, even if the frequency of the input signal changes somewhat, the filter output will always be 1.0 P, U for the input signal component.

Therefore, when determining the magnitude of an input signal, it can be determined with high accuracy regardless of frequency fluctuations of the input signal.

Further, in the analog input unit, the calculation period of the digital filter calculation is set to 1 of the calculation period of the other calculation units.
/ n times faster (n is an integer, 2, 3...), and the filter output data is converted to 1 by the analog input unit.
/ n and sends an interrupt signal. By doing this, complete synchronization can be achieved.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 shows an analog input unit of a digital arithmetic processing device to which the present invention is applied.

In FIG. 1, the input unit IA inputs analog state quantity data (input, in2...1n) from the power system.
This is a unit that has the function of taking in N), converting it into a digital quantity, performing filter processing by digital calculation, and outputting the calculation result.

The unit shown in IB is analog state quantity data (l n
x+ l nz...1nN), detects one frequency, and generates a signal Sp corresponding to the frequency.

Next, the internal configuration of the input unit IA will be explained.

1 a□, 1 a2-1 aN is the input signal C1n z
This is a low pass filter (LPF) that removes harmonics superimposed on p l n 2...1 ns). LPF is
This mainly prevents errors due to sampling aliasing components.

1 b,, 1b2-1 bN are each LPF (l
al.

This is a sample-and-hold circuit (S/H) that samples and holds the outputs of the terminals (la2...1aN) at the same time. The S/H is operated by a sampling command signal 5syH generated from a timing control circuit shown in 1k.

1c is a signal for switching sampled and held data (
This is a multiplexer (MPX) that switches sequentially by S Mpxl...SMpxn).

1d is analog state quantity data ("nx+inz...
1nN) as digital data CXx t X2 ・-X
s) analog/digital converter (A/D)
It is.

The A/D starts an A/D conversion operation in response to an A/D conversion command signal S^7D from the timing control circuit.

1e is a dual port memory (RAMI) having bidirectional ports on the A/D side and the local bus side of 1j. This RAM stores A/D conversion data in response to a write signal S^7D.

1f is a digital signal processor (Digital
Signal Processor: DSP
) and is a processor that has multiplication functions and can perform high-speed calculations. A detailed explanation will be given later.

1g is a memory (ROM) that stores the command words (instructions) of the DSP.

1h is a dual port memory (RA) with bidirectional ports on the IQ system bus side and 1j local bus side.
M2).

11 is an interface circuit with the IQ system bus.

Further, an arithmetic unit having a processor, a memory unit, etc. can be easily connected to the IQ system bus.

FIG. 2 is a block diagram of the timing control circuit indicated by 1k in FIG. 1.

In FIG. 2, 2a is an oscillation circuit, 2b and 2c are counters 1, and counter 2.2d is a decoder.

The operation of the blocks shown in FIG. 2 will be explained below.

First, the oscillation circuit 2a oscillates at a fixed frequency and then divides the oscillation frequency. Generally, a crystal resonator is used.

The output of the oscillation circuit 2a is applied to the clock input terminals C of the counters 1 and 2. Also.

The output signal (carry signal) of counter 1 is applied to count enable terminal E of counter 2.

This configuration constitutes a synchronous counter.

Further, the output signals of the counters 1 and 2 (outputs frequency-divided by 2") and the output of the oscillation circuit 2a are input to the decoder 2d. The decoder 2d decodes the input signals and outputs various control signals (SS/HIS Mpxx～S M
pxn r S^10t SRAM, 5DSP).

Such a decoder can be easily configured using a programmable logic device (PLD) or the like.

Next, the external periodic signal Sp is applied to the clear terminals CLR of the counters 1 and 2. This outer periphery synchronization signal Sp is applied from the frequency detection and pulse generation section shown in FIG. 1B.

When the signal Sp is input, the counters 1 and 2 are all in their initial states, all output signals are cleared, and the output of the decoder 2d is also in its initial state.

Therefore, the period of the output signal (S/H, DSP interrupt signal) of the decoder 2d can be made variable by the external synchronization signal Sp.

FIG. 3 is a timing waveform example showing the operation of the analog input unit IA shown in FIG.

The timing control circuit 1 operates based on the output CLK (CLK in FIG. 3(a)) of the built-in oscillation circuit 2a.

Hereinafter, the operation of the circuits shown in FIGS. 1 and 2 will be explained using FIG. 3.

First, a synchronization signal Sp shown in (b) is applied.

In this case, it is assumed that "L n is active. The frequency of sp is fs (=1/T), and there is a relationship as shown in the following equation with respect to the system frequency of the power system.

fs=to-f. ”・(1)k
=1.2-=M, fo: System frequency 7M: Integer The outputs of counters 1 and 2 shown at 2b and 2c in FIG. Sp is 1
Immediately after becoming 1 L II, everything is cleared and II L
II and starts counting up from the beginning. The counter output is the output of the previous stage divided by 2'' (n is 1.2...M integer).

2d in FIG. 2 is the CLK and counter output (c) ~
(g) is input, and various control signals (h) to (Q) are generated.

For example, the S/H command signal (i) becomes active (“L”) if the following conditional expression is satisfied.

S S/H = Counter output Counter output 2, Counter output 3, Counter output 4, Counter output 5... (2) Similarly, the control signals (h) to (Q) can be created by , which is easy to understand.

The S/H of 1b to 1 in FIG. 1 is sampled at the same time according to the S/H command signal of (i), and this value is held.

The MPX of the IC shown in FIG. 1 sequentially switches the S/H outputs of channels 1 to N (N=8 in this example) as shown in (h) using the counter outputs of (e) to (g).

1d in Fig. 1 inputs the signals of each channel switched by the MPX, and controls the A/D by the A/D command shown in (j).
Start D conversion and output to RAMI shown in 1e.

The RAMI 1e in FIG. 1 stores the A/D conversion output data from the RAM write signal shown in (k).

The DSP 1f in FIG. 1 performs calculations according to the intended interrupt processing in response to the DSP interrupt signal indicated by (Ω). At this time, processing is performed using the instruction word stored in the ROM shown in 1g. Furthermore, the same implementation can be achieved by providing a ROM inside the DSP in addition to the ROM shown here.

An example of DSP processing is shown in FIG. 3(m). First, input the data sampled at time t-1.

Perform digital filter calculation and set the filter pressure to the first
It is output to RAM2 shown in FIG. 1h.

By repeating the above-described operation every period T, a digital filter can be realized, as will be described in detail later, and harmonics superimposed on the input signal can be attenuated.

In addition, the sampling period of this digital filter changes according to the system frequency by the synchronization signal Sp, so
The filter characteristics (cutoff layer wavenumber) also change accordingly.

Next, the DSP shown in FIG. 1F will be explained in detail.

FIG. 4 shows a detailed diagram of the DSP. As shown in the figure, an address register 4a for specifying addresses of external memory, a data register 4b used as a parallel port, a data RAM 4c, and an m-bit x m-bit high-speed parallel multiplier 4.
d, ROM4e for instructions, ALU (Arithmetic Logic Unit) that performs addition and subtraction, etc.
) 4f, a control circuit 4h that controls registers 4g such as accumulators, interrupts of control signals (a, b, C, etc.) with the outside, and an internal bus 4j in the DSP.
It is composed of:

The multiplier 4d multiplies the contents of the input signals A and H during the instruction cycle, and sends the result C to the internal bus 4.
1. As is well known, DSPs are capable of performing multiply-accumulate operations within one instruction cycle and are capable of pipeline processing, making it possible to perform high-speed numerical operations on fixed and floating point data. It is characterized by This allows input data related to multiple input points to be filtered in real time. This processor for Ezawa cannot be applied because its processing speed is slow.

Next, the digital filter will be explained in detail.

FIG. 5 shows a typical block conceptual configuration of a digital filter. Figure 5 (a) shows the IIR type (Infini type).
te-extent Impulse Re5pons
e) Filter, (b) is FIR type (Finite ex
tent ImpulseResponse) filter.

In the same figure (,), Xi is an input signal code 5a is each coefficient block, K is a gain coefficient, AlpA2. B1 and B2 are filter coefficients. Reference numeral 5b is a delay block, which is a block (Wn-,) that delays the signal W by 2 times in the same way as a block (Wn-,) that delays the signal W by 1 time of period T.
, 2). Reference numeral 5c is an addition block, and Yn is filter output data. As can be seen from the figure, in the configuration shown in the figure, by adjusting the filter coefficients, the following equation (5) can be obtained.
, (6).

Various filters shown in (7), (8), and (9) can be realized.

Note that H(z) is a transfer function.

The figure can be expressed as an arithmetic expression as follows.

Wn=K −Xn+B, −W,, 10B z ・Wn−2
-(3) Yn=Wrl+A・Wn−□+A2・W n
-2'...(4) Knigain coefficient A1. A2. B engineering, B2: Filter coefficient Bandpass filter) ... (6) (Bypass filter) ... (7) (Notch filter) Here, r=2・cos2πfa・T T : Sampling period fo : Stopping frequency (all-pass filter) Fig. 5(b) In, X'. is the input data Y I,
indicates output data. Code 5d is a delay block,
X″n-1 is a block delayed by one time as described above,
X I n-2 indicates a block delayed by two times. Reference numeral 5e represents a filter coefficient block, in which filter coefficients A', , A'□, and 82 are set.

Reference numeral 5f is an addition block. This figure can be expressed by the following equation (10).

Y', =A'o-X', +A'□-X'n-1+A''2
'X'n-11...(10) As described above, the input signal is filtered by a digital filter using a DSP, and the sampling period T is set based on a preset filter coefficient.
Since this process is repeated for each input point, filter processing can be performed by software in a time-sharing manner according to the number of input points, making it possible to respond to increases and decreases in the number of human input points, changes in characteristics, and standardization of printed circuit boards. It is possible.

In addition, since filter processing can be performed without using an analog filter, the initial value deviation of the element described above.

There are no factors such as fluctuations in element values due to ambient temperature or element deterioration due to aging, and high accuracy and no adjustment can be achieved.

In addition, since an external inspection circuit is not required and can be handled by internal software, the manufacturing process can be significantly shortened, maintenance is not required, and there are significant benefits such as higher accuracy and lower cost of the protective relay device. big.

As described above, the effects of digitizing the input filter are very large.

Furthermore, digital filters also have the following features. This will be explained using a bandpass filter as an example.

The center frequency f0 of the bandpass filter can be expressed by the following equation.

B, B2...Filter coefficient T...Sampling period, that is, as is clear from equation (11), the center frequency f is equal to the frequency of the external synchronization signal Sp mentioned earlier (fs=1
/T) can be easily understood.

Therefore, by changing the external synchronization signal Sp according to the system frequency of the power system, the system frequency can always be the center frequency of the bandpass filter due to the characteristics of the filter. In other words, an adaptive digital filter can be constructed. (The filter coefficient is fixed.

) Next, a detailed explanation will be given using the drawings.

FIG. 6 shows an example of an input signal waveform and an example of gain characteristics of a bandpass filter.

First, in FIG. 6 (a), the input signal frequency is fo
The signal waveform and filter characteristics are shown in the case of . Due to the filter characteristics, the gain of the input signal frequency f0 is A.

In (b) and (c), the input signal frequency is f,'
Examples of input signal waveforms and filter characteristics are shown in the case of (<f,) and in the case of f,'(>f,).

As is clear from equation (11) and FIG. 6, even if the input signal frequency changes, the gain of the input signal frequency is A.

Next, another embodiment of the present invention will be described.

FIG. 7 is a block diagram of the timing control circuit shown at 1k in FIG. 1. 7a and 7b are counter 1 and counter 2, which are the same as those in FIG. 2, 2b and 2c.

Further, 7c is a decoding circuit, which is the same as that in FIG. 2 2d.

The difference between the circuit of FIG. 7 and the circuit of FIG. 2 is that the circuit of FIG. 7 does not have a single oscillation circuit, but controls the timing of taking in a signal serving as an original clock from the outside as a synchronization signal. That is, the external synchronization signal Sp' is a signal synchronized with the power grid, and has a higher frequency than the external synchronization signal Sp described above.

Therefore, in the circuit of FIG. 7, all control signals (all outputs) change in accordance with the external synchronization signal Sp'.

FIG. 8 shows an example of timing waveforms of the circuit shown in FIG. The function of each control signal is the same as the signal shown in FIG.

First, the period of the time synchronization signal Sp' is tsp.

Therefore, the sampling period is T as shown.

Next, the period of the synchronization signal Sp' at time t+1 is tsp
', which is shorter than tsp. Therefore, the sampling period becomes T', and the periods of each control signal are also uniformly shortened.

The advantage of this method is that since the original clock changes, the input data of all channels can be A/D converted at sampling intervals and digital filter processing can be performed.

Therefore, in this method as well, similarly to the circuit shown in FIG. 2, the sampling frequency is adjusted according to the power system frequency.
Since it can be changed, the frequency of the power system can always be matched to the center frequency of the digital filter.

Next, an applied example (digital arithmetic processing device) to which the present invention is applied will be described using FIG.

In FIG. 9, LA, IB, and IQ are the analog input unit, frequency detection/pulse generation unit, and system bus shown in FIG.

9a is a system control unit that performs data transfer management, bus arbitration, and interrupt control for the entire system. 9b is a man-machine interface unit for interfacing with the operation panel shown in 9c, and 9d is a digital I10 unit for performing calculation output and setting value (digital) input. 9e engineering ~ 9e+
is a digital arithmetic processing unit that performs arithmetic processing.

All units are connected to the system bus.

Next, the operation of the embodiment shown in FIG. 9 will be explained based on the flow diagram shown in FIG. In FIG. 10, (a) shows the processing flow of the input unit IA, and (b) shows the processing flow of the system control unit 9a.

The block 10a waits for an interrupt signal from the outside, and when an interrupt is generated by an external synchronization signal, the following predetermined processing is performed.

First, data subjected to unit A/D conversion in the block 10b is inputted, and digital filter coefficients are also inputted. In block 10c, digital filter calculations as shown in equations (3) and (4) are performed. The block 10d performs calculations to detect voltage values.

Next, the number of calculations (that is, whether n samples have been processed) of the digital filter in the block 10e is compared, and if the predetermined number of calculations is not reached, the processing starting from the interrupt wait in block 10a is performed again. If the predetermined number of operations is exceeded, l
Proceed to the block of, output the calculated data, and then
og block and outputs an interrupt request to the system control unit. That is, here, from the digital filter calculation cycle by the analog input unit to the data transfer cycle by the system control and 9
Synchronization is achieved by thinning out and transferring data at the cycle in which the calculation units e1 to 98 perform calculations.

Therefore, the calculation cycle of the system control unit is synchronized with the external synchronization signal Sp.

Next, 10h is the analog input unit I in the block.
It receives the interrupt from A and performs the following predetermined processing.

In the 10i block, the slave unit group (LA, I
B, 9b, 9d, 9e, ~9eM).

Specifically, the voltage value detected in the block 10d, 9
Setting value from b, digital input value from 9d, 9e□
~9eM of calculation output data are input, respectively.

In block 10j, data is transferred to the slave unit group except IA and IB.

Specifically, the detected voltage value from IA, the setting value from 9b, and the digital input data from 9d are sent to 9e1 to 9.
Transfer to the e2 arithmetic unit.

The calculation units 9e□ to 9e2 perform protection/control calculations based on a predetermined calculation algorithm.

Further, the calculation outputs of 9e-9es are transferred to the block 9d. Block 9d uses the above calculation data,
Various control signals are output according to the intended sequence processing.

In block 10, the slave unit group (9cl,
9e to 9eM), an interrupt signal is sent to start the operation. Since each slave starts its operation in response to this signal, synchronization can be achieved.

FIG. 11 is a diagram for explaining voltage detection. 1st
In Figure 1, (a) shows that the input signal frequency of amplitude A is f
An example of the waveform in case o is shown. As shown in the figure, there are 16 sampling signals in the half period (positive wave) Ta of the input Vln, and the period of this sampling signal is Tac.

Therefore, the voltage of the sampled data is detected using the following arithmetic expression, and the value α is calculated.

In (b), the frequency of the input signal is f. ′ and the amplitude is A
This is an example waveform in the case of .

The period of the input signal V i 11' is the signal V , n in (a)
As shown in Figure 1, there is also a sampling signal of lb around half the input V l n'' (positive wave) Tb, although it is shorter than 1. Therefore, the voltage detection value obtained by the above equation (12) is α
, which is the same as the value shown in (a). That is, this means that the voltage value (absolute value) can be detected accurately regardless of the input frequency.

As an actual application example of the present invention, the above voltage value (absolute value) is first determined, and then the difference ΔV with respect to a predetermined value is determined. By controlling this ΔV so that it falls within a certain allowable value range, a power system control device can be constructed. According to the present invention, there is an advantage that the voltage amount corresponding to the input can be faithfully derived using the same algorithm.

Next, another applied example of the present invention will be described. In the embodiments described so far, it was explained earlier that an external synchronization signal is input.Next, an abnormality detection method will be described when the synchronization signal is not input due to some abnormality. In addition.

The circuit configuration uses FIGS. 1 and 2.

FIG. 12 is an example of timing waveforms for explaining the operation of this applied example.

First, in FIG. 12, (a) is an example of timing waveforms during normal operation. That is, the synchronization signal from the outside shown in (1) has a period of 1/fs (fs: frequency) as shown in FIG.
timing control circuit (see Figure 2 2b and 2c for details)
(clear terminals of counters 1 and 2). In synchronization with this synchronization signal, the timing control circuit of (2)
) to (4) are sent out. Therefore, as shown in (5), the DSP processing is performed at the sampling period (1/fs
) shall be used to perform digital filter calculations. 1st
FIG. 3(a) shows an example of filter characteristics at this time. Here, the characteristics of the filter are set in advance so that zero points occur at frequencies twice, three times, and four times the frequency f0 of the fundamental wave.

Next, FIG. 12(b) shows a timing waveform when the external synchronization signal is not sent to the timing control circuit due to some abnormality, as shown in FIG. 12(1). As shown in (b), if no synchronization signal is input from the outside, counters 1 and 2 shown in FIG.
The counter output is sent to the decoder of d. Naturally,
As shown in FIG. 12(b), the period of each control signal is longer than that in FIG. 12(a). ((b) is a case where the length is twice that of (a).) Therefore, the filter characteristics are as shown in Fig. 13(b), and the fundamental wave f, which is the system frequency of the power system, is The frequency becomes zero and one point, and the gain becomes zero.

By monitoring the ratio between the magnitude of the filter output and the input signal, abnormalities in the synchronization circuit can be determined accurately and quickly, and malfunctions of the entire system can be prevented.

Since the ratio of the output to the input signal is constant regardless of the magnitude of the input signal, it is sufficient to monitor this value.

Furthermore, the above-described embodiment can be further applied to provide the following backup function.

That is, it can be realized by combining filter calculation processing and voltage detection means based on an external synchronization signal and filter calculation processing and voltage detection means according to a sampling signal generated within a period longer than the synchronization signal. In the latter method, since the sampling frequency is fixed, digital filter coefficients and voltage detection means (including frequency correction calculations) are provided in accordance with the sampling frequency. The former method has been explained in detail that the former method is better in terms of calculation accuracy, etc., but even if the accuracy deteriorates to some extent, the function of the entire system does not stop and it has the advantage of being able to operate stably.

Specifically, this will be explained based on the flow diagram shown in FIG.

First, the block 14a is enabled to accept interrupts, and when an interrupt signal is input, data is input. 14
In the block b, a filter operation corresponding to sampling using an external synchronization signal (sampling frequency is variable) is performed, and a voltage detection operation is also performed. Next, in the block 14c, the magnitude of the detected voltage is determined, and if it is not O (that is, an external synchronization signal is input) 14d
Proceed to block , determine the number of samples computed, and
If so, the process advances to block 14g and sends an interrupt signal to the data output and system control unit.

If the voltage is O in block 14c (that is, no external synchronization signal is input), proceed to block 14e, which corresponds to sampling by the internal oscillation signal (sampling frequency is fixed), first detects the frequency, performs filter calculation, and calculates the voltage. Perform detection calculation. This filter operation and voltage detection operation are different from the block 14b, and of course the filter coefficients are involved.

The voltage detection calculation algorithm is also different.

This voltage detection calculation algorithm also includes frequency detection and frequency correction calculations, as in the prior art.

Next, the process advances to block 14f, where the number of samples that have been calculated is determined, and when the calculation has been performed m times, the process proceeds to block 14g, where the calculated data is output and an interrupt signal is sent.

In this way, by having a backup function, the stability and reliability of the system can be greatly improved. Moreover, since it can be supported by any software, it goes without saying that it can be realized without increasing the hardware scale.

Further, it is also possible to easily deal with this by allocating the input state of the external synchronization signal to a status register in the analog input unit, constantly determining this information, and switching the program.

In the present invention, an example has been described in which a digital signal processor is applied as the calculation means. It can also be applied to processors.

〔Effect of the invention〕

According to the present invention, (1) The characteristics of the digital filter can be changed according to the frequency fluctuation of the input signal, and the input signal can always be used as an example of passing through the filter, so the magnitude of the input signal can be adjusted with high precision. can be detected.

(2) High precision can be achieved and the entire system can be synchronized by sampling data at high speed and performing digital filter calculations at a cycle that is 17 n times the calculation cycle of the protection/control calculation unit.

(3) If the analog input unit has an oscillation section inside and external synchronization is not applied, the external synchronization signal generation section can be Anomalies can be detected and system reliability can be improved.

(4) Even when an external synchronization signal input signal is not input, the external synchronization signal sending unit has a backup function that uses the signal from the oscillation section inside the analog input unit to sample the input data and performs digital filter calculations. It can be operated without stopping the entire system.

Therefore, the practical advantages are very large.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of an embodiment of the present invention, FIG. 2 is a diagram of the timing control circuit example (1) in FIG. 1, and FIG. 3 is a timing waveform example of an embodiment of the present invention. 4 is a diagram showing an example of a block configuration of a DSP, FIG. 5 is a processing block diagram of a digital filter, FIG. 6 is a diagram showing an example of gain characteristics of a filter according to the present invention, and FIG. 7 is a diagram shown in FIG. 1. FIG. 8 is a diagram showing an example of timing waveforms of the timing control circuit of FIG. 7, FIG. 9 is a block configuration diagram of an application example of the present invention, and FIG. 10 is a diagram of a timing control circuit example (2) of the present invention. FIG. 11 is a processing flow diagram of an application example of the present invention, and FIG.
FIG. 2 is a diagram showing an example of a timing waveform for explaining another embodiment of the present invention, FIG. 13 is a diagram showing an example of filter characteristics for explaining another embodiment of the present invention, and FIG. FIG. 7 is a process flow diagram of another application implementation of the invention. Ne 1 (21 Bu 2 Rikigai Kido 101 Signal Sugar Mu Kunikyo 5121 (b) 5f ff No. 6 Fig.'87 Ward $lo Zusei) (Mu)'4 ++
Concave (kuIf-f. $+ 12th ward (a) +5) D5PMl 1 Yumikomi Z-giwa 11 Zu 11 included Takerotaku 1312] Gain (Ki) Gain f, t, s9 2jo
Purge - (b) Cumulative I4

Claims (1)

[Claims] 1. A plurality of arithmetic units that take in various state quantities of objects to be controlled and protected in the power system, perform digital arithmetic processing according to predetermined processing procedures and criteria, and protect and control the power system. In a device consisting of a sampling frequency, an A/
A digital arithmetic processing device equipped with an analog input unit capable of changing the D conversion period and the period of rehearsing calculations performed by the calculation means. 2. In claim 1, the gain characteristics of the digital filter calculated by the calculation means are changed according to the frequencies of the input various state quantities, and the amplitude values of the input various state quantities are faithfully obtained. A digital arithmetic processing device characterized by: 3. Based on the amplitude value obtained in claim 2, the calculation period of a predetermined calculation is changed according to the frequency of various input state quantities, and the electric quantity corresponding to the input is faithfully derived using the same algorithm. A digital arithmetic processing device featuring: 4. In claim 1, the analog input unit is operated in synchronization with an external synchronization signal, and the analog input unit sends an interrupt signal and output data to other units every n times the cycle. A digital arithmetic processing device characterized by synchronous processing. 5. In claim 1, the analog input unit is provided with synchronization signal generation means consisting of a sampling signal transmission means having a period m times that of the synchronization signal and an interrupt signal transmission means of the calculation means, and the gain characteristic of the digital filter is is set in advance so that the zero point is m times the frequency of the various state quantities, and if no external synchronization signal is sent, the filter characteristics are changed so that the gain of the fundamental frequency of the various state quantities becomes zero, and the A digital arithmetic processing device characterized by constantly detecting a ratio between state quantity data and its filter output. 6. Claim 5, further comprising auxiliary calculation means for performing calculations in the digital signal processor using a synchronization signal from the synchronization signal generation means in the analog input unit when the external synchronization signal is not sent out. A digital arithmetic processing unit.