JP7294895B2 - Control device - Google Patents

Description

The present invention relates to a control device for industrial machines and the like.

2. Description of the Related Art Conventionally, in a control device, as an index for determining appropriate control, there is a case where the state of operation is measured for each predetermined period, and further statistically processed and used (for example, see Patent Document 1).

JP-A-8-249041

By the way, regarding the operation of a control device, it is desired to measure a performance index in order to judge processing performance, debug an operation program, detect an abnormality in operation, or the like.
In addition, it is not enough for such a performance index to be based only on the state of the control device at a certain point in time, and it is desired that trends over a long period of time be output in a timely manner.

The control device, which is one aspect of the present disclosure, includes the required processing time for each control cycle, the number of occurrences of a specific interrupt for each control cycle, the number of single reads for each control cycle, the number of single writes for each control cycle, the number of single writes for each control cycle, burst read count per control cycle, burst write count per control cycle, read byte count per control cycle, write byte count per control cycle, bus idle time per control cycle, bus overlap time per control cycle, bus overlap time per control cycle a measurement unit that measures a performance index including at least one of a specified condition hit count, single read latency, single write latency, burst read latency, or burst write latency; and sequentially calculates an average value of the performance index a calculation unit;

According to one aspect, the long-term trend of the performance index in the control device is output in a timely manner.

1 is a diagram showing a first method of sequential mean value calculation according to the prior art; FIG. FIG. 10 is a diagram showing a second method of sequential mean value calculation according to the prior art; FIG. 4 is a block diagram showing the circuit configuration of a computing device for implementing a second method of sequential average value calculation according to the prior art; It is a block diagram which shows the whole structure of the mean value sequential calculation apparatus in this indication. It is a block diagram which shows the circuit structure of the average value sequential calculation apparatus in 1st Embodiment. It is a figure which shows the calculation method of the average value by the mean value sequential calculation apparatus in 1st Embodiment. FIG. 4 is a diagram illustrating output of a ceiling function in the first embodiment; FIG. FIG. 10 is a block diagram showing the circuit configuration of the average value sequential calculation device in the second embodiment; It is a figure which shows the calculation method of the average value by the average value sequential calculation apparatus in 2nd Embodiment. It is a graph which compares and shows an average value sequential calculation result. It is the graph which drew the initial stage of the mean value sequential calculation result. FIG. 11 is a block diagram showing the functional configuration of a control device in a third embodiment; FIG. It is a figure which illustrates the generation|occurence|production method of the control period signal in 4th Embodiment. FIG. 11 is a block diagram showing the functional configuration of a control device in a fourth embodiment; FIG.

In the present disclosure, first, a conventional average value calculation method will be described for comparison, and a configuration example and a calculation method of an average value sequential calculation device that is an embodiment will be shown. Furthermore, as an application example of the average value sequential calculation device, the case where the function to measure the performance index and the function to synchronize the control cycle signal with other control devices are implemented for the control device in industrial machinery etc. show.

FIG. 1 is a diagram showing a first method of sequential mean value calculation according to the prior art.
In the first method, using a constant α (0<α<1), for the n-th input value x _n , the output value y _n =α(x _n −y _n−1 )+y _n−1 is Sequentially output. The output value y _n is a weighted average value of x ₁ to x _n .
Here, when α=2 ^−N , since multiplication can be performed by shift operation, the computational load is reduced, but the convergence to the average value is slow.

FIG. 2 is a diagram showing a second method of sequential mean value calculation according to the prior art.
In the second method, using the number of inputs n of the time-series data and the upper limit value N, the output value _{y n =} (x _n −y _n−1 )/k+y _n for the n-th input value x n _-1 is output sequentially. The output value y _n is a value obtained by averaging k=min{N,n} input values.

FIG. 3 is a block diagram showing the circuit configuration of a computing device 100 for implementing the second method of sequential average value calculation according to the prior art.
Calculation device 100 includes divider 110, 1-cycle delay element 120, counter 130 that counts the number of inputs of time-series data (sample values), subtractor 140, and adder 150. and

A value (A) obtained by subtracting the output value of one cycle before from the input value x and the number of sample values input (B) are input to the divider 110 . Subsequently, the output value 1 cycle before is added to the division result A/B to obtain the output value y.
Note that the counter 130 may saturate the number of inputs (B) at a predetermined upper limit value N.

As described above, in the second method, the circuit size increases due to the division. Moreover, even if it is configured by software, the processing load associated with the division increases.
Therefore, the present disclosure proposes an average value sequential calculation device 1 that does not use multipliers and dividers by substituting shift operations for multiplication and division.

FIG. 4 is a block diagram showing the overall configuration of the average value sequential calculation device 1. As shown in FIG.
The average value sequential calculation device 1 includes a variable Infinite Impulse Response (IIR) low-pass filter 10 that outputs an average value of input values that are sequentially input, and a setting unit 15 that sets variable parameters of the low-pass filter 10 .

The setting unit 15 controls the cutoff frequency of the low-pass filter 10 by counting the number of times the sample value is input to the low-pass filter 10 and setting the number of bits for the shift operation based on the number of inputs.
Note that the number of inputs may be saturated at a predetermined value according to the upper limit of the number of bits that can be shifted.

The average value sequential calculation device 1 uses a multiplier/divider-free low-pass filter 10 in which multiplication and division are replaced by shift operations, thereby reducing the calculation load and calculating the average value of time-series data with a high-speed and small-scale electronic circuit. can be calculated sequentially.
Hereinafter, as specific configuration examples of the mean value sequential calculation device 1, a first embodiment and a second embodiment in which the configuration of the low-pass filter 10 is different will be described.

[First embodiment]
FIG. 5 is a block diagram showing the circuit configuration of the average value sequential calculation device 1a in the first embodiment.
The average value sequential calculation device 1a includes a low-pass filter 10a and a setting unit 15. FIG.

The low-pass filter 10a comprises a shifter 11 capable of performing an arithmetic right shift operation, a delay element 12 for obtaining an output value one cycle before, a subtractor 16 and an adder 17. FIG. The low-pass filter 10a adds the output value of one cycle before to the value obtained by subtracting the output value of one cycle before from the input value x, which is arithmetically right-shifted by the shifter 11 by the number of bits set by the setting unit 15. Let the value be the output value y.
The setting unit 15 sets the number of bits for the arithmetic right shift operation based on the logarithm (log ₂ n) of the number of inputs n.

FIG. 6 is a diagram showing an average value calculation method by the average value sequential calculation device 1a in the first embodiment.

The average value sequential calculation device 1a uses the number of times of input of time-series data n and the upper limit number of bits of shift operation _K to obtain an output value y _n = (x _n - y _n−1 )/2 ^k +y _n−1 are sequentially output. The output value y _n is a weighted average value corresponding to k=min{K, ceiling(log ₂ n)} for each of x ₁ to x _n .
Here, the function ceiling(p) is the smallest integer greater than or equal to p.

FIG. 7 is a diagram exemplifying the output of the ceiling function in the first embodiment.
In the counter of the number of times of input immediately before _xn is input, the number of the most significant bit whose value is 1 is output as the function value. If there is no bit whose value is 1 in the input count counter, 0 is output as the function value.
For example, if the 5th bit from the bottom of the immediately preceding counter is 1 and there is no 1 in the bits above it, ceiling (log ₂ n)=5 regardless of the values of the 1st to 4th bits. Also, in the case of the first input (n=1), the value of the immediately preceding input counter is 0 and there is no bit with a value of 1, so ceiling(log ₂ n)=0.

[Second embodiment]
FIG. 8 is a block diagram showing the circuit configuration of the mean value sequential calculation device 1b in the second embodiment.
The mean value sequential calculation device 1 b includes a low-pass filter 10 b and a setting section 15 .

As in the first embodiment, the low-pass filter 10b includes a shifter 11 (first shifter) capable of performing an arithmetic right shift operation, a delay element 12 for obtaining an output value one cycle before, an adder/subtractor 18, an adder 17, a shifter 13 (second shifter) capable of performing an arithmetic left shift operation, and a delay element 14 for obtaining an input value one cycle before.

The low-pass filter 10b adds the input value of one cycle before to the input value x, and subtracts the output value of one cycle before by 1-bit arithmetic left shift (double) by the shifter 13, Let the output value y be the value obtained by adding the output value one cycle before to the value arithmetically right-shifted by the shifter 11 by the number of bits set by . Here, if the input value x is non-negative (unsigned number), the output value y can also be regarded as non-negative (unsigned number), so arithmetic left shift can be logical left shift.
The setting unit 15 sets the number of bits for arithmetic right shift operation by the shifter 11 based on the logarithm (log ₂ n) of the number of inputs n.

FIG. 9 is a diagram showing an average value calculation method by the average value sequential calculation device 1b in the second embodiment.

The mean value sequential calculation device 1b uses the number of times of input of time-series data n and the upper limit number of bits of shift operation _K to obtain an output value y _n = (x _n + x _{n −1} −2y _n−1 )/2 ^k +y _n−1 are sequentially output. The output value y _n is a weighted average value corresponding to k=min{K, ceiling(log ₂ n)} for each of x ₁ to x _n .

FIG. 10 compares the average value sequential calculation results when using the first method and second method according to the prior art, and the calculation method of the first embodiment and the calculation method of the second embodiment. It is a graph showing.

For high-frequency input waveforms, the first method according to the prior art takes a long time to converge to the average value, but the second method according to the prior art takes a short time to reach the average value. converged and the input waveform is smoothed.
On the other hand, according to the calculation methods of the first and second embodiments, calculation results equivalent to those of the second method according to the prior art are obtained, and in the figure, the second method according to the prior art overlaps with is drawn.

FIG. 11 is a graph showing the initial stage of the result of sequential average value calculation by enlarging the time axis in the graph of FIG.
The calculation results of the first and second embodiments quickly converge to the average value from the initial stage, and results equivalent to those of the second method according to the prior art are obtained.

According to the first embodiment or the second embodiment, for example, the following effects (A1) to (A3) are obtained.

(A1) The average value sequential calculation device 1 replaces multiplication and division with a shift operation, and counts the number of inputs to the variable IIR low-pass filter 10 that outputs the average value of the input values that are sequentially input, and the low-pass filter 10, and a setting unit 15 that controls the cutoff frequency of the low-pass filter 10 by setting the number of bits of the shift operation based on the number of inputs.

As a result, the average value sequential calculation device 1 (1a or 1b) uses a multiplier/divider-free low-pass filter 10 (10a or 10b) in which multiplication and division are substituted by shift operations, thereby reducing the calculation load and increasing the speed. In addition, it is possible to sequentially calculate the average value of time-series data with a small-scale electronic circuit.

(A2) In the average value sequential calculation device 1 described in (A1), the low-pass filter 10 includes a shifter 11 capable of executing an arithmetic right shift operation, and subtracts the output value of one cycle before from the input value, The value obtained by adding the output value of one cycle before to the value arithmetically right-shifted by the shifter 11 by the number of bits set by the setting unit 15 is used as the output value, and the setting unit 15 arithmetically right-shifts based on the logarithm of the number of inputs. You may set the bit number of the operation.

As a result, the mean value sequential calculation device 1a substitutes the shifter 11 for division and controls the number of bits of the shift calculation based on the logarithm of the number of sample values input, thereby reducing the load for calculating the mean value and increasing the speed. Moreover, a small-scale electronic circuit can be realized.

(A3) In the average value sequential calculation device 1 described in (A1), the low-pass filter 10 includes a shifter 11 capable of executing an arithmetic right shift operation and a shifter 13 capable of executing an arithmetic left shift operation, and the input value is added with the input value one cycle before, and the value obtained by subtracting the value obtained by shifting the output value one cycle before to the left by one bit by the shifter 13 is arithmetically shifted right by the shifter 11 by the number of bits set by the setting unit 15. The setting unit 15 may set the number of bits for the arithmetic right shift operation based on the logarithm of the number of inputs, with the value obtained by adding the output value of one cycle before to the value obtained by adding the output value.

As a result, the average value sequential calculation device 1b substitutes the shifter 11 for division and the shifter 13 for multiplication, respectively, and controls the number of bits of the right shift operation based on the logarithm of the number of times the sample value is input, thereby obtaining the average value can reduce the computational load of the circuit and realize a high-speed and small-scale electronic circuit.
Note that the shift operation by the shifter 13 may be an arithmetic left shift, but is not limited to this. If the input value is non-negative (unsigned number), the output value can be regarded as non-negative (unsigned number), so the shift operation by the shifter 13 can be a logical left shift.

(A4) In the average value sequential calculation device described in (A2) or (A3), the arithmetic right shift operation has a predetermined maximum number of bits as an upper limit, and the setting unit 15 selects either the logarithm of the number of inputs or the maximum number of bits. or the lesser may be set as the number of bits for the arithmetic right shift operation.

As a result, the mean value sequential calculation device 1 (1a or 1b) can realize a small-scale electronic circuit with a limited circuit scale for the shift operation by limiting the cutoff frequency of the low-pass filter 10 within a range necessary for operation. .

Next, a third embodiment and a fourth embodiment will be described as examples in which the mean value sequential calculation device 1 (1a or 1b) is applied to a control device for industrial machinery.

[Third embodiment]
The control device 2 of the third embodiment measures and outputs a performance index for determining processing performance, debugging an operation program, detecting an abnormality in operation, or the like.

FIG. 12 is a block diagram showing the functional configuration of the control device 2 according to the third embodiment.
The control device 2 includes a measurement unit 21 that measures performance indexes and a calculation unit 22 that sequentially calculates average values of the performance indexes.

The measurement unit 21 measures at least one of the following performance indicators.
・Required processing time for each predetermined control cycle ・Number of occurrences of specific interrupts for each predetermined control cycle ・Number of single reads for each predetermined control cycle ・Number of single writes for each predetermined control cycle ・For each predetermined control cycle Burst read count ・Burst write count per predetermined control cycle ・Read byte count per predetermined control cycle ・Write byte count per predetermined control cycle ・Bus idle time per predetermined control cycle ・Per predetermined control cycle bus overlap time ・The number of times a specified condition is hit for each predetermined control cycle ・Single read latency ・Single write latency ・Burst read latency ・Burst write latency

Here, the bus idle time is the number of clock cycles in which the outstanding number (the number of incomplete transactions) of the bus is zero. Also, the bus overlap time is the count of the number of clock cycles in which the number of outstandings of the bus is 2 or more. Instead of these, the measurement unit 21 measures the number of clock cycles in which the number of outstanding busses is 1, the number of clock cycles in which the number of outstanding busses is 2, and the number of clock cycles in which the number of outstanding busses is 3 or more. It may be configured to measure the number of clock cycles or the like in the state of .
Single read and single write latencies may also be measured by filtering by access size or access destination address. For example, 1-byte access, 2-byte access, 4-byte access, and 8-byte access may be separately measured. Burst read and burst write latencies may be measured by filtering by burst length or access destination address. For example, latency measurements may be limited to bus transactions of maximum burst length.

The control device 2 may have a plurality of measurement points for the performance index. For example, there are measurement points for the above performance index at the master and slave ports of the bus of each CPU in the control device 2, the master and slave ports of the bus bridge, the master port of the DMA controller, the slave port of the memory controller, etc. good.

The calculation unit 22 sequentially calculates the minimum value, the maximum value, and the average value of the performance index measured by the measurement unit 21 .
Here, the calculation unit 22 may be configured including the mean value sequential calculation device 1 (1a or 1b) of the first embodiment or the second embodiment described above. That is, the calculation unit 22 is provided with a variable IIR low-pass filter 10 (10a or 10b) that substitutes a shift operation for multiplication and division and outputs an average value of sequentially input performance indices. Further, the calculation unit 22 includes a setting unit 15 that counts the number of inputs to the low-pass filter 10 and sets the number of bits for shift calculation based on the number of inputs, thereby controlling the cut-off frequency of the low-pass filter.

Note that the calculation unit 22 may be configured as a part of the control device 2, or may be an external information processing device connected to the control device 2 for communication.

According to the third embodiment, for example, the following effects (B1) to (B2) are obtained.

(B1) The control device 2 determines the required processing time for each control cycle, the number of occurrences of specific interrupts for each control cycle, the number of single reads for each control cycle, the number of single writes for each control cycle, and the burst read for each control cycle. number of times, number of burst writes per control cycle, number of read bytes per control cycle, number of write bytes per control cycle, bus idle time per control cycle, bus overlap time per control cycle, specified condition hit per control cycle A measuring unit 21 that measures a performance index including at least one of the number of times, single read latency, single write latency, burst read latency, or burst write latency, and a calculation unit 22 that sequentially calculates the average value of the performance index. And prepare.

As a result, the control device 2 sequentially outputs an average value as a long-term trend of the performance index measured in each control cycle, and uses it to determine the processing performance, debug the operation program, or detect an abnormality in operation. can be provided in a timely manner.

(B2) In the control device 2 described in (B1), the calculation unit 22 replaces the multiplication and division with a shift operation, and includes the variable IIR low-pass filter 10 that outputs the average value of the performance indices that are sequentially input, and the low-pass filter 10 and a setting unit 15 that controls the cutoff frequency of the low-pass filter 10 by counting the number of inputs to and setting the number of bits for the shift operation based on the number of inputs.

As a result, the control device 2 can realize high-speed average value sequential calculation with a small circuit scale, and can easily provide the average value of the performance index.

[Fourth Embodiment]
In the fourth embodiment, a plurality of control devices 3 are connected to each other via communication channels, and each control device 3 generates a control cycle signal that is time-synchronized.

FIG. 13 is a diagram illustrating a method of generating a control period signal in the fourth embodiment.
The plurality of control devices 3 perform time synchronization between the master and the slaves using Precision Time Protocol (PTP) of a local area network (LAN) or Precision Time Measurement (PTM) of PCI Express.

Each synchronized control device 3 generates a Pulse Per Second (PPS) signal and generates an Interpolation Timing Pulse ( _{ITP) signal indicating a control period T_ITP that} is m/M times the period T_PPS of the PPS signal.
That is, the time ITP _kM+m of the kM+mth ITP signal is defined as follows based on the times PPS k and PPS _k + ₁ of the kth and k+1th PPS signals.
ITP _kM+m =PPS _k+1 +(PPS _k+1 −PPS _k )·m/M
(m = 0, 1, ..., M-1)

FIG. 14 is a block diagram showing the functional configuration of the control device 3 in the fourth embodiment.
The control device 3 includes a synchronization section 31, a PPS signal generation section 32, a period measurement device 33 (measurement section), a jitter removal filter 34 (calculation section), and an ITP signal generation section 35 (control period signal generation section). Prepare.

The synchronization unit 31 synchronizes the built-in clock of the control device 3 with the master control device 3 via the communication path.
The PPS signal generator 32 generates a PPS signal based on the synchronized internal clock.
Note that the synchronization unit 31 and the PPS signal generation unit 32 may be a communication controller capable of time synchronization, such as a PTP-compatible Ethernet (registered trademark) controller or a PTM-compatible PCI Express core.

The period measuring device 33 measures the period of the PPS signal, that is, the time between pulses (number of clock cycles) using a reference clock with a frequency sufficiently faster than that of the PPS signal.
At this time, the period measuring device 33 may output a value obtained by multiplying the measurement result by a predetermined value (N times).

The jitter removal filter 34 removes the jitter of the PPS signal, that is, the period fluctuation, by successively calculating the average value of the periods measured by the period measuring device 33 .
Here, the jitter removal filter 34 may be configured including the mean value sequential calculation device 1 (1a or 1b) of the first embodiment or the second embodiment. That is, the jitter removal filter 34 substitutes multiplication and division with a shift operation, counts the number of inputs to the variable IIR low-pass filter 10 that outputs the average value of the cycles that are sequentially input, and the low-pass filter 10, and and a setting unit 15 that controls the cutoff frequency of the low-pass filter 10 by setting the number of bits for the shift operation.

The ITP signal generator 35 multiplies the number of pulses of the PPS signal based on the average value of the period measured by the period measuring device 33 and smoothed by the jitter removal filter 34 to generate an ITP signal indicating the control period. .

Specifically, first, the multiplication number M is set by the multiplication number setting register 351, and the result obtained by dividing M00 . Input to accumulator 353 . In the L-bit accumulator 353, when the inputs are added by the number of PPS periods (the number of clock cycles), M overflows (carries) occur. As a result, the carry signal becomes the M multiplication of the PPS signal.
The incrementer 354 counts this carry signal, and the counted number is compared with M by the comparator 355 . After counting M times, the count is reset. The ITP signal generator 35 outputs the PPS signal when the count number is 0, and outputs the carry signal as the ITP signal when the count number is other than 0.

Although the case where the ITP signal is generated by multiplying the PPS signal by M is shown here, the period of the ITP signal is not limited to this. For example, when the period measuring device 33 outputs N times the period of the PPS signal, the ITP signal generator 35 generates pulses by dividing the N times the period by M. Therefore, an ITP signal obtained by multiplying the PPS signal by M/N is output.

According to the fourth embodiment, for example, the following effects (C1) to (C4) are obtained.

(C1) A plurality of control devices 3 are connected to each other via a communication path, and each control device 3 has a synchronization unit 31 for synchronizing an internal clock via a communication path, and a PPS signal based on the internal clock. a PPS signal generator 32 for generating a PPS signal, a period measuring device 33 for measuring the period of the PPS signal, and an ITP signal generating unit 35 for generating an ITP signal indicating the control period based on the period measured by the period measuring device 33; , provided.

Thereby, the control device 3 can appropriately generate the ITP signal whose phase is matched with the PPS signal by measuring the period of the time-synchronized PPS signal. As a result, the control cycles of the plurality of control devices 3 can be synchronized.
At this time, the control device 3 does not need to know the cycle of the PPS signal in advance, and the synchronization of the ITP signals among the plurality of control devices 3 is completed when the generation of the ITP signal is started after measuring the cycle.

(C2) In the control device 3 described in (C1), the period measuring device 33 may output a value obtained by multiplying the measured period by a predetermined value.

As a result, since the control device 3 generates M-divided pulses after multiplying the period of the PPS signal by N, it is possible to output the ITP signal obtained by multiplying the PPS signal by M/N.

(C3) The control device 3 described in (C1) or (C2) includes a jitter removal filter 34 that sequentially calculates the average value of the periods measured by the period measuring device 33, and the ITP signal generator 35 calculates the average value An ITP signal may be generated based on .

This allows the controller 3 to smooth the period measurement results and reduce the effects of jitter present in the PPS signal. As a result, fluctuations in the period of the ITP signal can be reduced. Further, the control device 3 can cause the ITP signal to follow even if the PPS period varies gently.

(C4) In the control device 3 described in (C3), the jitter removal filter 34 replaces multiplication and division with a shift operation, and includes the variable IIR low-pass filter 10 that outputs the average value of the cycles that are sequentially input, and the low-pass filter 10 and a setting unit 15 that controls the cutoff frequency of the low-pass filter 10 by counting the number of inputs to and setting the number of bits for the shift operation based on the number of inputs.

As a result, the control device 3 can realize high-speed average value sequential calculation with a small circuit scale, and can easily provide the average value of the period of the PPS signal.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments. For example, although the first-order variable IIR low-pass filter is used in the first embodiment and the second embodiment, a second-order or higher-order variable IIR low-pass filter may be used. For example, an N-order variable IIR low-pass filter may be realized by cascade connecting N first-order variable IIR low-pass filters. Moreover, the effects described in the present embodiment are merely enumerations of the most suitable effects resulting from the present invention, and the effects of the present invention are not limited to those described in the present embodiment.

The mean value sequential calculation method by the mean value sequential calculation device 1 is implemented by software. When realized by software, the programs that make up this software are installed on the computer. These programs may be recorded on removable media and distributed to users, or may be distributed by being downloaded to users' computers via a network.

Reference Signs List 1, 1a, 1b average value sequential calculation device 2 control device 3 control device 10, 10a, 10b low-pass filter 11 shifter (first shifter)
13 shifter (second shifter)
15 setting unit 21 measurement unit 22 calculation unit 31 synchronization unit 32 PPS signal generation unit 33 period measurement device (measurement unit)
34 Jitter removal filter (calculation part)
35 ITP signal generator (control cycle signal generator)

Claims (1)

Required processing time for each control cycle,
the number of occurrences of a specific interrupt per control cycle,
number of single reads per control cycle,
number of single writes per control cycle,
number of burst reads per control cycle,
number of burst writes per control cycle,
number of read bytes per control cycle,
number of write bytes per control cycle,
Bus idle time per control cycle,
bus overlap time for each control cycle,
Specified condition hit count per control cycle,
single read latency,
single write latency,
a measurement unit that measures a performance index including at least one of burst read latency and burst write latency;
a calculation unit that sequentially calculates the average value of the performance index ,
The calculation unit
a variable Infinite Impulse Response (IIR) low-pass filter that substitutes shift operations for multiplication and division and outputs an average value of the performance indicators that are sequentially input;
and a setting unit that counts the number of inputs to the low-pass filter and sets the number of bits for the shift operation based on the number of inputs, thereby controlling the cut-off frequency of the low-pass filter.

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