JP7401198B2 - Average value sequential calculation device - Google Patents

Description

The present invention relates to an apparatus for calculating an average value of time series data.

Conventionally, when smoothing time series data, it may be necessary to sequentially calculate long-term average values instead of short-term moving averages.
For example, Patent Document 1 proposes a technique for averaging observed values using a low-pass filter.

Japanese Patent Application Publication No. 2007-147554

It is generally known that when multiplication and division, and especially division, are implemented using software, the calculation time is long, and when implemented using hardware, the circuit scale becomes large.
Averaging methods that do not use multiplication and division have been proposed depending on the conditions, but it takes too much time to converge to the average value. In addition, the averaging method that converges quickly requires division, which increases the computational load.
Therefore, there is a need for a device that can realize sequential calculation of average values of time-series data using a high-speed and small-scale electronic circuit.

An average value sequential calculation device that is an aspect of the present disclosure includes a variable infinite impulse response (IIR) low-pass filter that substitutes a shift operation for multiplication and division and outputs an average value of input values that are sequentially input, and a variable infinite impulse response (IIR) low-pass filter that outputs an average value of input values that are input sequentially; and a setting unit that controls the cutoff frequency of the low-pass filter by counting the number of inputs and setting the number of bits of the shift operation based on the number of inputs.

According to one aspect, sequential calculation of average values of time-series data is realized using a high-speed and small-scale electronic circuit.

FIG. 2 is a diagram illustrating a first method of sequential average value calculation according to the prior art. FIG. 7 is a diagram illustrating a second method of sequential average value calculation according to the prior art. FIG. 2 is a block diagram showing a circuit configuration of a calculation device for implementing a second method of sequential calculation of average values according to the prior art. FIG. 1 is a block diagram showing the overall configuration of an average value sequential calculation device according to the present disclosure. FIG. 2 is a block diagram showing the circuit configuration of the average value sequential calculation device in the first embodiment. It is a figure showing the calculation method of the average value by the average value sequential calculation device in a 1st embodiment. It is a figure which illustrates the output of the ceiling function in 1st Embodiment. FIG. 2 is a block diagram showing a circuit configuration of an average value sequential calculation device in a second embodiment. It is a figure which shows the calculation method of the average value by the average value sequential calculation apparatus in 2nd Embodiment. It is a graph which compares and shows the average value sequential calculation result. This is a graph depicting the initial stage of the average value sequential calculation results. It is a block diagram showing the functional composition of a control device in a 3rd embodiment. FIG. 7 is a diagram illustrating a method of generating a control period signal in a fourth embodiment. It is a block diagram showing the functional composition of a control device in a 4th embodiment.

In the present disclosure, first, a conventional average value calculation method will be described for comparison, and a configuration example and calculation method of an average value sequential calculation device according to an embodiment will be shown. Furthermore, as an application example of the average value sequential calculation device, we will consider a case where a function for measuring performance indicators and a function for synchronizing control period signals with other control devices are implemented in a control device for industrial machinery, etc. show.

FIG. 1 is a diagram showing a first method of sequential average value calculation according to the prior art.
In the first method, using a constant α (0<α<1), for the nth input value x _n , the output value y _n =α (x _n -y _n-1 )+y _n-1 is Output sequentially. The output value y _n is a weighted average value of each of x ₁ to x _n .
Here, in the case of α=2 ^−N , multiplication can be performed by a shift operation, so the calculation load is reduced, but convergence to the average value is slow.

FIG. 2 is a diagram illustrating a second method of sequential average value calculation according to the prior art.
In the second method, the output value y _{n =} (x _n -y _n-1 )/k+y _{n -1} is output sequentially. The output value y _n is the average value of k=min {N, n} input values.

FIG. 3 is a block diagram showing a circuit configuration of a calculation device 100 for implementing the second method of sequential calculation of average values according to the prior art.
The calculation device 100 includes a divider 110, a one-cycle delay element 120, a counter 130 that counts the number of inputs of time series data (sample values), a subtracter 140, and an adder 150. Equipped with.

A value (A) obtained by subtracting the output value one cycle before from the input value x and the number of inputs of the sample value (B) are input to the divider 110. Subsequently, the output value of one cycle before is added to the division result A/B to obtain the output value y.
Note that the counter 130 may saturate the number of inputs (B) at a predetermined upper limit value N.

In this way, in the second method, the circuit scale increases due to division. Further, even if it is configured by software, the processing load associated with division will be large.
Therefore, the present disclosure proposes an average value sequential calculation device 1 that does not use multipliers and dividers by substituting shift operations for multiplication and division.

FIG. 4 is a block diagram showing the overall configuration of the average value sequential calculation device 1. As shown in FIG.
The average value sequential calculation device 1 includes a variable infinite impulse response (IIR) low-pass filter 10 that outputs an average value of input values that are sequentially input, and a setting unit 15 that sets variable parameters of the low-pass filter 10.

The setting unit 15 controls the cutoff frequency of the low-pass filter 10 by counting the number of inputs of sample values to the low-pass filter 10 and setting the number of bits for shift calculation based on this number of inputs.
Note that the number of inputs may be saturated at a predetermined value depending on the upper limit of the number of bits that can be shifted.

The average value sequential calculation device 1 reduces the calculation load by using a multiplier-free low-pass filter 10 in which multiplication and division are replaced by shift operations, and calculates the average value of time-series data using a high-speed and small-scale electronic circuit. can be calculated sequentially.
Hereinafter, as specific configuration examples of the average value sequential calculation device 1, a first embodiment and a second embodiment in which the configurations of the low-pass filter 10 are different will be shown.

[First embodiment]
FIG. 5 is a block diagram showing the circuit configuration of the average value sequential calculation device 1a in the first embodiment.
The average value sequential calculation device 1a includes a low-pass filter 10a and a setting section 15.

The low-pass filter 10a includes a shifter 11 capable of performing an arithmetic right shift operation, a delay element 12 for obtaining an output value of one cycle before, a subtracter 16, and an adder 17. The low-pass filter 10a adds the output value of one cycle to the value obtained by subtracting the output value of one cycle before from the input value x, which is arithmetic shifted to the right by the shifter 11 by the number of bits set by the setting unit 15. Let the value be the output value y.
The setting unit 15 sets the number of bits for the arithmetic right shift operation based on the logarithm (log ₂ n) of the number of inputs n.

FIG. 6 is a diagram showing a method for calculating an average value by the average value sequential calculation device 1a in the first embodiment.

The average value sequential calculation device 1a calculates the output value y _n =(x _{n -} y _n-1 )/2 ^k +y _n-1 are output sequentially. The output value y _n is a weighted average value for each of x ₁ to x _n according to k=min{K, ceiling (log ₂ n)}.
Here, the function ceiling(p) is the smallest integer greater than or equal to p.

FIG. 7 is a diagram illustrating the output of the ceiling function in the first embodiment.
In the counter for the number of inputs immediately before x _n is input, the number of the most significant bit having a value of 1 is output as a function value. If there is no bit with a value of 1 in the input count counter, 0 is output as the function value.
For example, if the fifth bit from the bottom of the immediately preceding counter is 1 and the bits above it are not 1, ceiling (log ₂ n)=5, regardless of the values of the 1st to 4th bits. Furthermore, in the case of the first input (n=1), the value of the previous input count counter is 0, and there is no bit with a value of 1, so ceiling(log ₂ n)=0.

[Second embodiment]
FIG. 8 is a block diagram showing the circuit configuration of the average value sequential calculation device 1b in the second embodiment.
The average value sequential calculation device 1b includes a low-pass filter 10b and a setting section 15.

Similar to the first embodiment, the low-pass filter 10b includes a shifter 11 (first shifter) capable of performing an arithmetic right shift operation, a delay element 12 for obtaining an output value of one cycle before, and an adder/subtractor 18. It further includes a shifter 13 (second shifter) capable of executing an arithmetic left shift operation, and a delay element 14 for obtaining an input value one cycle before.

The low-pass filter 10b adds the input value of one cycle before to the input value x, and subtracts the value obtained by arithmetic left-shifting (doubling) the output value of one cycle by one bit using the shifter 13. The output value y is obtained by adding the output value of one cycle before to the value arithmetic right-shifted by the shifter 11 by the number of bits set by . Here, if the input value x is non-negative (unsigned number), the output value y can also be considered non-negative (unsigned number), so the arithmetic left shift may be a logical left shift.
The setting unit 15 sets the number of bits for the arithmetic right shift operation by the shifter 11 based on the logarithm (log ₂ n) of the number of inputs n.

FIG. 9 is a diagram showing a method for calculating an average value by the average value sequential calculation device 1b in the second embodiment.

The average value sequential calculation device 1b calculates the output value y _n =(x _{n +} x _{n -1} -2y _n-1 )/2 ^k +y _n-1 are output sequentially. The output value y _n is a weighted average value for each of x ₁ to x _n according to k=min{K, ceiling (log ₂ n)}.

FIG. 10 compares the average value sequential calculation results when using the first method and the second method according to the prior art, and the calculation method of the first embodiment and the calculation method of the second embodiment. This is a graph showing.

For high-frequency input waveforms, the first method based on the prior art takes a long time to converge to the average value, but the second method based on the prior art allows the calculation results to reach the average value in a short time. It has converged and the input waveform has been smoothed.
On the other hand, according to the calculation methods of the first embodiment and the second embodiment, calculation results equivalent to those of the second method according to the prior art are obtained, and in the figure, the calculation results overlap with the second method according to the prior art. It is drawn.

FIG. 11 is a graph in which the time axis in the graph of FIG. 10 is expanded to depict the initial stage of the average value sequential calculation results.
The calculation results of the first embodiment and the second embodiment quickly converge to the average value from the initial stage, and results equivalent to those of the second method according to the prior art are obtained.

According to the first embodiment or the second embodiment, for example, the following effects (A1) to (A3) can be obtained.

(A1) The average value sequential calculation device 1 includes a variable IIR low-pass filter 10 that substitutes multiplication and division with a shift operation and outputs the average value of input values that are sequentially input, and counts the number of inputs to the low-pass filter 10, A setting unit 15 is provided that controls the cutoff frequency of the low-pass filter 10 by setting the number of bits for shift calculation based on the number of inputs.

As a result, the average value sequential calculation device 1 (1a or 1b) uses a multiplier/divider-free low-pass filter 10 (10a or 10b) in which multiplication and division are replaced by shift operations, thereby reducing the calculation load and increasing speed. Moreover, the average value of time-series data can be calculated sequentially using a small-scale electronic circuit.

(A2) In the average value sequential calculation device 1 described in (A1), the low-pass filter 10 includes a shifter 11 capable of performing an arithmetic right shift operation, and calculates the value obtained by subtracting the output value of one cycle before from the input value. The value obtained by adding the output value of one cycle before to the value arithmetic right-shifted by the shifter 11 by the number of bits set by the setting unit 15 is set as the output value, and the setting unit 15 performs the arithmetic right-shifting based on the logarithm of the number of inputs. The number of bits for calculation may be set.

As a result, the average value sequential calculation device 1a reduces the calculation load of the average value and achieves high speed by substituting the shifter 11 for division and controlling the number of bits of the shift operation based on the logarithm of the number of inputs of sample values. Moreover, a small-scale electronic circuit can be realized.

(A3) In the average value sequential calculation device 1 described in (A1), the low-pass filter 10 includes a shifter 11 capable of performing an arithmetic right shift operation and a shifter 13 capable of performing a left shift operation, and The input value from one cycle before is added to , and the value obtained by subtracting the value obtained by shifting the output value from one cycle before to the left by one bit using the shifter 13 is arithmetic shifted to the right by the shifter 11 by the number of bits set by the setting unit 15. The setting unit 15 may set the number of bits of the arithmetic right shift operation based on the logarithm of the number of inputs, with the output value being the value obtained by adding the output value of one cycle before.

As a result, the average value sequential calculation device 1b substitutes the shifter 11 for division and the shifter 13 for multiplication, and controls the number of bits of the right shift operation based on the logarithm of the number of inputs of sample values. It is possible to reduce the calculation load and realize high-speed and small-scale electronic circuits.
Note that the shift operation by the shifter 13 may be an arithmetic left shift, but is not limited to this. If the input value is non-negative (unsigned number), the output value can also be considered non-negative (unsigned number), so the shift operation by the shifter 13 may be a logical left shift.

(A4) In the average value sequential calculation device according to (A2) or (A3), the upper limit of the arithmetic right shift operation is a predetermined maximum number of bits, and the setting unit 15 is configured to determine which of the logarithm of the number of inputs and the maximum number of bits. The smaller of these may be set as the number of bits for the arithmetic right shift operation.

Thereby, the average value sequential calculation device 1 (1a or 1b) can realize a small-scale electronic circuit with a limited circuit scale related to shift calculation by limiting the cutoff frequency of the low-pass filter 10 within the range necessary for operation. .

Next, a third embodiment and a fourth embodiment will be described as examples in which the average value sequential calculation device 1 (1a or 1b) is applied to a control device for industrial machinery.

[Third embodiment]
The control device 2 of the third embodiment measures and outputs a performance index for determining processing performance, debugging an operating program, detecting an abnormality in operation, or the like.

FIG. 12 is a block diagram showing the functional configuration of the control device 2 in the third embodiment.
The control device 2 includes a measurement unit 21 that measures performance indicators, and a calculation unit 22 that sequentially calculates the average value of the performance indicators.

The measurement unit 21 measures at least one of the following performance indicators.
・Required processing time per predetermined control cycle ・Number of occurrences of a specific interrupt per predetermined control cycle ・Number of single reads per predetermined control cycle ・Number of single writes per predetermined control cycle ・Number of single writes per predetermined control cycle Number of burst reads - Number of burst writes per predetermined control cycle - Number of read bytes per predetermined control cycle - Number of write bytes per predetermined control cycle - Bus idle time per predetermined control cycle - Every predetermined control cycle bus overlap time ・Number of specified condition hits per predetermined control cycle ・Single read latency ・Single write latency ・Burst read latency ・Burst write latency

Here, the bus idle time is defined as the number of clock cycles in which the number of bus outstandings (the number of incomplete transactions) is zero. The bus overlap time is defined as the number of clock cycles in which the number of bus outstandings is two or more. Note that, instead of these, the measurement unit 21 measures the number of clock cycles in which the outstanding number of the bus is 1, the number of clock cycles in which the outstanding number of the bus is 2, and the number of clock cycles in which the outstanding number of the bus is 3 or more. The configuration may be such that the number of clock cycles, etc. in the state of .
Furthermore, single read and single write latencies may be measured by filtering by access size or access destination address. For example, 1-byte access, 2-byte access, 4-byte access, and 8-byte access may be measured separately. Burst read and burst write latencies may be measured by filtering by burst length or access destination address. For example, latency may be measured only for bus transactions with the maximum burst length.

There may be a plurality of measurement points for the above-mentioned performance indicators in the control device 2. For example, there are measurement points for the above performance indicators at the master port and slave port of the bus of each CPU in the control device 2, the master port and slave port of the bus bridge, the master port of the DMA controller, the slave port of the memory controller, etc. good.

The calculation unit 22 sequentially calculates the average value as well as the minimum value and maximum value of the performance index measured by the measurement unit 21.
Here, the calculation unit 22 may be configured to include the average value sequential calculation device 1 (1a or 1b) of the first embodiment or the second embodiment described above. That is, the calculation unit 22 includes a variable IIR low-pass filter 10 (10a or 10b) that substitutes a shift operation for multiplication and division and outputs the average value of performance indicators that are sequentially input. Furthermore, the calculation unit 22 includes a setting unit 15 that controls the cutoff frequency of the low-pass filter by counting the number of inputs to the low-pass filter 10 and setting the number of bits for the shift operation based on the number of inputs.

Note that the calculation unit 22 may be configured as a part of the control device 2, but may also be an external information processing device communicatively connected to the control device 2.

According to the third embodiment, for example, the following effects (B1) to (B2) can be obtained.

(B1) The control device 2 determines the required processing time for each control cycle, the number of occurrences of a specific interrupt for each control cycle, the number of single reads for each control cycle, the number of single writes for each control cycle, and the burst read for each control cycle. number of burst writes per control cycle, number of read bytes per control cycle, number of write bytes per control cycle, bus idle time per control cycle, bus overlap time per control cycle, specified condition hit per control cycle a measurement unit 21 that measures performance indicators including at least one of the number of times, single read latency, single write latency, burst read latency, or burst write latency; and a calculation unit 22 that sequentially calculates the average value of the performance indicators. and.

As a result, the control device 2 sequentially outputs the average value as a long-term trend of the performance index measured at each control cycle, and is used for determining processing performance, debugging operating programs, detecting abnormalities in operation, etc. Can be provided in a timely manner.

(B2) In the control device 2 described in (B1), the calculation unit 22 includes a variable IIR low-pass filter 10 that substitutes a shift operation for multiplication and division, and outputs an average value of performance indicators that are sequentially input; The low-pass filter 10 may include a setting unit 15 that controls the cutoff frequency of the low-pass filter 10 by counting the number of inputs to and setting the number of bits for shift calculation based on the number of inputs.

Thereby, the control device 2 realizes high-speed average value sequential calculation with a small circuit scale, and can easily provide the average value of the performance index.

[Fourth embodiment]
In the fourth embodiment, a plurality of control devices 3 are connected to each other via communication paths, and each control device 3 generates time-synchronized control period signals.

FIG. 13 is a diagram illustrating a method of generating a control period signal in the fourth embodiment.
The plurality of control devices 3 perform time synchronization between a master and a slave using Precision Time Protocol (PTP) of a local area network (LAN) or Precision Time Measurement (PTM) of PCI Express.

Each synchronized control device 3 generates a Pulse Per Second (PPS) signal and generates an Interpolation Timing Pulse (ITP) signal indicating a control period T _ITP which is m/M times the period T _PPS of this PPS signal.
That is, the time ITP _kM+m of the kM+m-th ITP signal is defined as follows based on the times PPS k and PPS _k + _{1 of the k-th and k+1-th} PPS signals.
ITP _kM+m = PPS _k+1 + (PPS _k+1 - PPS _k )・m/M
(m=0,1,...,M-1)

FIG. 14 is a block diagram showing the functional configuration of the control device 3 in the fourth embodiment.
The control device 3 includes a synchronization section 31, a PPS signal generation section 32, a period measuring device 33 (measurement section), a jitter removal filter 34 (calculation section), and an ITP signal generation section 35 (control period signal generation section). Equipped with

The synchronization unit 31 synchronizes the built-in clock of the control device 3 with the master control device 3 via a communication path.
The PPS signal generator 32 generates a PPS signal based on a synchronized built-in clock.
Note that the synchronization unit 31 and the PPS signal generation unit 32 may be a communication controller capable of time synchronization, such as a PTP-compatible Ethernet (registered trademark) controller or a PTM-compatible PCI Express core.

The period measuring device 33 measures the period of the PPS signal, that is, the time between pulses (number of clock cycles) using a reference clock having a frequency sufficiently faster than that of the PPS signal.
At this time, the period measuring device 33 may output a value obtained by multiplying the measurement result by a predetermined value (N times).

The jitter removal filter 34 removes jitter, that is, period fluctuation, from the PPS signal by sequentially calculating the average value of the periods measured by the period measuring device 33.
Here, the jitter removal filter 34 may be configured to include the average value sequential calculation device 1 (1a or 1b) of the first embodiment or the second embodiment described above. That is, the jitter removal filter 34 includes a variable IIR low-pass filter 10 that substitutes shift operations for multiplication and division, and outputs the average value of the cycles input sequentially, and a variable IIR low-pass filter 10 that counts the number of inputs to the low-pass filter 10 and calculates the number of inputs based on the number of inputs. and a setting unit 15 that controls the cutoff frequency of the low-pass filter 10 by setting the number of bits for shift calculation.

The ITP signal generation unit 35 generates an ITP signal indicating the control period by multiplying the number of pulses of the PPS signal based on the average value of the period measured by the period measuring device 33 and smoothed by the jitter removal filter 34. .

Specifically, first, the multiplier setting register 351 sets the multiplier M, and the divider 352 divides M00...0 (L bit 0) by the PPS period (clock cycle number), and the result is the L bit. It is input to accumulator 353. In the L-bit accumulator 353, when the input is added by the number of PPS periods (number of clock cycles), overflow (carry) occurs M times. As a result, the carry signal becomes the PPS signal multiplied by M.
This carry signal is counted by an incrementer 354, and the count number is compared with M by a comparator 355. When counted M times, the count number is reset. Then, the ITP signal generating section 35 outputs a PPS signal when the count number is 0, and outputs a carry signal as an ITP signal when the count number is other than 0.

Here, a case has been shown in which the ITP signal is generated by multiplying the PPS signal by M, but the period of the ITP signal is not limited to this. For example, when the period measuring device 33 outputs N times the period of the PPS signal, the ITP signal generating section 35 generates a pulse by dividing the N times the period by M. Therefore, an ITP signal obtained by multiplying the PPS signal by M/N is output.

According to the fourth embodiment, for example, the following effects (C1) to (C4) can be obtained.

(C1) The plurality of control devices 3 are connected to each other via a communication path, and each control device 3 has a synchronization section 31 that synchronizes a built-in clock via a communication path, and a synchronization section 31 that synchronizes a built-in clock via a communication path. A PPS signal generating section 32 that generates a PPS signal, a period measuring device 33 that measures the period of the PPS signal, and an ITP signal generating section 35 that generates an ITP signal indicating a control period based on the period measured by the period measuring device 33. , is provided.

Thereby, the control device 3 can appropriately generate an ITP signal whose phase matches that of the PPS signal by measuring the period of the time-synchronized PPS signal. As a result, the control cycles of the plurality of control devices 3 can be synchronized.
At this time, the control device 3 does not need to know the period of the PPS signal in advance, and the synchronization of the ITP signals among the plurality of control devices 3 is completed at the time when the generation of the ITP signal is started after measuring the period.

(C2) In the control device 3 described in (C1), the period measuring device 33 may output a value obtained by multiplying the measured period by a predetermined value.

Thereby, the control device 3 multiplies the period of the PPS signal by N and then generates pulses divided by M, so that the control device 3 can output an ITP signal obtained by multiplying the PPS signal by M/N.

(C3) The control device 3 according to (C1) or (C2) includes a jitter removal filter 34 that sequentially calculates the average value of the periods measured by the period measuring device 33, and the ITP signal generation unit 35 calculates the average value of the period measured by the period measuring device 33. The ITP signal may be generated based on.

Thereby, the control device 3 can smooth the period measurement result and reduce the influence of jitter present in the PPS signal. As a result, fluctuations in the period of the ITP signal can be reduced. Further, the control device 3 can follow the ITP signal even if the PPS period fluctuates slowly.

(C4) In the control device 3 described in (C3), the jitter removal filter 34 includes a variable IIR low-pass filter 10 that substitutes shift operations for multiplication and division, and outputs the average value of the sequentially input cycles; The low-pass filter 10 may include a setting unit 15 that controls the cutoff frequency of the low-pass filter 10 by counting the number of inputs to and setting the number of bits for shift calculation based on the number of inputs.

Thereby, the control device 3 realizes high-speed average value sequential calculation with a small circuit scale, and can easily provide the average value of the period of the PPS signal.

Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above. For example, in the first embodiment and the second embodiment, a first-order variable IIR low-pass filter is used, but a second-order or higher-order variable IIR low-pass filter may be used. For example, an N-order variable IIR low-pass filter may be realized by cascading N first-order variable IIR low-pass filters. Further, the effects described in this embodiment are only a list of the most preferable effects resulting from the present invention, and the effects according to the present invention are not limited to those described in this embodiment.

The average value sequential calculation method by the average value sequential calculation device 1 is realized by software. When realized by software, programs constituting this software are installed on the computer. Furthermore, these programs may be recorded on removable media and distributed to users, or may be distributed by being downloaded to users' computers via a network.

1, 1a, 1b average value sequential calculation device 2 control device 3 control device 10, 10a, 10b low-pass filter 11 shifter (first shifter)
13 Shifter (second shifter)
15 Setting section 21 Measuring section 22 Calculating section 31 Synchronizing section 32 PPS signal generating section 33 Period measuring device (measuring section)
34 Jitter removal filter (calculation section)
35 ITP signal generation section (control period signal generation section)

Claims (4)

a variable infinite impulse response (IIR) low-pass filter that substitutes shift operations for multiplication and division and outputs an average value of input values that are input sequentially;
An average value sequential calculation device comprising: a setting unit that controls a cutoff frequency of the low-pass filter by counting the number of inputs to the low-pass filter and setting the number of bits of the shift operation based on the number of inputs. The low pass filter is
Equipped with a shifter that can perform arithmetic right shift operations,
The output value is the sum of the value obtained by subtracting the output value from one cycle before from the input value, and the value obtained by arithmetic right-shifting by the shifter by the number of bits set by the setting unit, and the output value from one cycle before. ,
The average value sequential calculation device according to claim 1, wherein the setting unit sets the number of bits of the arithmetic right shift operation based on the logarithm of the number of inputs. The low pass filter is
a first shifter capable of performing an arithmetic right shift operation;
A second shifter capable of performing a left shift operation,
The input value from one cycle before is added to the input value, and the value obtained by subtracting the value obtained by shifting the output value from one cycle before to the left by one bit by the second shifter is added to the input value by the number of bits set by the setting section. The value obtained by adding the output value of the previous cycle to the value arithmetic shifted to the right by one shifter is set as the output value,
The average value sequential calculation device according to claim 1, wherein the setting unit sets the number of bits of the arithmetic right shift operation based on the logarithm of the number of inputs. The arithmetic right shift operation has an upper limit of a predetermined maximum number of bits;
4. The average value sequential calculation device according to claim 2, wherein the setting unit sets the smaller of the logarithm of the number of inputs and the maximum number of bits as the number of bits of the arithmetic right shift operation.

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