JP2007225566A - Malfunctioning detection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect occurrence of malfunctioning with higher precision. <P>SOLUTION: The detection system 1 of a programmable display is provided with a plurality of bandpass filters 11, ... which are connected in parallel with one another and remove, from input signals, signal components other than pass bands determined beforehand for them respectively, and a matching processing section 4. The processing section 4 detects whether or not malfunctioning occurs, depending on whether or not changes with time of the output signal of each bandpass filter 11 coincides with a predetermined pattern. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an abnormality detection device that detects whether or not an abnormality has occurred based on an input signal indicating, for example, sound, vibration, or a rotational frequency of a motor.

For example, an abnormal state detection device shown in Patent Document 1 and the like to be described later detects a sound related to an abnormal state and converts it into an electric signal, a filter that extracts a predetermined frequency component of the electric signal, A timer for measuring the duration of the predetermined frequency component, and detecting an abnormal state of the electrical device by issuing a signal for determining an abnormal state when the timer measures the predetermined time.
Japanese Patent Laid-Open No. 5-034396 (published February 9, 1993)

  However, as described above, it is sufficient to determine whether or not an abnormal state is present from an input signal indicating sound, vibration, motor rotation frequency, or the like only by determining the abnormal state when the timer measures a predetermined time. Therefore, it is difficult to judge the occurrence of abnormality, and it is required to detect the occurrence of abnormality with higher accuracy.

  The present invention has been made in view of the above problems, and an object of the present invention is to realize an abnormality detection apparatus capable of detecting the occurrence of abnormality with higher accuracy.

  In order to solve the above problems, the abnormality detection apparatus according to the present invention is connected in parallel to each other, and a plurality of bandpass filters that remove signal components other than a predetermined passband from the input signals, respectively, And a matching processing means for detecting whether or not an abnormality has occurred depending on whether or not the time change of the output signal of each bandpass filter matches a predetermined pattern.

  Further, in addition to the above configuration, the matching processing means can set one or a plurality of states as the patterns to be passed from an initial state to a final state where a pattern match is detected. For each state, as an event necessary for transitioning to the next state, it can be set that the output of a predetermined bandpass filter out of the plurality of bandpass filters exceeds a threshold value. Also good. In this case, the pattern is set as a change in the combination of the bandpass filter outputs. Moreover, in addition to the said structure, the said input signal is an audio | voice signal, The said abnormality detection apparatus may detect the abnormal sound which generate | occur | produces from the apparatus in a programmable display. In addition, the abnormality detection apparatus may be in a programmable display or may be outside.

  Here, when a failure is to occur in a device, for example, unusual vibration or abnormal noise may occur, or the rotational frequency of the motor may change to be different from normal. Further, when a failure is about to occur, these sounds, vibrations, rotation frequency of the motor, etc. may change according to a predetermined pattern with time. If you are familiar with the equipment, you may be able to foresee whether a failure will occur from these sounds, vibrations, or changes in the rotational frequency of the motor. Based on these, it is difficult to predict the occurrence of a failure.

  On the other hand, each of the above configurations is provided with a band pass filter and a matching processing means, and an input signal indicating these sounds, vibrations, motor rotation frequency, etc. is input to the band pass filter. The matching processing means detects whether or not an abnormality has occurred depending on whether or not the time change of the output signal of each bandpass filter matches a predetermined pattern. Therefore, even a person who is not familiar with the device or a machine can determine whether or not the device is likely to break down (whether or not an abnormality has occurred) with high accuracy, enabling predictive maintenance of the device. Become.

  In addition to the above configuration, the matching processing means sets a time from the transition to the next state to the occurrence of an event for transition to the next state as the pattern. It may be possible.

  In the above configuration, as the above pattern, the time from the transition to the next state to the occurrence of the event for transitioning to the next state can be set, so not only the change in the combination of bandpass filter outputs, but also You can also set the time interval when the change occurs, and more accurately describe the pattern when an abnormality occurs. As a result, an abnormality detection device capable of detecting an abnormality with higher accuracy can be realized.

  Further, in addition to the above configuration, when the matching processing means detects an event for transitioning to the next state at a timing deviating from the pattern, the bandpass filter determines whether or not to return to the initial state. It may be possible to set in advance every time.

  In this configuration, it is possible to set whether or not to return to the initial state when an event for transitioning to the next state is detected at a timing deviating from the pattern for each bandpass filter. An abnormality detection device capable of detection can be realized.

  In addition, since the matching processing means can set the time from the transition to the state to the occurrence of an event for transitioning to the next state, and transitioning to the next state at a timing deviating from the pattern If it is possible to set whether or not to return to the initial state when an event is detected, a timeout time is set as the above time, and an event for transitioning to the next state does not occur even if the timeout time elapses In such a case, by setting so as to return to the initial state, the matching processing unit does not continue to wait for the next state in the middle state, and an abnormality detection device capable of more stable operation can be realized.

  In addition to the above configuration, the bandpass filter can switch the operating frequency to the first frequency and the second frequency lower than that, and the abnormality detecting device has the operating frequency of When the first frequency is set and the operating frequency of the band-pass filter is the second frequency, an input-side low-pass filter for removing a high-frequency component of a signal input to the band-pass filter is provided. Each stores a digital value periodically input at the operating frequency by the order of the filter, a digital value stored in the storage circuit, and a filter coefficient constituting a filter coefficient sequence of the filter A digital FIR (Finite Impulse Response) filter including an arithmetic circuit for calculating a product-sum operation result with the bandpass filter. When the band pass filter operates at the first frequency, the arithmetic circuit of the filter replaces the storage circuit of the band pass filter with the digital value stored in the storage circuit of the input side low pass filter and the band pass filter. A product-sum operation result with the filter coefficient may be calculated.

  In the above configuration, since the band pass filter can switch the operating frequency to the first frequency and the second frequency lower than the first frequency, the band pass filter makes the sequence length of the filter coefficient sequence too long. The signal component in the lower frequency band can be extracted without increasing the circuit scale without much. In the above configuration, when the operating frequency of the band-pass filter is the second frequency, the input-side low-pass filter removes the high-frequency component of the signal input to the band-pass filter. Therefore, although the operating frequency can be changed, the occurrence of aliasing errors can be suppressed, and a highly accurate abnormality detection device can be realized.

  In addition, when the bandpass filter operates at the first frequency, the arithmetic circuit of the bandpass filter replaces the storage circuit of the bandpass filter with a digital value stored in the storage circuit of the input-side lowpass filter. A product-sum operation result with the filter coefficient of the bandpass filter is calculated. In other words, when the band-pass filter operates at the first frequency, the storage circuit of the input-side low-pass filter operates as the storage circuit of the band-pass filter.

  Therefore, unlike the configuration in which the storage circuit that stores the digital value when the bandpass filter operates at the second frequency stores the digital value even when the bandpass filter operates at the first frequency, the bandpass filter The memory circuit that stores the digital value when operating at the second frequency only needs to be able to operate at the second frequency. As a result, it is possible to limit the portions that need to operate at high speed in the abnormality detection device, and to reduce the power consumption of the entire abnormality detection device.

  In addition, when the bandpass filter operates at the second frequency, the digital circuit also operates when the bandpass filter operates at the first frequency as a separate circuit from the storage circuit that stores the digital value when the bandpass filter operates at the second frequency. The circuit scale can be reduced as compared with a configuration in which a storage circuit for storing values is provided.

  Since the storage circuit of the input side low-pass filter operates at the first frequency in the same manner as the band-pass filter when operating at the first frequency in order to remove the high-frequency component of the input signal of the band-pass filter. The operation circuit of the band-pass filter when operating at the first frequency can calculate the product-sum operation result of the digital value stored in the storage circuit of the input-side low-pass filter and the filter coefficient without any problem.

  As a result, a highly accurate abnormality detection device can be realized without significantly increasing the circuit scale and power consumption.

  According to the present invention, whether or not an abnormality has occurred is detected based on whether or not the time change of the output signal of each bandpass filter matches a predetermined pattern. Even if it is a person or a machine that is not working, it can be determined in advance whether or not a failure is likely to occur in the device, and predictive maintenance of the device becomes possible.

  An embodiment of the present invention will be described below with reference to FIGS. That is, the detection system (digital filter circuit) 1 according to the present embodiment is a system that is preferably used for detecting whether or not an abnormality has occurred in the hard disk from the operating sound of the hard disk, for example. It is possible to detect whether or not the time change of the input audio signal matches a predetermined pattern.

  Below, before explaining the structure of the said detection system 1, the schematic structure and schematic operation | movement of a control system containing the programmable display in which the detection system 1 was provided are demonstrated easily. That is, as shown in FIG. 2, the control system 501 according to the present embodiment is suitably used for controlling a target system 502 provided in a manufacturing plant, for example, and for example, a belt conveyor type automatic It is used to control a device (control target) 502a of the target system 502 such as an assembly machine.

  The control system 501 includes a PLC 511 as a control device for controlling the device 502a, and is often arranged in the vicinity of the control target, and also displays the status of the device 502a as an HMI of the control system 501, by the operator And a programmable display 512 that receives an operation on the device 502a. Note that the programmable display 512 may also have a function as a PLC. In this case, the programmable display 512 is directly connected not only to the corresponding PLC 511 but also to the device 502a that it controls.

  Furthermore, in the control system 501 according to the present embodiment, the programmable displays 512 are connected to each other by a LAN (Local Area Network) 513 such as Ethernet (registered trademark). Further, in many cases, a control host computer 514 that manages the entire control system 501 is connected to the LAN 513 from a location far from the programmable display 512.

  Each programmable display 512 is connected to a corresponding PLC 511 through a serial cable or the like. In FIG. 2, for convenience of explanation, two programmable displays 512 are connected to the LAN 513, and one PLC 511 and one device 502 a are connected to each programmable display 512, and a device 502 a is connected to each PLC 511. Although the case where one unit is connected is illustrated, it is a matter of course that the number of connected units can be arbitrarily set.

  Further, the device may be the device 502a itself, for example, as long as it can be specified by a device address or a variable and can acquire or control (change) the state. For example, the device may be a PLC 511 or a programmable display. An area of a storage device provided in the control system 501 such as a storage device of the device 512 may be shown.

  Here, the control system 501 is a configuration essential to the control system 501, and since it operates as an HMI, the programmable display 512 having sufficient computing capacity is configured to process most of the communication. . Further, each programmable display 512 converts a dedicated protocol specific to the model of the PLC 511 connected to itself and a common protocol in the LAN 513, and the other programmable display 512, the control host computer 514, and the PLC 511 are converted. Relay communication with For protocol conversion between the common protocol and the dedicated protocol, conversion between a common command predetermined so that the same code is assigned to the same instruction and a command unique to the PLC 511 corresponding to the common command is performed. Also included are conversion of data and address expression methods, conversion of device addresses and variables that correspond to the device addresses, and that can be set to values different from the device addresses and variable names (variable names). .

  Thus, the programmable display 512 and the control host computer 514 can communicate with each other via the LAN 513 regardless of the PLC 511 connected to the other programmable display 512. As a result, the control system 1 in which different types of PLCs 511 are mixed can be realized relatively easily.

  The programmable display 512 specifies the operation when displaying the device state on the screen and the operation when controlling the device state according to the operation on the screen, based on screen data to be described later. , A PLC / IF unit 521 that communicates with the PLC 511, a LAN / IF unit 522 for connecting to the LAN 513, a display 523 including, for example, a liquid crystal display device, and a touch panel 524 arranged on the screen of the display 523, The HMI processing unit 525 that controls the members 521 to 524, and the storage unit 526 that is referred to by the HMI processing unit 525 and stores the screen data and variables to be described later.

  In each of the above members 521 to 525, a calculation unit such as a CPU executes a program stored in a storage unit such as a ROM or a RAM, and an input / output unit such as a touch panel or a liquid crystal display device, an interface circuit, or the like. It is a functional block realized by controlling a communication circuit. Of these members, each storage unit 526 may be a storage device itself such as a RAM. Therefore, the programmable display 512 according to the present embodiment can be realized simply by a computer having these means reading a recording medium (for example, a CD-ROM) on which the program is recorded and executing the program. For example, if a program for downloading a program via the LAN 513 or another communication path is installed in the computer in advance, the program is distributed to the computer via the communication path. You can also.

  The screen data is configured by combining a tag indicating a correspondence relationship between an area on the screen and a device corresponding to display or input in the area. In this embodiment, the HMI processing unit 525 can switch and display a plurality of unit screens, and the tag specifies the file number indicating the unit screen in which the tag is valid and the operation content to be executed on the unit screen. Event name and reference information referenced for each event.

  For example, when the tag is a display tag that displays a component graphic corresponding to a predetermined device state in a predetermined screen area (display coordinate range), the reference information includes a display coordinate range and a variable that can specify the device. For example, when the component graphic is a switch, a file number to be referred to at the time of display such as a graphic file indicating ON and a graphic file indicating OFF is included. Further, when the tag is an input tag, reference information includes an effective input coordinate range and a device variable in which an input result is written.

  In addition, the storage unit 526 is provided with an area for variables (variable area). In the variable area, for each variable, the name of the variable (variable name) and the device 502a corresponding to the variable or the internal A combination of information (for example, an address) for specifying the memory and the contents of the variable is stored. In this embodiment, regardless of the model of the device 502a corresponding to the variable, the expression method (for example, word length, presence / absence of code, BCD / binary notation, etc.) for storing the contents of the variable is previously set. In the case where the expression is standardized and the variable corresponds to the actual device 502a, the storage unit 526 also stores the expression method in the actual model. In this case, when the HMI processing unit 525 acquires or controls the state of the device 502a via the PLC / IF unit 521, the HMI processing unit 525 performs format conversion of the representation method to unify the representation method at the time of storage.

  On the other hand, the HMI processing unit 525 extracts the display tag whose base screen file number is the currently displayed base screen from the screen data stored in the storage unit 526 at predetermined time intervals. Further, the HMI processing unit 525 refers to the variable area of the storage unit 526, reads the content of the variable corresponding to the tag, and displays a part graphic corresponding to the content on the display 23. Here, when the variable corresponds to the device 2a controlled by the PLC 511 connected to the PLC / IF unit 521, the HMI processing unit 525 communicates with the PLC 511 by the PLC / IF unit 521 to communicate with the device 502a. And the contents of the variable are updated according to the state. As a result, the state of the device 502a is displayed on the display 523.

  In the case of the device 502a controlled by the PLC 511 connected to another programmable display 512, the HMI processing unit 525 is connected to the PLC 511 via the LAN / IF unit 522, the LAN 513, and the other programmable display 512. The state of the device is acquired through communication or the like, and the content of the variable is updated accordingly.

  When receiving an operator input operation such as a push operation on the touch panel 524, the HMI processing unit 525 searches the screen data for an input tag corresponding to the currently displayed base screen and matching the input operation. At the same time, the content of the variable corresponding to the tag is updated according to the input result. Furthermore, the HMI processing unit 525 controls the state of the device 502a according to the contents of the variable by communicating with the PLC 511 and the programmable display 512, for example, in the same manner as when acquiring the state of the device 502a. Here, even after the input operation, the HMI processing unit 525 displays the state of the device 502a on the screen, so that the operation result is reflected on the screen display.

  In addition, the HMI processing unit 525 receives a control instruction from the device connected to the LAN 513 such as another programmable display 512 or the control host computer 514 to the device 502a of the PLC 511 connected to the HMI processing unit 525. On the contrary, when the status of the device 502a to be reported to the device is received from its own PLC 511, it is possible to relay between the communication on the LAN 513 and the communication with the PLC 511 by the protocol conversion described above. .

  Thereby, the programmable display 512 can display the state of the device on the screen based on the screen data, or can control the state of the device according to an operation on the screen.

  Here, in the programmable display device 512 according to the present embodiment, for example, a hard disk drive is employed as the storage unit 526, and the hard disk drive has vibrations or abnormal sounds that are different from normal when a failure is likely to occur. May occur, or the rotational frequency of the motor may change to be different from normal.

  On the other hand, the programmable display 512 according to the present embodiment determines whether or not an abnormality has occurred in the device based on the sound, vibration generated from the device such as a hard disk drive, or the rotational frequency of the motor of the hard disk drive. A detection system 1 is provided. In the following, a configuration for detecting the presence or absence of abnormality based on sound will be described.

  Specifically, the detection system 1 according to the present embodiment is a system for processing an audio signal input to the input terminal Tin, and includes a plurality of filter units 2 as shown in FIG. In the input terminal Tin, for example, an ADC converts a digital value obtained by AD-converting an analog audio signal from the device to be detected (in this case, a hard disk drive) at a predetermined sampling frequency (for example, 48 kHz). A digital audio signal that has been converted into a digital value in advance is input.

  Each filter unit 2 determines whether or not the magnitude of a signal component in a predetermined frequency band among input audio signals exceeds a predetermined threshold, A bandpass filter 11 that passes a signal component in a predetermined frequency band, an absolute value (or a root mean square) of an output value of the bandpass filter 11, and an absolute value of an output value of the bandpass filter 11 The moving average value calculating unit 12 that calculates the moving average value of the moving average value, and the determining unit 13 that determines whether or not the output value of the moving average value calculating unit 12 exceeds a predetermined threshold value.

  In the present embodiment, as described above, the audio signal is input as a digital signal, and the bandpass filter 11 is realized by an FIR digital filter as will be described in detail later.

  Each filter unit 2 can set the frequency band and the threshold value independently of each other, and can set the frequency band and / or the threshold value different from each other. Further, each filter unit 2 can accept the frequency band and threshold setting instructions by, for example, specifying a filter coefficient string of the bandpass filter 11 or specifying a threshold value.

  Each bandpass filter 11 according to the present embodiment can operate not only at a predetermined frequency (normal frequency) but also at a lower frequency (frequency during downsampling). Thereby, even if it is a case where the pass band of the band pass filter 11 is set to a low frequency, it can suppress that the sequence length of a filter coefficient sequence becomes long. Furthermore, the detection system 1 according to the present embodiment can change the ratio between the normal frequency and the frequency at the time of downsampling according to an instruction from the outside.

  In addition, the detection system 1 according to the present embodiment is provided with a low-pass filter 3 as an input-side low-pass filter. When each band-pass filter 11 samples at a normal frequency, the original audio signal ( When an audio signal input to the input terminal Tin is operated as an input signal and sampling is performed at a frequency at the time of downsampling, the audio signal via the low-pass filter 3 can be operated as an input signal.

  Here, at the time of sampling, information of a frequency of 1/2 or more of the sampling frequency is lost. Therefore, in order to prevent the occurrence of an aliasing error, it is desirable to remove in advance a component having a frequency of ½ or more of the sampling frequency. However, since the frequency band to be removed differs between the case where the sampling frequency is the normal frequency and the case where the sampling frequency is the frequency at the time of downsampling, the low-pass filter determines a predetermined low frequency from the audio signal input to the detection system 1. If the frequency component is removed, the aliasing error may occur in the case of the downsampling frequency or the aliasing error may occur in the case of the downsampling frequency. In this case, even if the occurrence of an aliasing error can be prevented appropriately, a part of the signal component may be removed at the normal frequency.

  However, in the detection system 1 according to the present embodiment, each band pass filter 11 selects one of the output signal of the low pass filter 3 and the original audio signal as an input signal. The occurrence of aliasing errors can be prevented appropriately.

  Here, the low-pass filter 3 may be provided for each band-pass filter 11. However, in the detection system 1 according to the present embodiment, as shown in FIG. A filter 3 is provided in common for each bandpass filter 11.

  In addition, the detection system 1 determines whether or not the time change of the output signal from each filter unit 2 (more specifically, the determination result of each determination unit 13) matches a predetermined pattern. The matching processing unit 4 is provided, and when matched, the final detection result signal Q indicating true can be output.

  Here, as described above, when a failure is to occur in a device, for example, unusual vibration or abnormal noise occurs, or the rotational frequency of the motor changes to be different from normal. Sometimes. Further, when a failure is about to occur, these sounds, vibrations, rotation frequency of the motor, etc. may change according to a predetermined pattern with time. If you are familiar with the equipment, you may be able to foresee whether a failure will occur from these sounds, vibrations, or changes in the rotational frequency of the motor. Based on these, it is difficult to predict the occurrence of a failure.

  However, the detection system 1 determines whether the time change of the output signal from each filter unit 2 (more specifically, the determination result of each determination unit 13) matches a predetermined pattern. ing. Therefore, even a person who is not familiar with the device or a machine can determine in advance whether or not the device is likely to fail (whether it is in an abnormal state), thereby enabling predictive maintenance of the device. Become.

  More specifically, the matching processing unit 4 according to the present embodiment sets one or a plurality of states as a state to be passed from the initial state where the start of the pattern is not detected to the final state where the pattern match is detected. it can. In addition, the matching processing unit 4 indicates that each state has an event necessary for moving to the next state as “the detection result of the predetermined filter unit 2 among the output signals of each filter unit 2 is true. Can be set.

  As a result, whether or not the occurrence of another event is detected before the occurrence of an event for transitioning to another state from the time when the state becomes a certain state, Regardless of the elapsed time until the occurrence of an event for transitioning to a state is detected, the detection system 1 can detect whether the time change of the output signal from each filter unit 2 matches a predetermined pattern, The final detection result signal Q indicating true can be output.

  Furthermore, the matching processing unit 4 according to the present embodiment sets, for each state, a period for waiting for the occurrence of an event necessary for moving to the next state, for example, by an elapsed time after detecting the start of the pattern. Events that occur during other periods can be ignored, and predetermined processing such as processing for returning to the initial state (initialization processing) can be performed. Thereby, the time change of the output signal from each filter part 2 can be specified not only by the order but also by the time interval between the states, and the pattern can be described more accurately.

  In addition, the matching processing unit 4 according to the present embodiment can set an event for returning to the initial state for each state. Thereby, for example, when the detection result of the filter unit 2 other than the filter unit 2 that is waiting for the detection result to be true becomes true, it is initialized or before the waiting period, or after If detected at the time, it can be initialized.

  Thereby, when it determines with not matching a pattern, it can be made to return to an initial state, and a pattern can be described more correctly. Further, in each state, the matching processing unit 4 can initialize the pattern matching process when a standby event does not occur even after a predetermined timeout period elapses. As a result, it is possible to prevent waiting in the middle, and stably detect whether or not the time change of the input audio signal matches a predetermined pattern.

  Furthermore, the matching processing unit 4 according to the present embodiment can determine whether or not to perform pattern matching processing according to the Match_EN signal. If the Match_EN signal is set to invalid, the pattern matching processing by the matching processing unit 4 is stopped. Can be made.

  Below, the structural example of the matching process part 4 is demonstrated, referring FIG. 3 and FIG. That is, as shown in FIG. 3, the matching processing unit 4 according to this configuration example detects a register 21 that stores information on a pattern to be detected, a state counter 22 that stores a current state, and the start of the pattern. Flip-flops 23 that store whether or not (pattern matching is in progress) and the respective filter units 2 are provided corresponding to the output signals of the filter units 2 and the outputs of the members 21 to 23 corresponding thereto. Based on the signal, the FilterOK signal, that is, in the current state, does not prevent the output signal of the filter unit 2 corresponding thereto from transitioning to the next state (the next state in the sequence from the initial state to the final state). A final detection based on the output signal of each determination circuit 24 including a determination circuit 24 that generates a signal indicating a value and a FilterOK signal To generate a result signal Q, and a control circuit 25 for controlling the respective members 22 to 23.

  As shown in FIG. 4, the register 21 is provided with a sequence storage area associated with each filter unit 2, and the sequence storage area is associated with each of the states S0 to S7 and is in that state. Further, Sqce_Con data indicating whether or not the determination circuit 24 corresponding to the filter unit 2 determines the output signal of the filter unit 2 is stored. In FIG. 4, reference numerals of the filter unit 2 corresponding to the parentheses () are illustrated.

  On the other hand, the determination circuit 24 indicates that the output signal of the flip-flop 23 is in the process of pattern matching, and the Sqce_Con stored in the register 21 in association with the filter unit 2 corresponding to itself and the state indicated by the state counter 22. When the data indicates true (needs determination), the true / false of the FilterOK signal can be changed according to the output signal (true / false) of the filter unit 2. On the contrary, if the output signal of the flip-flop 23 does not indicate that pattern matching is being performed, and if the Sqce_Con data indicates false (no determination is required), the true value is obtained regardless of the output signal of the filter unit 2. Filter OK signal can be output.

  Further, the control circuit 25 is provided with an AND circuit 25a for calculating a logical product of the FilterOK signals of the determination circuits 24. An output signal of the AND circuit 25a is applied to a count-up terminal of the state counter 22. ing. Accordingly, when all the FilterOK signals indicate that “the output signal of the filter unit 2 corresponding to the FilterOK signal does not prevent transition to the next state in the current state” (if true), the state counter The count value indicating the current state stored in 22 can be changed to a value indicating the next state.

In this configuration example, the state counter 22 is realized by a 7-bit shift register, and the output signal of the AND circuit 25a is connected to a shift terminal as a count-up terminal. In this configuration example, the input terminal of the shift register is set to 1, and every time the shift terminal becomes true, from 00h indicating the initial state to 01h, 03h, 07h,..., 7Fh, The output value can be changed sequentially.
In this configuration example, the output signal of the AND circuit 25a is also used for waveform shaping (timing adjustment) of the final detection result signal Q, and the AND circuit 25b provided in the control circuit 25 A logical product of the final state signal indicating that the output signal of the counter 22 indicates the final state (S7) and the output signal of the AND circuit 25a is output as the final detection result signal Q. In FIG. 3, as an example, in this configuration example, the logical product of all the bits of the output signal of the shift register as the state counter 22 and the output signal of the AND circuit 25 a is the final detection result signal. For example, if the comparison result between the register that stores the final state and the output signal of the state counter 22 is the final state signal, the control circuit can change the value of the register. , You can change the number of states.

  Further, each determination circuit 24 can also output a Match_St signal indicating the start of the pattern in addition to the FilterOK signal, and the Sqce_Con data stored in association with the filter unit 2 corresponding to itself and the initial state. Is true, the true / false of the Match_St signal can be changed according to the output signal (true / false) of the filter unit 2. The control circuit 25 is provided with an OR circuit 25c that calculates the logical sum of the Match_St signals of the determination circuits 24. The output signal of the OR circuit 25c is applied to the set terminal of the flip-flop 23. ing. Thus, when any of the determination circuits 24 detects the start of a pattern, the flip-flop 23 can be set to a value indicating that pattern matching is in progress.

  Each determination circuit 24 according to the present configuration example can also output a Match_Init signal indicating that the initial state is returned in addition to the FilterOK signal and the Match_St signal.

  Specifically, EV_Time data indicating a timeout time is stored for each filter unit 2 in the register 21 according to this configuration example. Further, the determination circuit 24 waiting for the output signal of the filter unit 2 corresponding to itself to be true, that is, the filter unit 2 corresponding to itself and the state indicated by the state counter 22 is stored in the register 21. If the Sqce_Con data is true (determined to be necessary), the determination circuit 24 does not become true even if the EV_Time data elapses after the EV_Time data has passed. , A true Match_Init signal can be output.

  In the matching processing unit 4 according to this configuration example, the time counter 26 that is counted up at a predetermined cycle and is reset when any of the determination circuits 24 detects the start of a pattern is used for each determination. Each determination circuit 24 refers to the output value of the time counter 26 and grasps the elapsed time from the time when the start of the pattern is detected. In this configuration example, for example, the output signal of the OR circuit 25 c is applied to the reset terminal of the time counter 26. On the other hand, the determination circuit 24 waiting for the output signal of the filter unit 2 corresponding to itself to be true is, for example, the count value of the time counter 26 at the time when the current state is reached and the current time counter. It is determined whether or not EV_Time data has elapsed since the current state was reached, for example, by determining whether or not the difference from the count value of 26 exceeds the value indicated by EV_Time data.

  Further, the control circuit 25 is provided with an OR circuit 25d for calculating the logical sum of the Match_Init signals of the determination circuits 24. The output signal of the OR circuit 25d is the reset terminal of the state counter 22 and the flip-flop 23. Is applied. As a result, when any of the determination circuits 24 outputs a true Match_Init signal, the matching processing unit 4 can be returned (initialized) to the initial state. As a result, the matching processing unit 4 may return to the initial state when the output signal of the filter unit 2 necessary for transitioning to the next state does not become true even after a predetermined timeout period has elapsed. it can.

  In addition, the matching processing unit 4 according to the present configuration example performs the above-described operation, that is, “every time elapsed until the occurrence of an event for transition from one time point to another state is detected. In addition to the time independent mode in which the operation of outputting the final detection result signal Q indicating true is performed if the time change of the output signal from the filter unit 2 matches a predetermined pattern, the time dependent mode is also used. When it is possible to operate and is set to time-dependent mode, it is possible to transition to the next state only when an occurrence of an event for transitioning to another state is detected during a predetermined detection period. .

  Specifically, the register 21 according to the present configuration example indicates, for each filter unit 2, whether the determination unit 13 corresponding to the filter unit 2 operates in the time independent mode or the time dependent mode. A TimeIndep flag is stored. When the TimeIndep flag indicates that the time independent mode is operated, the determination unit 13 corresponding to the filter unit 2 operates as described above and can operate in the time independent mode.

  The register 21 stores SQ_Time data, a TimeRdnBf flag, and a TimeRdnAf flag for each filter unit 2. The SQ_Time data indicates the start time of a period (monitoring period) in which the determination unit 13 corresponding to the filter unit 2 monitors the output of the filter unit 2. In this configuration example, for example, the time counter 26 The start time is described by the count value. The end point of the monitoring period is stored as the above-described EV_Time data.

  The TimeRdnBf flag and the TimeRdnAf flag indicate whether to initialize or ignore the pattern matching process when it is detected that the output of the filter unit 2 becomes true outside the monitoring period. The operation when the TimeRdnBf flag is detected before the monitoring period and the operation when the TimeRdnAf flag is detected after the monitoring period are shown.

  On the other hand, when the operation mode of the filter unit 2 corresponding to the determination circuit 24 is set to the time-dependent mode, the determination circuit 24 compares the SQ_Time data with the count value from the time counter 26, for example. Wait until the time indicated by The operations of the remaining circuits 21 to 23, 25, and 26 are the same as those in the time independent mode.

  Here, when the TimeRdnBf flag of the filter unit 2 corresponding to the determination circuit 24 indicates the initialization of the pattern matching process, the determination circuit 24 does not change the filter unit 2 until the time indicated by the SQ_Time data. When the output signal is monitored and the output signal becomes true, a true Match_Init signal can be output. On the other hand, when the TimeRdnBf flag indicates “ignore”, the determination circuit 24 keeps the Match_Init signal false until the time indicated by the SQ_Time data regardless of the output signal of the filter unit 2.

  On the other hand, at the time indicated by the SQ_Time data (when the monitoring period starts), the determination circuit 24 changes the true / false of the FilterOK signal according to the true / false of the output signal of the filter unit 2. Further, when the Sqce_Con data stored in association with the filter unit 2 and the initial state corresponding to the determination circuit 24 indicates true, the determination circuit 24 determines whether the determination unit 24 outputs true (false / false) according to the output signal (true / false) of the filter unit 2. The true / false of the Match_St signal can be changed. When the output signal of the filter unit 2 becomes true during the monitoring period, the determination circuit 24 can store the detection during the monitoring period in, for example, the register 21.

  Further, after the time point indicated by the SQ_Time data is reached, the determination circuit 24 measures the elapsed time from the time point by, for example, comparing the SQ_Time data with the current count value of the time counter 26. When it is determined that the output signal of the filter unit 2 is not true during the monitoring period, for example, by referring to the register 21 when the time indicated by the EV_Time data has elapsed, the time corresponding to the TimeRdnAf flag A Match_Init signal can be output. Specifically, when the TimeRdnAf flag indicates initialization, the determination circuit 24 outputs a true Match_Init signal, and when the TimeRdnAf flag indicates ignore, the determination circuit 24 outputs a false Match_Init signal. it can. Even if the TimeRdnAf flag indicates neglect, the determination circuit 24 outputs a true Match_Init signal if the state does not change even after a predetermined time has elapsed as a sufficiently long time. Thus, the matching processing unit 4 can be initialized.

  In the following, as an example, in FIG. 4, eight filter units 2 a to 2 h are provided. As a pattern, the following pattern, that is, each filter unit 2 that outputs a true signal is “filter” Part 2b and 2e "→" filter part 2d and 2g "→" filter part 2h "→" filter part 2a and 2f "→" filter part 2b "→" filter part 2h "→" filter parts 2a and 2c " A case where a time-varying pattern is registered will be described. In this case, the Sqce_Con data corresponding to the states S0 to S7 of the filter units 2a to 2h are set as shown in FIG. In this setting example, the filter units 2a, 2e, 2f and 2h are set in the time independent mode, and the remaining filter units 2b, 2c, 2d and 2g are set in the time dependent mode. Further, the TimeRdnAf flag and the TimeRdnBf flag of each filter unit 2 are set to values indicating initialization. In this setting example, the EV_Time and SQ_Time of each of the filter units 2a to 2h, and the determination circuit 24 are attached with the alphabetical character at the end of the corresponding filter unit 2 such as EV_Time_a of the filter unit 2a. Refer to it.

  Here, in the initial state S0 including the time point t0 shown in FIG. 5 and before the time point t1, the state counter 22 and the flip-flop 23 are reset. In this state, the determination circuits 24b and 24e in which the Sqce_Con data corresponding to the initial state S0 is set to true (1 in the example of FIG. 3) output a false FilterOK signal, and the remaining determination circuits 24a, 24c,. 24d and 24f to 24h output true FilterOK signals. In this state, each of the determination circuits 24a to 24h outputs a false Match_Init signal and a false Match_St signal.

  In this state, when the output signal of the filter unit 2e becomes true at time t0, the determination circuit 24e that monitors the output signal of the filter unit 2e sets the FilterOK signal and the Match_St signal to true.

  By this Match_St signal, the flip-flop 23 is set to true. Further, the time counter 26 is reset by the FilterOK signal, and the time counter 26 starts to measure the elapsed time from the time point t0. At time t0, even if the FilterOK signal of the determination circuit 24e becomes true, the FilterOK signal of the determination circuit 24b remains false, so the value of the state counter 22 remains a value indicating the initial state S0.

  Here, since the filter units 2b and 2e are set to require determination in the initial state S0, as described above, the count value of the time counter 26 is compared with the count value indicated by each EV_Time, and the time counter 26 It is determined whether or not the time indicated by each EV_Time has elapsed since the start of time measurement (from time t0).

  As described above, since the output signal of the filter unit 2e is already true at time t0, the determination circuit 24e keeps the Match_Init signal false even when the time indicated by EV_Time_e has elapsed. Here, since the output signal of the filter unit 2b is not true at the time t0, if the output signal of the filter unit 2b does not become true even after the time indicated by EV_Time_b has elapsed, the determination circuit 24b determines that the Match_Init Set the signal to true.

  On the other hand, in the example of FIG. 5, the output signal of the filter unit 2b becomes true at a time point t1 before that. Thereby, the determination circuit 24b sets the FilterOK signal and the Match_St signal to true. In this configuration example, the time counter 26 is reset again by the Match_St signal of the determination circuit 24b, and the time counter 26 starts to count the elapsed time from the time point t1.

  At time t1, since the FilterOK signal of the determination circuit 24b is also true, the state counter 22 is counted up, and the count value of the state counter 22 changes to a value indicating the state S1 next to the initial state S0. In this configuration example, since the state counter 22 is configured by a shift register, the count value changes from 00h to 01h.

  Here, among the filter units 2, the filter units 2a, 2e, 2f, and 2h are set in the time independent mode, and in the state S1, the determination is not required. Accordingly, the filter units 2a, 2e, 2f, and 2h maintain the FilterOK signal as true and the Match_Init signal and the Match_St signal as false during the state S1.

  On the other hand, among the filter units 2, the filter units 2b, 2c, 2d, and 2g are set to the time dependent mode, and the respective TimeRdnAf flag and TimeRdnBf flag are set to values indicating initialization. Therefore, the determination circuits 24b, 24c, 24d, and 24g corresponding to these compare the count value of the time counter 26 with the SQ_Time data set for each time until the time indicated by the SQ_Time data is reached. The output signal of the filter unit 2 corresponding to each is monitored. Therefore, if the output signal becomes true during this period, the Match_Init signal should be set to true. However, in the example of FIG. 5, the output signals of the filter units 2b, 2c, 2d, and 2g are all kept false until the time indicated by the SQ_Time data. Accordingly, each of the determination circuits 24b, 24c, 24d, and 24g maintains the Match_Init signal to be false.

  Further, in the state S1, since the filter units 2d and 2g among these filter units 2b, 2c, 2d and 2g are set as requiring determination, the determination circuits 24d and 24g output a false FilterOK signal, The remaining determination circuits 24b and 24c output a true FilterOK signal.

  After entering the state S1 at the time t1, when the time indicated by SQ_Time_d is reached, the determination circuit 24d starts measuring EV_Time_d. Similarly, at the time indicated by SQ_Time_g, the determination circuit 24g starts timing of EV_Time_g. Here, if the output signals of the filter units 2d and 2g corresponding to these EV_Times do not become true even when these EV_Times have elapsed, the determination circuits 24d and 24g should set the Match_Init signal to true. However, in the example of FIG. 5, the output signals of the filter units 2d and 2g become true before each EV_Time elapses. Therefore, the determination circuits 24d and 2g output the FilterOK signal while keeping the Match_Init signal false. Set to true. As a result, at the time t2 when both the FilterOK signals become true, the state counter 22 is incremented and changes to a value indicating the state S2 next to the initial state S1. In the present configuration example, the count value of the state counter 22 changes from 01h to 03h.

  In this state S2, since only the determination circuit 24h is set to require determination, only the determination circuit 24h sets the FilterOK signal to false, and the remaining determination circuit 24 sets the FilterOK signal to true. In addition, the determination circuit 24h set to the time independent mode measures the elapsed time since the transition to the state S2, and the output signal of the filter unit 2h does not become true until the time indicated by EV_Time_h elapses. , Set Match_Init signal to true. However, in the example of FIG. 5, since the output signal of the filter unit 2h is true before the time indicated by EV_Time_h has elapsed, at that time t3, the FilterOK signal becomes true and the state counter 22 is counted up. The

  Each of the above operations is repeated until the final state S7 is reached. Specifically, in the time independent mode, the determination circuit 24 that is set to require determination in that state is in the time dependent mode until the time indicated by EV_Time has elapsed since the change to that state. In this case, when the output signal of the filter unit 2 becomes true from the time indicated by SQ_Time until the time indicated by EV_Time elapses, the FilterOK signal is set to true, and in that state, the determination is set to be necessary. When all of the FilterOK signals from the determination circuit 24 become true, the state counter 22 is counted up to a value indicating the next state.

  In the final state S7, the control circuit 25 of the matching processing unit 4 changes the final detection result signal Q to true. In the case of this configuration example, in the final state S7, the count value of the state counter 22 becomes 7Fh, so that the control circuit 25 of the matching processing unit 4 has the count value of the state counter 22 at this value. When the output signal of the AND circuit 25a becomes true, the final detection result signal Q is changed to true.

  Thereby, the matching processing unit 4 can determine whether or not the time change of the output signal from each filter unit 2 matches a predetermined pattern stored in the register 21.

  Next, the low-pass filter 3 and the band-pass filter 11 of each filter unit 2 shown in FIG. 1 will be described in detail with reference to FIGS. In other words, in the present embodiment, these filters are realized by FIR digital filters.

The output Y (t) of the FIR digital filter is an input signal input every predetermined period (sampling period etc.) in order from the oldest, x (t−n + 1), x (t−n + 2), ..., x (t-1), x (t), the order of the filter is n, an arbitrary integer from 0 to n-1 is i, and each filter coefficient constituting the filter coefficient sequence of the filter is h (i ), As shown in the following equation (1):
Y (t) = Σ [h (i) · x (t−n + 1 + i)] (1)
It becomes. In the above formula (1), Σ is the total in [] when i is changed from 0 to n−1. N is an even number.

In the present embodiment, using the symmetry of the filter coefficient in the filter coefficient sequence, the above equation (1) is expressed as the following equation (2):
Y (t) = Σ [h (j) · (x (t−n / 2 + 1 + j)
+ X (t−n / 2−j))] (2)
It is transformed and calculated. In the above formula (2), j is an arbitrary integer from 0 to n / 2-1 and Σ is the total in [] when j is changed from 0 to n / 2-1. It is.

  Furthermore, as shown in FIG. 6, the FIR filter 31 according to the present embodiment prepares two memories 32 and 33, and one of the memories (for example, the memory 32) includes an input signal that is input for each period. The second half (newer half) of the input signal train is stored, and the first half (older half) is stored in the other (in this case, the memory 33). In this case, the memory 32 becomes the second half memory circuit described in the claims, and the memory 33 becomes the first half memory circuit.

  Further, the FIR filter 31 includes an adder 34 for adding the values read from the memories 32 and 33, a coefficient register 35 for storing the filter coefficient sequence, and the coefficients read from the coefficient register 35 and the adder 34. A product-sum circuit (product-sum operation circuit) 36 that outputs a value (product-sum operation result) obtained by accumulating the multiplication result with the output value, and a control circuit 37 that controls them are provided.

  Note that, as described above, the FIR filter 31 according to the present embodiment operates according to the above equation (2), and the coefficient register 35 stores the coefficient sequence of length n / 2 (the above equation (2)). h (j)) is stored. Further, the product-sum circuit 36, for example, as shown in FIG. 7, adds a multiplier 36a that multiplies two values to be multiplied, and adds, for example, its own output value and the output value of the multiplier 36a. And an accumulator 36b for accumulating the multiplication result of the multiplier 36a.

  The control circuit 37 inputs the oldest input signal sequence stored in the memory 32 to the memory 33 every time an input signal is newly input. Note that when a new input signal is input, the oldest input of the memory 33 is no longer used for computation, so the area storing this input signal may be overwritten. Thus, regardless of which input signal is input, the memory 32 stores the latter half of the input signal sequence (x (t−n / 2 + 1) to x (t) in the above equation (2)). Then, the memory 33 stores the first half of the input signal sequence (x (t−n + 1) to x (t−n / 2) in the above equation (2)). As an example, in the present embodiment, the memories 32 and 33 are implemented as ring buffers provided on the RAM, as will be described in detail later.

  In addition, the control circuit 37 is configured so that the adder 34 and the product-sum circuit 36 are equal to the number of times of the sequence length of the coefficient sequence stored in the coefficient register 35 (n / 2 times) for each input period of the input signal. It controls to perform each calculation.

  More specifically, the control circuit 37 sequentially reads the input signals x (t−n / 2 + 1) to x (t) from the memory 32 and supplies them to one input terminal of the adder 34. Note that the read cycle (calculation cycle) Tc is set to satisfy Tc ≦ Ti / (n / 2), where Ti is the input cycle of the input signal.

  Further, the control circuit 37 sequentially reads the input signals x (t−n / 2) to x (t−n + 1) from the memory 33 in synchronization with the reading from the memory 32, and the other of the adders 34. Is given to the input terminal. As a result, x (t−n / 2 + 1 + j) and x (t−n / 2−j) are input to the adder 34 in each calculation cycle, and the adder 34 receives x (( t−n / 2 + 1 + j) + x (t−n / 2−j) can be output. Note that j is an integer from 0 to n / 2-1 and is set to a different value in different calculation cycles. As an example, the control circuit 37 according to the present embodiment reads each input signal from both the memories 32 and 33 so that j increases by 1 from 0 to n / 2-1 every calculation cycle.

  Further, the control circuit 37 reads out the filter coefficient h (j) corresponding to j used in calculating the output of the adder 34 from the coefficient register 35 in synchronization with the output of the adder 34 and reads the product-sum circuit. 36 is input.

  Further, each time an input signal is input (every input cycle Ti), the control circuit 37 clears the accumulation result of the accumulator 36b shown in FIG. The product-sum operation result of 36 is cleared to zero. Further, for example, every time the multiplication result is output from the multiplier 36a shown in FIG. 7, the control circuit 37 adds the multiplication result from the multiplier 36a to the accumulated value so far, to the accumulator 36b. For example, the product-sum operation is instructed to the product-sum circuit 36. Thus, when the product-sum circuit 36 performs the product-sum operation for all j, the output value of the product-sum circuit 36 is Y (t).

  Here, the low-pass filter 3 and the band-pass filter 11 shown in FIG. 1 may be configured separately from each other as the FIR filter 31 shown in FIG. 7, but in this embodiment, the memory 32 used for the low-pass filter 3 is used. 33 and the adder 34 are also used as the memories 32 and 33 and the adder 34 when the band pass filter 11 processes the input signal without going through the low pass filter 3. As a result, as will be described in detail later, it is possible to limit the places that need to operate at high speed in the circuit and reduce the power consumption of the entire circuit.

  Specifically, as shown in FIG. 8, the low-pass filter 3 according to the present embodiment is provided with members 42 to 47 similar to the members 32 to 37 shown in FIG. The bandpass filter 11 of the filter unit 2 is also provided with members 52 to 57 similar to the members 32 to 37 shown in FIG. In the figure, for convenience of explanation, a control circuit including the control circuit 47 and the control circuit 57 of each filter unit 2 and low-pass filter 3 is illustrated as a control circuit 61.

  However, in the detection system 1 according to the present embodiment, a switch 62 is provided between the adder 54 and the product-sum circuit 56, and the switch 62 includes an output value of the adder 44 and an output value of the adder 54. Can be selected and applied to the product-sum circuit 56. The control circuit 61 can switch the switch 62 according to whether or not the bandpass filter 11 performs downsampling.

  Further, in the present embodiment, the members 42 to 44 and 52 to 54 are provided in common between the filter units 2. A coefficient register 45 and a product-sum circuit 46 are also provided in common between the filter units 2. Thereby, the circuit scale can be greatly reduced as compared with the case where these are provided independently for each filter unit 2.

  On the other hand, among the members 52 to 57, the coefficient register 55 and the product-sum circuit 56 are provided independently for each filter unit 2. Therefore, each filter unit 2 can set each filter coefficient sequence independently of each other without any trouble, and can determine whether or not to down-sample independently of each other.

  In the above configuration, the control circuit 61 switches the switch 62 of the bandpass filter 11 that is set to downsample among the bandpass filters 11 to the adder 54 side. In FIG. 8, as an example, the bandpass filters 11a and 11c of the filter units 2a and 2c are set to downsample, and the switches 62a and 62c of the bandpass filters 11a and 11c are connected to the adder 54 side. It has been switched.

  In this case, as shown in FIG. 9, the low-pass filter 3 is formed by the members 42 to 46, and the high frequency component of the sampled input signal can be removed. In FIG. 9 and FIG. 10 (described later), the signal path or circuit that is not selected is indicated by a broken line.

  The output signal of the low-pass filter 3 (the output signal of the product-sum circuit 46) is supplied to the band-pass filter 11 formed by the members 52 to 56, and the memories 52 and 53 sequentially store the output signals. . However, since the band-pass filter 11 is down-sampled, the control circuit 61 operates the band-pass filter 11 at the frequency at the time of down-sampling. Therefore, the output signals of the low-pass filter 3 are stored in the memories 52 and 53 every cycle longer than the normal cycle. As an example, at the time of downsampling, when sampling at a normal 1/4 frequency, the memories 52 and 53 store the output value of the output signal of the low-pass filter 3 every four times. In addition, since the input period Ti of the bandpass filter 11 is extended more than usual, the calculation period Tc of the bandpass filter 11 is also extended accordingly.

  As a result, the band-pass filter 11 can pass the signal component without significantly increasing the length of the filter coefficient sequence even when the signal component of the low frequency band is passed.

  On the other hand, the control circuit 61 switches the switch 62 to the adder 44 side for the bandpass filter 11 that is not set to downsampling among the bandpass filters 11. In the example of FIG. 8, since the band pass filter 11b of the filter unit 2b is set not to downsample, the switch 62b of the band pass filter 11b is switched to the adder 44 side.

  In this case, as shown in FIG. 10, the bandpass filter 11 is formed by the members 42 to 44 and the members 55 to 56, and the bandpass filter 11 is a signal in a desired frequency band set by the filter coefficient series. Only the components can be passed.

  Here, in this case, the control circuit 61 operates the bandpass filter 11 at the normal frequency. Therefore, the calculation cycle Tc of the band pass filter 11 is set shorter than that in the case of downsampling.

  As shown in FIG. 8, the band-pass filters 11a and 11c for down-sampling and the band-pass filter 11b not for down-sampling are mixed, but the calculation cycle when the memories 42 and 43 and the adder 44 are operated. Tc is set to a value corresponding to the normal frequency. Therefore, if the subsequent product-sum circuits 46 and 56 operate in synchronization with each other at the calculation cycle Tc, even if the memories 42 and 43 and the adder 44 are shared, the low-pass filter 3 and the downsampling are not performed. The band pass filter 11b can operate without any trouble.

  Here, as a comparative example, instead of the switch 62, a configuration in which one of the input signal not passing through the low-pass filter 3 and the output signal of the low-pass filter 3 is selected and input to the band-pass filter 11 is provided. When not down-sampling, the memories 52 and 53 of the band-pass filter 11 store an input signal not passing through the low-pass filter 3.

  In this configuration, in preparation for the case where the low-pass filter 3 is not used, the operation speeds of the memories 52 and 53 and the adder 54 of the band-pass filter 11 need to be set so that they can operate even at a normal frequency.

  On the other hand, in the present embodiment, by providing the switch 62, the bandpass filter 11 when the memories 42 and 43 and the adder 44 process the input signal without using the lowpass filter 3 and the lowpass filter 3. The memories 52 and 53 and the adder 54 are used as the band-pass filter 11 at the time of downsampling. As a result, unlike the comparative example, even if the operation speeds of the memories 52 and 53 and the adder 54 are set to be slow enough to operate at the frequency at the time of downsampling, the bandpass filter 11 operates correctly. Can do. Therefore, it is possible to limit the portions that need to operate at high speed in the circuit, and to reduce power consumption of the entire circuit.

  Hereinafter, an example of a configuration for forming a ring buffer in the memories 32 and 33 will be described. That is, as shown in FIG. 11, the FIR filter 1 according to this configuration example includes a data delay circuit 102 including memories 32 and 33, a coefficient register 35, an adder 34, a multiplier 36a, and an accumulation circuit 36b. A product-sum circuit 36.

  The data delay circuit 102 includes a RAM-DF 121 as the memory 32, a RAM-DS 122 as the memory 33, and address control circuits 123 and 124 and a control circuit 125 that constitute the control circuit 37.

  The RAM-DF 121 and the RAM-DS 122 constitute a delay unit, and read input data sequentially input in a designated order as will be described later, thereby providing input data delayed for a predetermined time to a product-sum operation described later. . The RAM-DF 121 and the RAM-DS 122 each have a storage capacity for storing a maximum of m / 2 (m is an even number) input data, and a total of m input data can be stored. . Each storage area for storing input data in the RAM-DF 121 and the RAM-DS 122 corresponds to a delay element in the delay unit.

  The address control circuit 123 is a circuit that controls output of addresses for writing to and reading from the RAM-DF 121. The address control circuit 123 includes an input pointer (in-pointer F in the figure) 231, an output pointer (out-pointer F in the figure) 232, a read pointer (rd-pointer F in the figure) 233, and an input number counter 234. And a selector 235.

  The input pointer 231 is a circuit (address pointer) that changes an address for designating an area in which external input data is written in the RAM-DF 121, and is constituted by a counter, for example. The input pointer 231 is loaded with an address value (for example, address 0) of an area in which input data to be input first is written in advance, and the address is counted when the input data is input to the RAM-DF 121 for the first time. The address is incremented by one each time input data is input. Therefore, the most recently input data is stored in the RAM-DF 121 area specified by the address output from the input pointer 231.

  The output pointer 232 is a circuit (address pointer) that generates an address for designating an area from which input data written in the RAM-DF 121 is read, and is constituted by a counter, for example. The output pointer 232 is loaded with an address value (for example, address 0) in which input data to be input first is written in advance, and the address is incremented by one each time input data is read. Therefore, the input data input first is stored in the area of the RAM-DF 121 specified by the address output by the output pointer 232.

  The read pointer 233 is a circuit (address pointer) that generates an address for designating an area from which the input data is read when the input data written in the RAM-DF 121 is subjected to addition by the adder 34. It is configured. The read pointer 233 is loaded with the address from the output pointer 232, and increments the address by one each time input data is read. As a result, the address output by the read pointer 233 changes so that the input data written later is sequentially read one by one from the input data written first in the RAM-DF 121.

  The input number counter 234 counts the number of input data (input pulse number) input to the RAM-DF 121. The input number counter 234 counts up when it counts k pieces (2k is the order n of the FIR filter 31), which is the prescribed data input number of the RAM-DF 121.

  The selector 235 is a circuit that selects and outputs one of the addresses output from the input pointer 231, the output pointer 232, and the read pointer 233, and supplies the selected address to the RAM-DF 121. The selector 235 outputs the address from the input pointer 231 until the input number counter 234 counts up the input of k pieces of input data to the RAM-DF 121. Further, when the input number counter 234 counts up as described above, the selector 235 switches the output so that the address from the output pointer 232 and the address from the input pointer 231 are alternately output one by one. Thus, when one input data is read from the RAM-DF 121 to the RAM-DS 22, the operation of writing one new input data to the RAM-DF 121 is repeated. Further, when the input number counter 243 described later counts up the input of k pieces of input data to the RAM-DS 122, the selector 235 outputs k addresses corresponding to the k pieces of input data from the read pointer 233. After that, the output switching is repeated so that one address from the input pointer 231 is output. Thereby, the operation of reading k pieces of input data from the RAM-DF 121 and the operation of writing one new input data to the RAM-DF 121 are repeated.

  The address control circuit 124 is a circuit that controls output of addresses for writing to and reading from the RAM-DS 122. The address control circuit 124 includes an input pointer (in-pointer S in the figure) 241, a read pointer (rd-pointer S in the figure) 242, an input number counter 243, and a selector 244.

  The input pointer 241 is a circuit (address pointer) that generates an address for designating an area in which input data read from the RAM-DF 121 is written in the RAM-DS 22 and is configured by an n-ary counter, for example. The input pointer 241 is preloaded with the address value (for example, address 0) of the area in which input data to be input first is written in advance, and when input data is first input to the RAM-DS 122, that is, the number of inputs Each time input data is input when the counter 234 counts up, the address is incremented by one. Therefore, the most recently input data is stored in the RAM-DS 122 area designated by the address output from the input pointer 241.

  The read pointer 242 is a circuit (address pointer) that generates an address for designating an area from which the input data is read when the input data written in the RAM-DS 122 is subjected to addition by the adder 34. It is configured. The read pointer 242 is loaded with the address from the input pointer 241 and decrements the address by one each time input data is read. As a result, the address output by the read pointer 242 changes so that the input data written earlier is sequentially read one by one from the input data written last in the RAM-DS 122.

  The input number counter 243 counts the number of input data (input pulse number) input to the RAM-DS 122. The input number counter 243 counts up when k data, which is the specified data input number of the RAM-DS 122, are counted.

  The selector 244 is a circuit that selects and outputs one of the addresses output from the input pointer 241 and the read pointer 242 and supplies the selected address to the RAM-DS 122. The selector 244 outputs the address from the input pointer 241 until the input number counter 243 counts up the input of k pieces of input data to the RAM-DS 122. Further, when the input number counter 243 counts up as described above, the selector 244 outputs k addresses individually corresponding to k input data from the read pointer 242, and then sets the address from the input pointer 241 to 1. Repeatedly switching the output to output one. Thereby, the operation of reading k input data from the RAM-DS 122 and the operation of writing one input data output from the RAM-DF 121 to the RAM-DS 122 are repeated.

  The control circuit 125 is a circuit that controls operations of the RAM-DF 121, the RAM-DS 122, and the address control circuits 123 and 124. The control circuit 125 permits writing and reading to the RAM-DF 121 and the RAM-DS 122 in accordance with output control of the following addresses.

The control circuit 125 performs the following controls (1) to (6) for the address control circuit 123.
(1) In accordance with the input of the first input data to the RAM-DF 121, an instruction to start counting is given to the input number counter 234, and an instruction to start outputting the address is given to the input pointer 231.
(2) The selector 235 is instructed to output the address from the input pointer 231 between when the input number counter 234 starts counting the number of input data and when it counts up.
(3) When the input number counter 234 counts up, after giving an instruction to stop the output of the address to the input pointer 231, to give an instruction to output one address to the output pointer 232, Repeat giving instructions to output one address.
(4) When the input number counter 234 counts up, the selector 235 is instructed to alternately output the address from the output pointer 232 and the address from the input pointer 231 one by one.
(5) When the input number counter 234 counts up, an instruction for outputting k addresses to the read pointer 233 and an instruction for outputting one address to the input pointer 231 are repeated.
(6) When the input number counter 243 counts up, the selector 235 is instructed to alternately output k addresses from the read pointer 233 and one address from the input pointer 231.

The control circuit 125 performs the following controls (7) to (10) for the address control circuit 124.
(7) When the input number counter 234 counts up, the input number counter 243 is instructed to start counting in accordance with the input of the first input data to the RAM-DS 122, and the input pointer 231 is instructed to start outputting the address. give.
(8) The selector 244 is instructed to output the address from the input pointer 241 between the time when the input number counter 243 starts counting the number of input data and the time when it counts up.
(9) When the input number counter 243 counts up, an instruction for outputting k addresses to the read pointer 242 and an instruction for outputting one address to the input pointer 241 are repeated.
(10) When the input number counter 243 counts up, the selector 244 is instructed to alternately output k addresses from the read pointer 242 and one address from the input pointer 241.

  The coefficient register 34 has a RAM-CE 131 and a read pointer 132.

  The RAM-CE 131 is provided for storing filter coefficients to be supplied to the multiplier 36a, and stores k filter coefficients input in advance from the outside, for example, the external register 107.

  The read pointer 132 is a circuit (address pointer) that generates an address for designating an area from which the filter coefficient is read when the filter coefficient stored in the RAM-CE 131 is supplied to the multiplier 36a. Has been. The read pointer 132 is loaded with a value (for example, address 0) of an address (first address) of an area in which a filter coefficient to be output first is stored in advance. One address is read each time the filter coefficient is read. Increment by one. As a result, the address output by the read pointer 132 changes so that the RAM-CE 131 sequentially reads one by one from the first filter coefficient.

  The adder 34 is a circuit that adds the input data read from the RAM-DF 121 and the input data read from the RAM-DS 122. The multiplier 36 a is a circuit that multiplies the addition data output from the adder 34 by the filter coefficient output from the RAM-CE 131.

  As described above, the accumulation circuit 36b is a circuit that accumulates k multiplication values continuously output from the multiplier 36a to obtain a filter output. The accumulation circuit 36 b includes an adder 161, a register 162, an output register 163, a processing number counter 164, and a comparator 165.

  The adder 161 is a circuit that adds the value output from the register 162 to the multiplication value output from the multiplier 36a.

  The register 162 is a circuit that holds the added value output from the adder 161. The register 162 is reset every time input data is newly input to the RAM-DF 121 after the addition process by the adder 34 is started.

  The output register 163 is a circuit that holds the output value of the register 162. The output register 163 outputs the output value held when the number of accumulation processes by the accumulation circuit 36b reaches k times as output data.

  The processing number counter 164 is a counter that counts the number of times the added data from the adder 161 is held before the register 162 is reset. The comparator 165 compares the count value of the processing number counter 164 with the specified number k, and gives a signal for outputting the output value held in the output register 163 when they match.

  The operation of the FIR filter 31 configured as described above will be described.

  First, in the initial state, input data is not written in the RAM-DF 121 and the RAM-DS 122. From this state, when input data is input to the RAM-DF 121, the input data is written in an area designated by an address (for example, address 0) given from the input pointer 231 via the selector 235. The input pointer 231 increments the address every time input data is input. Thereby, the input data is written in different areas of the RAM-DF 121 in the order of input. At this time, the number of input data input to the RAM-DF 121 is counted by the input number counter 234.

  In this way, when k pieces of input data (D1 to Dk) are written into the RAM-DF 121, the input number counter 234 counts up. As a result, the address from the output pointer 232 is given to the RAM-DF 121 via the selector 235. Then, the input data (D1) written in the RAM-DF 121 first is read out. The output pointer 232 increments the address when input data is read. Therefore, the input data (D2) designated by the address is read from the RAM-DF 121.

  On the other hand, in the address control circuit 124, the address from the input pointer 241 is given to the RAM-DS 122 via the selector 244, so in the RAM-DS 122, the area specified by the address is first read from the RAM-DF 121. The input data (D1) is written. Then, since the input pointer 241 increments the address, the input data (D2) read from the RAM-DF 121 is written next in the area of the RAM-DS 122 specified by the address. In this way, by repeating the reading of the input data from the RAM-DF 121 and the writing of the input data to the RAM-DS 122, the input data written to the RAM-DF 121 is moved to the RAM-DS 122. At this time, the number of input data input to the RAM-DS 122 is counted by the input number counter 243. In parallel with this operation, input data is also written to the RAM-DF 121 as described above.

  In this way, when k pieces of input data (D1 to Dk) from the RAM-DF 121 are written to the RAM-DS 122, the input number counter 243 counts up. Since new k pieces of input data (Dk + 1 to D2k) are also written in the RAM-DF 121, the input number counter 234 counts up. Thereby, reading of input data from the RAM-DF 121 and the RAM-DS 122 for use in the product-sum operation is started.

  At this time, the read pointer 233 is loaded with an address from the output pointer 232, and the address is given to the RAM-DF 121 via the selector 235. On the other hand, the read pointer 242 is loaded with an address from the input pointer 241, and the address is given to the RAM-DS 122 via the selector 244. Then, the input data (Dk + 1) written first in the RAM-DF 121 and the input data (Dk) written last in the RAM-DS 122 are read.

  The read pointer 233 increments the address when input data is read, while the read pointer 242 decrements the address when input data is read. Thereby, the input data (Dk + 2) written next to the input data (Dk + 1) is read from the RAM-DF 121, while the input data (Dk) written before the input data (Dk) is read from the RAM-DS 122. Dk-1) is read out. As described above, the increment of the address by the read pointer 233, the decrement of the address by the read pointer 242, and the reading of the input data from the RAM-DF 121 and the RAM-DS 122 by the designation of the obtained address are repeated.

  The two input data read from the RAM-DF 121 and the RAM-DS 122 are added by the adder 34 and input to the multiplier 36a. In the coefficient register 35, the filter coefficient is read by the address given from the read pointer 132. The two input data are multiplied by the filter coefficient from the corresponding RAM-CE 131 by the multiplier 36. The read pointer 131 increments the address every time the filter coefficient is read. Such addition and multiplication processes are repeatedly performed on two input data sequentially input to the adder 34.

  The upper limit result (multiplication data) output from the multiplier 36a is sequentially input to the accumulation circuit 36b. In the accumulation circuit 36 b, the adder 161 adds the output (addition data) from the register 162 to the input multiplication data and outputs the result to the register 162. Each time the addition data is output from the adder 161, the register 162 rewrites the held addition data with the latest addition data. Further, since the addition data held in the register 162 is output not only to the adder 161 but also to the output register 163, the output register 163 also holds the same addition data.

  On the other hand, the number of times the register 162 holds the addition data from the adder 161 is compared with k by the comparator 165. As a result of the comparison by the comparator 165, when the number of times of holding coincides with k (when the above multiplication data is accumulated), the addition data held in the output register 163 is output as output data. As described above, reading of input data from the RAM-DF 121 and RAM-DS 122, addition by the adder 34, multiplication by the multiplier 36a, and accumulation by the accumulation circuit 36b are repeated k times to obtain output data. Later, new input data is input to the RAM-DF 121. The register 162 and the output register 163 are reset by the input of this input data.

  The series of k times of reading, adding, multiplying and accumulating the input data is completed before the next input data is input to the RAM-DF 21. For this reason, the control circuit 25 controls the timing so that each process of reading, adding, multiplying and accumulating input data is performed during one clock of the clock, and each process proceeds in a pipeline manner. For example, the first data read is performed in the first period, and the second data read and the first read data are added in the second period. In the subsequent third period, the third data read, the second read data addition, and the first addition data multiplication are performed. In a further subsequent fourth period, the fourth data read, the third read data addition, the second addition data multiplication, and the first accumulation are performed. By performing such pipeline processing, even a circuit having a relatively slow operation can execute k product-sum operations while input data is input to the RAM-DF 121.

  As described above, by performing the above-described series of arithmetic processing k times, a product-sum operation is performed on 2k pieces of input data read from the RAM-DF 121 and the RAM-DS 122. When new input data is input to the FIR filter 1, the input data is written into the RAM-DF 121 according to the address designation of the input pointer 234 as described above. At the same time, the input data written first in the RAM-DF 121 is read by addressing by the pointer 232 and written and transferred to the RAM-DS 122. Therefore, the writing and transfer of the input data and the same series of arithmetic processing as the above arithmetic processing for new 2k input data are completed until the next input of force data to the RAM-DF 121 is performed.

  When the input data is written, the above-mentioned k product-sum operations are performed on the 2k input data stored in the RAM-DF 121 and the RAM-DS 122 including the newest input data. At this time, the earliest input data (oldest) written in the RAM-DS 122 used in the previous product-sum operation is not used (discarded) in the product-sum operation. In this way, the filter processing is realized by adding the newest input data and repeating the product-sum operation on 2k input data excluding the oldest input data used in the previous product-sum operation.

  As described above, the FIR filter 31 according to the present configuration example is based on continuous k pieces of input data stored in the two RAM-DF 121 and RAM-DS 122 (which are also continuous between the RAM-DF 121 and the RAM-DS 122). The input data to be multiplied by the filter coefficients having a symmetrical relationship is read out one by one and added by the adder 34, and the addition result is multiplied by the filter coefficient by the multiplier 36a. The data is calculated and the sum is calculated by the accumulation circuit 36b. As a result, the FIR filter 31 capable of halving the number of multiplication processes using the symmetry of the filter coefficient can be configured by a digital circuit using a RAM such as the RAM-DF 121 and the RAM-DS 122. . Therefore, the FIR filter 31 can be easily configured with an application specific integrated circuit (AISC) or a field programmable gate array (FPGA).

  In the FIR filter 31 according to this configuration example, the write position and the read position are changed by the input pointer 231, the output pointer 232, and the read pointer 233 in the RAM-DF 121, and the input pointer 241 and the read pointer are changed in the RAM-DS 122. The writing position and the reading position are changed by 242. Thereby, the RAM-DF 121 and the RAM-DS 122 function as a ring buffer that writes and reads input data at an arbitrary position. Therefore, by setting the upper limit of the total number of input data that can be stored in each of the RAM-DF 121 and the RAM-DS 122 as m / 2 ≧ n / 2 (m and n are even numbers), By changing the address ranges defined by the input pointers 231 and 241, the output pointer 232, and the read pointers 233 and 242, the filter order n (filter length) can be arbitrarily set.

  By the way, the detection system 1 according to the present embodiment not only outputs the final detection result signal Q, but also has a configuration for confirming from outside whether or not it is operating normally.

  Specifically, as shown in FIG. 12, the detection system 1 according to the present embodiment includes a signal generator 71 that generates an audio signal having a predetermined waveform, and an input selector 72. The input selector 72 outputs the audio signal input from the outside or the output signal of the signal generator 71 according to the instruction of the control circuit 61 described above to the low-pass filter 3 and the band-pass filter 11 (in the example of FIG. 43).

  As a result, an audio signal having a predetermined waveform is input to the low-pass filter 3 and the band-pass filter 11, and the final detection result signal Q at that time is confirmed to determine whether or not the detection system 1 is operating correctly. Can be verified.

  Further, the detection system 1 according to the present embodiment can output not only the final detection result signal Q but also the signals of the respective units. Specifically, the detection system 1 is provided with an output selector 73, which outputs an audio signal input from the outside or an output signal of the low-pass filter 3 in accordance with an instruction from the control circuit 61. Can be output to terminal Tout. Further, in the detection system 1 according to the present embodiment, one of the output signals of the bandpass filter 11 of each filter unit 2 is selected according to the instruction of the control circuit 61 and is output to the output selector 73. The output selector 73 can also select the output of the filter selector 74.

  Here, the output signal of the band-pass filter 11 that has been down-sampled and the output signal of the band-pass filter 11 that has not been down-sampled or the output signal of the low-pass filter 3 have different frequencies. On the other hand, when the DA converter connected to the outside of the output terminal Tout is converted into an analog signal and the waveform is to be observed with, for example, an oscilloscope, the DA converter is only required to change the operating frequency. For simplification, when the DA converter tries to DA convert both output signals at the latter frequency, the output signal of the band-pass filter 11 down-sampled is up-sampled.

  Even in this case, the detection system 1 according to the present embodiment includes a low-pass filter (output-side low-pass filter) 75 that removes the high-frequency component of the output signal of the output selector 73 so that the occurrence of aliasing errors can be suppressed. An output switch 76 is provided that selects one of the output signal of the low-pass filter 75 or the output signal of the output selector 73 in accordance with an instruction from the control circuit 61 and outputs the selected signal to the output terminal Tout.

  The low-pass filter 75 is also constituted by an FIR digital filter, and includes members 32 to 37 shown in FIG. Furthermore, in the present embodiment, as shown in FIG. 13, the coefficient register 35 of the low-pass filter 75 is shared with the coefficient register 35 (45) of the low-pass filter 3. Thereby, the circuit scale and power consumption can be reduced as compared with the case where each is provided separately.

  In addition, each member of the low-pass filter 75 operates at a normal frequency similarly to each member of the low-pass filter 3. The cut-off frequencies of the low-pass filter 75 and the low-pass filter 3 are set to be the same. Therefore, even if the coefficient register 35 is shared with the coefficient register 35 (45) of the low-pass filter 3, the low-pass filter 75 can block the high-frequency component without any trouble.

  In the above configuration, when the output selector 75 selects the down-sampled output signal of the bandpass filter 11 and the output switch 76 selects the output signal of the low-pass filter 75 according to the instruction of the control circuit 61, the output terminal Tout The downsampled output signal of the bandpass filter 11 is output after passing through the lowpass filter 75.

  Therefore, even when a circuit connected to the outside of the output terminal Tout up-samples the output signal of the band-pass filter 11 that has been down-sampled, the occurrence of aliasing errors can be suppressed without increasing the circuit scale. .

  In the above description, a case has been described in which each member of the detection system 1 is realized by a hardware circuit such as an adder or a multiplier without using software, but the present invention is not limited to this. You may implement | achieve all or one part of each member with the combination of the program for implement | achieving the function mentioned above, and the hardware (computer) which performs the program.

  In any case, if it is possible to determine whether or not the time change of the output signal from each filter unit 2 (more specifically, the determination result of each determination unit 13) matches a predetermined pattern. As with the detection system 1 described above, the occurrence of abnormality can be accurately detected.

  However, when each of the FIR digital filters is realized by a combination of software and a computer, it is necessary to set the operating frequency of the computer to be significantly high in order to perform each calculation at the calculation cycle Tc, which greatly increases power consumption. Will increase. Therefore, when a reduction in power consumption is required, it is preferable to implement the hardware circuit as described above.

  In the above description, the FIR digital filter 31 is provided with the two memories 32 and 33, and the addition is executed prior to the multiplication to reduce the number of repetitions to n / 2. However, the present invention is not limited to this. It is not a thing. For example, only one memory may be provided, and multiplication and accumulation may be repeated n times.

  In the above, in order to determine whether the time change of the output signal from each filter unit 2 (more specifically, the determination result of each determination unit 13) matches a predetermined pattern, Although the structure which provides the some filter part 2 in parallel was demonstrated, it does not restrict to this.

  Even in these cases, when the bandpass filter arithmetic circuit operates in the normal frequency, the low-pass filter storage circuit instead of the bandpass filter memory, when the bandpass filter operates at a normal frequency. If the configuration is such that the product-sum operation result of the digital value stored in the filter and the filter coefficient of the bandpass filter is calculated, it is possible to limit the places that need to operate at high speed, and to reduce the circuit scale of the entire digital filter circuit. Power consumption can be reduced without much increase.

  Further, instead of / in addition to the configuration, when the bandpass filter operates at a frequency at the time of downsampling, the input side and output side lowpass filters respectively remove high frequency components from the input signal and output signal of the bandpass filter. If the coefficient register of the input-side low-pass filter is a coefficient register of the output-side low-pass filter, power consumption can be reduced without significantly increasing the circuit scale of the entire digital filter circuit.

  In the above description, the audio signal processing has been described as an example, but the present invention is not limited to this. As long as the signal can be converted into an electric waveform, the same effect can be obtained even with a signal indicating vibration, the rotational frequency of the motor, or the like.

  It can be used widely and suitably for anomaly detection devices including a band pass filter as well as a detection system for detecting abnormal noise.

1, showing an embodiment of the present invention, is a block diagram illustrating a main configuration of a detection system. FIG. It is a block diagram which shows the principal part structure of the whole control system containing the programmable display provided with the said detection system. It is a circuit diagram which shows the principal part structure of the matching process part provided in the said detection system. It is a figure which shows an example of the Sqce_Con data stored in the register of the said matching process part. It is a timing chart which shows operation | movement of the said detection system. It is a block diagram which shows the principal part structure of the digital FIR filter provided in the said detection system. It is a block diagram which shows the structural example of the product-sum circuit provided in the said digital FIR filter. It is a block diagram which shows the structural example of the said detection system, and shows the bandpass filter and the low-pass filter vicinity. It is operation | movement of the said structural example, and is a block diagram which shows the state which the band pass filter is down-sampling. FIG. 10 is a block diagram illustrating the operation of the above configuration example, and illustrating a state in which the bandpass filter is operating at a normal frequency. It is a block diagram which shows the structural example of the said digital FIR filter. It is a block diagram which shows the signal generator, selector, and output side low pass filter which were provided in the said detection system. It is a block diagram which shows the structural example of the said output side low pass filter.

Explanation of symbols

1 Programmable display (abnormality detection device)
3 Low-pass filter (input-side low-pass filter)
4 Matching processing part (matching processing means)
11 Band pass filter 32, 42, 52 Memory (second half memory circuit; memory circuit)
33.43.53 Memory (first half memory circuit; memory circuit)
34/44/54 Adder (arithmetic circuit)
35 ・ 45 ・ 55 Coefficient register (arithmetic circuit)
36/46/56 multiply-add circuit (product-sum operation circuit; operation circuit)
62 switch

Claims (6)

A plurality of bandpass filters connected in parallel to each other and removing signal components other than a predetermined passband from the input signal,
And a matching processing means for detecting whether or not an abnormality has occurred depending on whether or not the time change of the output signal of each bandpass filter matches a predetermined pattern. Anomaly detection device. The matching processing means can set one or a plurality of states as a state to be passed from an initial state to a final state where a pattern match is detected as the pattern,
In the matching processing means, the output of a predetermined bandpass filter among the plurality of bandpass filters exceeds a threshold as an event necessary for transitioning to the next state for each state. The abnormality detection device according to claim 1, wherein   3. The matching processing means, as the pattern, is associated with each of the states, and can set a time until an event for transitioning to the next state occurs after transitioning to the state. The abnormality detection device described.   If the matching processing means detects an event for transitioning to the next state at a timing deviating from the pattern, whether or not to return to the initial state can be preset for each band-pass filter. The abnormality detection device according to claim 2 or 3. The band pass filter can switch the operating frequency to a first frequency and a second frequency lower than the first frequency,
Furthermore, when the operating frequency of the abnormality detecting device is set to the first frequency and the operating frequency of the bandpass filter is the second frequency, a high frequency component of a signal input to the bandpass filter is detected. An input-side low-pass filter to be removed is provided,
Each of the filters constitutes a storage circuit that stores digital values periodically input at the operating frequency by the order of the filter, a digital value stored in the storage circuit, and a filter coefficient sequence of the filter A digital FIR filter comprising an arithmetic circuit for calculating a product-sum operation result with the filter coefficient
When the bandpass filter operates at the first frequency, the arithmetic circuit of the bandpass filter replaces the storage circuit of the bandpass filter with the digital value and the band stored in the storage circuit of the input-side lowpass filter. The abnormality detection apparatus according to claim 1, wherein a product-sum operation result with a filter coefficient of a pass filter is calculated. The input signal is an audio signal,
The abnormality detection device according to any one of claims 1 to 5, wherein the abnormality detection device detects an abnormal sound generated from a device in a programmable display.

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