JPH04373179A - Voltage regulator diode - Google Patents

Voltage regulator diode

Info

Publication number
JPH04373179A
JPH04373179A JP17737091A JP17737091A JPH04373179A JP H04373179 A JPH04373179 A JP H04373179A JP 17737091 A JP17737091 A JP 17737091A JP 17737091 A JP17737091 A JP 17737091A JP H04373179 A JPH04373179 A JP H04373179A
Authority
JP
Japan
Prior art keywords
semiconductor layer
semiconductor
breakdown voltage
conductivity type
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17737091A
Other languages
Japanese (ja)
Other versions
JP3018608B2 (en
Inventor
Yasuhiko Ochiai
落合 康彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3177370A priority Critical patent/JP3018608B2/en
Publication of JPH04373179A publication Critical patent/JPH04373179A/en
Application granted granted Critical
Publication of JP3018608B2 publication Critical patent/JP3018608B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent irregularity of breakdown voltage of a voltage regulator diode in a semiconductor wafer surface, and improve yield. CONSTITUTION:The title diode has a first semiconductor layer having the same conductivity type as a semiconductor substrate 1, on the semiconductor substrate having a conductivity type, and a second semiconductor layer 4 having a conductivity type opposite to the substrate 1, on the first semiconductor layer, and the breakdown voltage is obtained by a PN junction of the first and the second semiconductor layers. The breakdown voltage is determined by the impurity concentration of the first semiconductor layer 2 formed by a deposition method. Almost uniform distribution of impurity concentration can be obtained in the semiconductor wafer surface. Thereby irregularity of resistivity can be restrained and irregularity of breakdown voltage is reduced.

Description

【発明の詳細な説明】[Detailed description of the invention] 【産業上の利用分野】[Industrial application field]

【0001】本発明は定電圧ダイオードに関し、特に半
導体ウェハース面内における降伏電圧のバラツキによる
ダイオードの品質低下を防止した定電圧ダイオードに関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant voltage diode, and more particularly to a constant voltage diode that prevents deterioration in diode quality due to variations in breakdown voltage within the plane of a semiconductor wafer.

【0002】0002

【従来の技術】図3は従来から知られている定電圧ダイ
オードの縦断面図である。N型半導体基板21を高温処
理して、N型半導体基板21上に全面にシリコン熱酸化
膜23を形成させた後、フォトレジストにより選択的に
拡散窓を形成する。次に、ボロンをドープしたシリコン
をN型基板21上全面に成長させた後、周辺部をプラズ
マ処理によりエッチングし、P+ 型半導体層22を得
る。このとき、拡散窓内で半導体基板21に接する部分
では単結晶層として構成される。その後、DHD(do
uble heatsink diode)容器に封入
するための電極として、P+ 型半導体層22上にメッ
キ法によりAgバンプ電極25を形成し、更にN型半導
体基板21の裏面にはAg電極26を形成する。
2. Description of the Related Art FIG. 3 is a longitudinal sectional view of a conventionally known constant voltage diode. After the N-type semiconductor substrate 21 is subjected to high-temperature treatment to form a silicon thermal oxide film 23 on the entire surface of the N-type semiconductor substrate 21, diffusion windows are selectively formed using photoresist. Next, silicon doped with boron is grown over the entire surface of the N-type substrate 21, and then the peripheral portion is etched by plasma processing to obtain a P+-type semiconductor layer 22. At this time, the portion in contact with the semiconductor substrate 21 within the diffusion window is configured as a single crystal layer. After that, DHD (do
An Ag bump electrode 25 is formed by plating on the P+ type semiconductor layer 22 as an electrode for sealing in the container (heatsink diode), and an Ag electrode 26 is further formed on the back surface of the N type semiconductor substrate 21.

【0003】このようにして製造される定電圧ダイオー
ドは、主として降伏電圧が7V以上のものであり、降伏
時の電流電圧特性を改善(ツェナーブレークダウン領域
の降伏波形をハードにする)するためのものである。こ
の定電圧ダイオードの降伏電圧はN型半導体基板21と
P+ 型半導体層22で形成されたP+ N接合の濃度
勾配に依存する。
The voltage regulator diodes manufactured in this way mainly have a breakdown voltage of 7 V or more, and are designed to improve the current-voltage characteristics at breakdown (harden the breakdown waveform in the Zener breakdown region). It is something. The breakdown voltage of this constant voltage diode depends on the concentration gradient of the P+N junction formed by the N-type semiconductor substrate 21 and the P+-type semiconductor layer 22.

【0004】0004

【発明が解決しようとする課題】上述した従来の定電圧
ダイオードでは、降伏電圧を決定する要因は、P+ N
接合の濃度勾配に依存しており、これは低不純物濃度側
のN型半導体基板21の不純物濃度により決定される。 しかしながら、通常の半導体基板の製造に際し、例えば
、リンをドープした抵抗率が0.005Ω・cm(この
場合の降伏電圧は約5Vとなる)の半導体ウェハースを
、CZ法にて3インチの口径で引き上げた場合、半導体
ウェハース面内の不純物濃度のバラツキは約6〜15%
程度あり、不純物濃度による抵抗率は半導体ウェハース
の周囲が高く、中央部が低いといった分布となる。この
抵抗率のバラツキが、そのまま半導体ウェハース面内の
各箇所で夫々形成される定電圧ダイオードの各降伏電圧
のバラツキとなり、所定の降伏電圧の定電圧ダイオード
を得るための歩留が低下されるという問題を有している
。本発明の目的は半導体ウェハース面内における降伏電
圧のバラツキを防止し、所要の降伏電圧を得る際の歩留
りを改善した定電圧ダイオードを提供することにある。
[Problems to be Solved by the Invention] In the conventional voltage regulator diode described above, the factor that determines the breakdown voltage is P+N
It depends on the concentration gradient of the junction, which is determined by the impurity concentration of the N-type semiconductor substrate 21 on the low impurity concentration side. However, when manufacturing normal semiconductor substrates, for example, a phosphorus-doped semiconductor wafer with a resistivity of 0.005 Ωcm (the breakdown voltage in this case is approximately 5V) is processed into a 3-inch diameter semiconductor wafer using the CZ method. When pulled up, the variation in impurity concentration within the semiconductor wafer surface is approximately 6 to 15%.
The resistivity depending on the impurity concentration has a distribution such that it is high at the periphery of the semiconductor wafer and low at the center. This variation in resistivity causes variation in the breakdown voltage of each voltage regulator diode formed at each location within the surface of the semiconductor wafer, reducing the yield for obtaining a voltage regulator diode with a predetermined breakdown voltage. I have a problem. An object of the present invention is to provide a constant voltage diode that prevents variations in breakdown voltage within the plane of a semiconductor wafer and improves the yield when obtaining a required breakdown voltage.

【0005】[0005]

【課題を解決するための手段】本発明の定電圧ダイオー
ドは、一導電型を有する半導体基板上に半導体基板と同
じ導電型の第1半導体層を有し、かつこの第1半導体層
上に異なる導電型を有する第2半導体層を有し、これら
第1及び第2の半導体層のPN接合により降伏電圧を得
るようにする。第1及び第2の半導体層は、ポリシリコ
ンを成長させかつ単結晶化した半導体層で構成する。
[Means for Solving the Problems] A constant voltage diode of the present invention has a first semiconductor layer of the same conductivity type as the semiconductor substrate on a semiconductor substrate having one conductivity type, and has a different conductivity type on the first semiconductor layer. A second semiconductor layer having a conductivity type is provided, and a breakdown voltage is obtained by a PN junction between the first and second semiconductor layers. The first and second semiconductor layers are formed by growing polysilicon and making it a single crystal semiconductor layer.

【0006】[0006]

【作用】本発明によれば、降伏電圧は堆積法で形成した
第1半導体層の不純物濃度によって決定されるので、半
導体ウェハース面内において略均一な不純物濃度分布に
でき、抵抗率のバラツキを抑制して降伏電圧のバラツキ
を小さくする。
[Operation] According to the present invention, since the breakdown voltage is determined by the impurity concentration of the first semiconductor layer formed by the deposition method, it is possible to achieve a substantially uniform impurity concentration distribution within the semiconductor wafer surface, suppressing variations in resistivity. to reduce variations in breakdown voltage.

【0007】[0007]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明による定電圧ダイオードの第1実施例
の縦断面図である。5Vの降伏電圧を得ようとした場合
、抵抗率が 0.005Ω・cmを有するN型半導体基
板1上に、N型半導体基板1と同じ導電型となるように
リンを添加したシリコンを堆積し、全面に厚さ2μmの
N+ 型の第1半導体層2を形成する。その後、CVD
法によりプラズマ窒化膜3を 1.5μm形成し、フォ
トレジストにより選択的に窓あけを行う。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a longitudinal sectional view of a first embodiment of a constant voltage diode according to the present invention. When trying to obtain a breakdown voltage of 5V, silicon doped with phosphorus is deposited on an N-type semiconductor substrate 1 having a resistivity of 0.005 Ωcm so that it has the same conductivity type as the N-type semiconductor substrate 1. , an N+ type first semiconductor layer 2 having a thickness of 2 μm is formed over the entire surface. After that, CVD
A plasma nitride film 3 with a thickness of 1.5 μm is formed by the method, and windows are selectively opened using photoresist.

【0008】次に、ボロンを添加したシリコンを堆積さ
せてP+ 型の第2半導体層4を形成する。この第2半
導体層4はプラズマ窒化膜3の窓内で第1半導体層2に
接する部分が単結晶化される。その後、周囲をプラズマ
処理してエッチングする。更に、DHD容器に封入する
ための電極として第2半導体層4上にメッキ法によりA
gバンプ電極5を形成し、かつN型半導体基板1の裏面
にAg電極6を形成する。
Next, boron-doped silicon is deposited to form a P+ type second semiconductor layer 4. The second semiconductor layer 4 is formed into a single crystal at a portion in contact with the first semiconductor layer 2 within the window of the plasma nitride film 3. Thereafter, the surrounding area is plasma-treated and etched. Further, A is formed by plating on the second semiconductor layer 4 as an electrode for sealing in the DHD container.
A G bump electrode 5 is formed, and an Ag electrode 6 is formed on the back surface of the N-type semiconductor substrate 1.

【0009】この構成の定電圧ダイオードによれば、降
伏電圧は、第1半導体層2と第2半導体層4とで形成さ
れたP+ /N+ 接合の不純物濃度が低濃度側の第1
半導体層2の抵抗率によって決定される。第1半導体層
2は堆積法によって形成しているため、その半導体ウェ
ハース面内の抵抗率のバラツキは、約4〜10%となり
、従来の定電圧ダイオードに比べて降伏電圧のバラツキ
が小さくなる。
According to the constant voltage diode having this configuration, the breakdown voltage is the lower the impurity concentration of the P+/N+ junction formed by the first semiconductor layer 2 and the second semiconductor layer 4, the lower the impurity concentration.
It is determined by the resistivity of the semiconductor layer 2. Since the first semiconductor layer 2 is formed by a deposition method, the variation in resistivity within the plane of the semiconductor wafer is about 4 to 10%, and the variation in breakdown voltage is smaller than that of a conventional constant voltage diode.

【0010】図2は本発明の第2実施例の縦断面図であ
る。N型半導体基板11上にリンをドープしたシリコン
を全面に形成し、かつ周囲をプラズマ処理によりエッチ
ングすることで、同じ導電型を有するN+ 型の第1半
導体層12を形成する。次に、ボロンをドープしたシリ
コンを全面に形成し、周囲をプラズマ処理でエッチング
することでP+ 型の第2半導体層14を形成する。こ
のとき、第1半導体層12上では第2半導体層14は単
結晶化される。更に、全面にプラズマ窒化膜13を厚さ
 1.5μmで形成し、DHD容器に封入するための電
極として第2半導体層14上にメッキ法によりAgバン
プ電極15を形成し、かつN型半導体基板11の裏面に
Ag電極16を形成する。
FIG. 2 is a longitudinal sectional view of a second embodiment of the present invention. By forming silicon doped with phosphorus over the entire surface of the N-type semiconductor substrate 11 and etching the periphery by plasma treatment, an N+-type first semiconductor layer 12 having the same conductivity type is formed. Next, silicon doped with boron is formed over the entire surface, and the periphery is etched by plasma processing to form a P+ type second semiconductor layer 14. At this time, the second semiconductor layer 14 is made into a single crystal on the first semiconductor layer 12. Furthermore, a plasma nitride film 13 with a thickness of 1.5 μm is formed on the entire surface, an Ag bump electrode 15 is formed by plating on the second semiconductor layer 14 as an electrode for sealing the DHD container, and an N-type semiconductor substrate is formed. An Ag electrode 16 is formed on the back surface of 11.

【0011】この実施例では、第1及び第2の半導体層
12,14のP+/N+ 接合と、半導体基板11と第
2の半導体層14のP+ /N接合との2つの接合部が
存在するが、P+ /N+ 接合の方が降伏電圧が低く
、かつ第1半導体層12は堆積法によって形成するため
、半導体ウェハース面内の抵抗率のバラツキを抑制し、
第1実施例と同様に降伏電圧のバラツキを小さくするこ
とができる。又、P+ /N接合はガードリングとして
作用する。 更に、プラズマ窒化膜13はAgバンプ電極15を形成
する時のマスクとして用いられるため、フォトレジスト
による窓あけ工程が1回少なくて済む等の、第1実施例
では得られなかった効果も得られる。
In this embodiment, there are two junctions: a P+/N+ junction between the first and second semiconductor layers 12 and 14, and a P+/N junction between the semiconductor substrate 11 and the second semiconductor layer 14. However, since the P+/N+ junction has a lower breakdown voltage and the first semiconductor layer 12 is formed by a deposition method, variations in resistivity within the semiconductor wafer surface are suppressed,
Similar to the first embodiment, variations in breakdown voltage can be reduced. Also, the P+/N junction acts as a guard ring. Furthermore, since the plasma nitride film 13 is used as a mask when forming the Ag bump electrodes 15, it is possible to obtain effects that could not be obtained in the first embodiment, such as requiring one less window opening process using photoresist. .

【0012】0012

【発明の効果】以上説明したように、本発明による定電
圧ダイオードは、その降伏電圧は、第1半導体層の抵抗
率によって決定され、その抵抗率の半導体ウェハース面
内のバラツキが約4〜10%と、従来の半導体基板の抵
抗率のバラツキ約6〜15%に比べ小さいため、所要の
降伏電圧の歩留が向上するといった効果を有する。
As explained above, in the constant voltage diode according to the present invention, the breakdown voltage is determined by the resistivity of the first semiconductor layer, and the variation in the resistivity within the semiconductor wafer surface is approximately 4 to 10. %, which is smaller than the variation in resistivity of about 6 to 15% in conventional semiconductor substrates, which has the effect of improving the yield of the required breakdown voltage.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の定電圧ダイオードの第1実施例の縦断
面図である。
FIG. 1 is a longitudinal cross-sectional view of a first embodiment of a constant voltage diode of the present invention.

【図2】本発明の定電圧ダイオードの第2実施例の縦断
面図である。
FIG. 2 is a longitudinal cross-sectional view of a second embodiment of the voltage regulator diode of the present invention.

【図3】従来の定電圧ダイオードの一例の縦断面図であ
る。
FIG. 3 is a longitudinal cross-sectional view of an example of a conventional constant voltage diode.

【符号の説明】[Explanation of symbols]

1,11  N型半導体基板 2,12  第1半導体層(N+ 型)3,13  プ
ラズマ窒化膜 4,14  第2半導体層(P+ 型)5,15  A
gバンプ電極 6,16  Ag電極
1, 11 N-type semiconductor substrate 2, 12 First semiconductor layer (N+ type) 3, 13 Plasma nitride film 4, 14 Second semiconductor layer (P+ type) 5, 15 A
g bump electrode 6, 16 Ag electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  一導電型を有する半導体基板上に、半
導体基板と同じ導電型の第1半導体層を有し、かつこの
第1半導体層上に異なる導電型を有する第2半導体層を
有し、これら第1及び第2の半導体層のPN接合により
降伏電圧を得ることを特徴とした定電圧ダイオード。
1. A first semiconductor layer having the same conductivity type as the semiconductor substrate on a semiconductor substrate having one conductivity type, and a second semiconductor layer having a different conductivity type on the first semiconductor layer. , a constant voltage diode characterized in that a breakdown voltage is obtained by a PN junction between these first and second semiconductor layers.
【請求項2】  第1及び第2の半導体層は、ポリシリ
コンを成長させかつ単結晶化した半導体層で構成してな
る請求項1の定電圧ダイオード。
2. The constant voltage diode according to claim 1, wherein the first and second semiconductor layers are formed by growing polysilicon and making it a single crystal.
JP3177370A 1991-06-22 1991-06-22 Constant voltage diode and its manufacturing method Expired - Lifetime JP3018608B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3177370A JP3018608B2 (en) 1991-06-22 1991-06-22 Constant voltage diode and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3177370A JP3018608B2 (en) 1991-06-22 1991-06-22 Constant voltage diode and its manufacturing method

Publications (2)

Publication Number Publication Date
JPH04373179A true JPH04373179A (en) 1992-12-25
JP3018608B2 JP3018608B2 (en) 2000-03-13

Family

ID=16029770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3177370A Expired - Lifetime JP3018608B2 (en) 1991-06-22 1991-06-22 Constant voltage diode and its manufacturing method

Country Status (1)

Country Link
JP (1) JP3018608B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014050422A1 (en) * 2012-09-27 2014-04-03 ローム株式会社 Chip diode and method for manufacturing same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014050422A1 (en) * 2012-09-27 2014-04-03 ローム株式会社 Chip diode and method for manufacturing same
CN104508806A (en) * 2012-09-27 2015-04-08 罗姆股份有限公司 Chip diode and method for manufacturing same
KR20150060664A (en) * 2012-09-27 2015-06-03 로무 가부시키가이샤 Chip diode and method for manufacturing same
JPWO2014050422A1 (en) * 2012-09-27 2016-08-22 ローム株式会社 Chip diode and manufacturing method thereof
US9653619B2 (en) 2012-09-27 2017-05-16 Rohm Co., Ltd. Chip diode and method for manufacturing same
US10903373B2 (en) 2012-09-27 2021-01-26 Rohm Co., Ltd. Chip diode and method for manufacturing same

Also Published As

Publication number Publication date
JP3018608B2 (en) 2000-03-13

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