JPS63138767A - Semiconductor substrate for vertical type semi-conductor device and manufacture thereof - Google Patents
Semiconductor substrate for vertical type semi-conductor device and manufacture thereofInfo
- Publication number
- JPS63138767A JPS63138767A JP61285479A JP28547986A JPS63138767A JP S63138767 A JPS63138767 A JP S63138767A JP 61285479 A JP61285479 A JP 61285479A JP 28547986 A JP28547986 A JP 28547986A JP S63138767 A JPS63138767 A JP S63138767A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- semiconductor
- type
- conductivity type
- impurities
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- 239000000758 substrate Substances 0.000 title claims abstract description 67
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000012535 impurity Substances 0.000 claims abstract description 59
- 238000009792 diffusion process Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 15
- 229910052710 silicon Inorganic materials 0.000 abstract description 15
- 239000010703 silicon Substances 0.000 abstract description 15
- 239000007858 starting material Substances 0.000 abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 30
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 235000012431 wafers Nutrition 0.000 description 12
- 229910052785 arsenic Inorganic materials 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052787 antimony Inorganic materials 0.000 description 4
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明はショットキバリヤ形半導体装置、縦形MOS
FET、縦形バイポーラトランジスタ等の縦形半導体
装置に用いられる半導体基体およびその製造方法に関す
るもので、特に縦形半導体装置の性能を向上することが
できるとともにコストの低減を図ることができる技術に
関するものである。Detailed Description of the Invention (Industrial Application Field) The present invention relates to a Schottky barrier type semiconductor device, a vertical MOS
The present invention relates to semiconductor substrates used in vertical semiconductor devices such as FETs and vertical bipolar transistors, and methods for manufacturing the same, and particularly to techniques that can improve the performance of vertical semiconductor devices and reduce costs.
(従来の技術)
縦形半導体装置の内、例えば大電力用ショットキバリア
形ダイオードは、特にスイッチング電源用の整流素子と
して広く用いられており、その高速性能は極めて優れて
いる。しかしながら、その価格は必ずしも安価とは言え
ない。ショットキバリア形ダイオードの価格が高くなる
のは、そのシリコン基体のコストが高いことが要因の一
つとなっている。一般的に、定格性能の内、順方向電圧
■、と逆方向電圧■□が重要な特性となっている。(Prior Art) Among vertical semiconductor devices, for example, high-power Schottky barrier diodes are widely used, especially as rectifying elements for switching power supplies, and their high-speed performance is extremely excellent. However, the price cannot necessarily be called cheap. One of the reasons for the high price of Schottky barrier diodes is the high cost of their silicon substrates. Generally, among the rated performance, forward voltage (■) and reverse voltage (■□) are important characteristics.
そこで従来のショットキバリア形ダイオードにおいては
シリコン基体としてnオンn9構造のエピタキシャルウ
ェファを用い、n゛構造拡散係数が小さい不純物、例え
ば砒素を高濃度でドープして形成している。Therefore, in a conventional Schottky barrier diode, an epitaxial wafer with an n-on-n9 structure is used as a silicon substrate, and the silicon substrate is doped with an impurity having a small diffusion coefficient of the n' structure, such as arsenic, at a high concentration.
第4図は従来のショットキバリア形ダイオードの構成を
示すもので、n型不純物である砒素を高濃度にドープし
たn°型シリコン基板1の上に比抵抗が0.5〜1Ω−
1のn型エピタキシャルN2が5〜7μ鶴の厚さに堆積
されてnオンn゛構造の半導体基体が構成されている。FIG. 4 shows the structure of a conventional Schottky barrier diode, in which a specific resistance of 0.5 to 1 Ω-
An n-type epitaxial layer N2 of No. 1 is deposited to a thickness of 5 to 7 μm to form a semiconductor substrate having an n-on-n structure.
このエピタキシャル層2の表面には5000〜8000
人の厚いシリコン酸化膜3が熱酸化により形成されてい
る。The surface of this epitaxial layer 2 has 5,000 to 8,000
A thick silicon oxide film 3 is formed by thermal oxidation.
このシリコン酸化膜3をフォトエツチング技術によって
選択的に除去し、周縁にテーバが付けられた開口部3a
が活性領域の位置に形成されている。This silicon oxide film 3 is selectively removed by photoetching to form an opening 3a with a tapered periphery.
is formed at the location of the active region.
この開口部を覆うようにシリコン酸化膜3上にはモリブ
デン等のバリアメタル膜4が、例えば2000人程度O
4さに形成されており、さらにその上にアルミニウムl
i!5が約8μmの厚さに形成され、さらにこのアルミ
ニウム膜上にワイヤ6がボンディングされている。また
、シリコン基板lの裏面には裏面電極膜7が形成されて
いる。A barrier metal film 4 made of molybdenum or the like is formed on the silicon oxide film 3 so as to cover this opening.
4, and on top of that is an aluminum plate.
i! 5 is formed to have a thickness of about 8 μm, and a wire 6 is further bonded onto this aluminum film. Further, a back electrode film 7 is formed on the back surface of the silicon substrate l.
(発明が解決しようとする問題点)
上述した従来の半導体基体1.2において、n゛型半導
体基板1の不純物濃度が、0.01Ω−値の比抵抗を与
える濃度以上である場合には、厚みが400μm程度と
厚くなってもショットキバリア形ダイオードの順方向電
圧■、に悪影響を及ぼすことはなかった。しかしながら
、このよ・うなn3型半導体基板1を結晶引上げ法によ
って形成するためには、高濃度であるためにウェファの
直径を大きくすることが困難であり、従来では3〜4イ
ンチのウェファを得るのが限界であった。n0型半導体
基板1の不純物濃度を下げることによって、直径の大き
なウェファを製造することは可能となるが、不純物濃度
が低くなるとV、が高(なる傾向にあるので、■rを必
要な値にまで低下させるためにはn0型半導体基板1上
に形成されるショットキバリア形ダイオードのチップ面
積を大きくしなければならず、それだけ歩留りが低下す
るとともにウニノア1枚当たりに形成することができる
チップ数が少なくなり、必然的にコストアップとなる欠
点があった。(Problems to be Solved by the Invention) In the conventional semiconductor substrate 1.2 described above, when the impurity concentration of the n'-type semiconductor substrate 1 is equal to or higher than the concentration that provides a specific resistance of 0.01Ω-value, Even when the thickness was increased to about 400 μm, there was no adverse effect on the forward voltage (2) of the Schottky barrier diode. However, in order to form such an N3 type semiconductor substrate 1 by the crystal pulling method, it is difficult to increase the diameter of the wafer due to the high concentration, and conventionally, a wafer of 3 to 4 inches is obtained. was the limit. By lowering the impurity concentration of the n0 type semiconductor substrate 1, it is possible to manufacture a wafer with a larger diameter. However, as the impurity concentration decreases, V tends to become high. In order to reduce the number of chips that can be formed per Uninoa, the chip area of the Schottky barrier diode formed on the n0 type semiconductor substrate 1 must be increased. This has the disadvantage of inevitably increasing costs.
上述したような問題は大電力用ショットキバリア形ダイ
オードだけでなく、大電力MO5FETや大電力バイポ
ーラトランジスタのような縦形半導体装置におけるオン
抵抗を低く保とうとするときに同様に現れるものである
。The above-mentioned problems appear not only in high-power Schottky barrier diodes, but also when trying to keep the on-resistance low in vertical semiconductor devices such as high-power MO5FETs and high-power bipolar transistors.
本発明の目的は、上述した従来の欠点を除去し、出発材
料としての半導体基板の不純物濃度を下げることによっ
て直径の大きなウェファを用いることができ、したがっ
て歩留りを向上し、コストを低減すことができ、しかも
半導体基体全体としての不純物濃度を高くすることによ
って順方向電圧vFを高くすることができ、その結果と
してチップ面積を小さくすることができ、1枚のウェフ
ァから多(のチップを得ることができる半導体基体およ
びその製造方法を提供しようとするものである。The object of the present invention is to eliminate the above-mentioned conventional drawbacks and to reduce the impurity concentration of the semiconductor substrate as a starting material, thereby making it possible to use wafers with larger diameters, thus increasing the yield and reducing costs. Moreover, by increasing the impurity concentration of the entire semiconductor substrate, the forward voltage vF can be increased, and as a result, the chip area can be reduced, making it possible to obtain multiple chips from one wafer. The purpose of this invention is to provide a semiconductor substrate that can be used as a semiconductor substrate and a method for manufacturing the same.
(問題点を解決するための手段および作用)本発明の半
導体基体は、縦形半導体装置に用いる半導体基体におい
て、一導電型の不純物を含む半導体基板と、この半導体
基板中に、その一方の表面から一導電型の不純物を深く
拡散して形成した第1半導体層と、この第1半導体層上
に形成され、前記第1半導体層に含まれる一導電型の不
純物よりも拡散係数が小さい一導電型の不純物を含む第
2半導体層と、この第2半導体層上に形成され、一導電
型の不純物を低濃度で含む第3半導体層とを具えること
を特徴とするものである。(Means and effects for solving the problem) The semiconductor substrate of the present invention is a semiconductor substrate used in a vertical semiconductor device, and includes a semiconductor substrate containing impurities of one conductivity type, and a semiconductor substrate containing an impurity of one conductivity type from one surface of the semiconductor substrate. a first semiconductor layer formed by deeply diffusing an impurity of one conductivity type; and a first semiconductor layer formed on the first semiconductor layer, the one conductivity type having a smaller diffusion coefficient than the impurity of the one conductivity type contained in the first semiconductor layer. The third semiconductor layer is formed on the second semiconductor layer and contains impurities of one conductivity type at a low concentration.
また、本発明による半導体基体の製造方法は、縦形半導
体装置に用いる半導体基体を製造するに当たり、一導電
型の不純物を含む半導体基板の両表面から一導電型の不
純物を高濃度で導入して第1および第2の半導体層を形
成する工程と、第1の半導体層の表面に、そこに含まれ
る不純物よりも拡散係数が小さい一導電型の不純物を含
む第1のエピタキシャル層を形成する工程と、このエピ
タキシャル層上に一導電型の不純物を低濃度で含む第2
のエピタキシャル層を形成する工程とを具えることを特
徴とするものである。Further, in the method for manufacturing a semiconductor substrate according to the present invention, when manufacturing a semiconductor substrate for use in a vertical semiconductor device, impurities of one conductivity type are introduced at high concentration from both surfaces of a semiconductor substrate containing impurities of one conductivity type. a step of forming a first epitaxial layer containing an impurity of one conductivity type whose diffusion coefficient is smaller than that of the impurity contained therein on the surface of the first semiconductor layer; , a second layer containing impurities of one conductivity type at a low concentration is formed on this epitaxial layer.
The method is characterized by comprising a step of forming an epitaxial layer.
このような本発明の半導体基体によれば、出発材料とし
ての半導体基板の不純物濃度はそれ程高くする必要はな
いので、例えば結晶引上げ法によっても直径の大きなウ
ェファを造ることができ、例えば5〜6インチと言った
大きなウェファを利用することができる。一方、この半
導体基板の表面に一導電型の不純物を深く拡散させるこ
とによって不純物濃度の高い第1半導体層が形成され、
さらにその上に拡散係数の小さい不純物を含む第2半導
体層が形成されているので、ショットキバリア形ダイオ
ードにおいては順方向電圧V、を十分小さくすることが
でき、また大電力用MOS FETにおいてはオン抵抗
を低く抑えることができる。According to such a semiconductor substrate of the present invention, since the impurity concentration of the semiconductor substrate as a starting material does not need to be so high, a wafer with a large diameter can be manufactured by, for example, a crystal pulling method. Large wafers such as inch can be used. On the other hand, a first semiconductor layer with a high impurity concentration is formed by deeply diffusing impurities of one conductivity type into the surface of this semiconductor substrate,
Furthermore, since a second semiconductor layer containing impurities with a small diffusion coefficient is formed on top of the second semiconductor layer, the forward voltage V can be made sufficiently small in a Schottky barrier diode, and the on-state voltage can be made sufficiently small in a high power MOS FET. Resistance can be kept low.
このように順方向電圧vFを小さくできるのでチップ面
積を小さくすることができ、大きなウェファを用いるこ
とと相俟って1枚のウェファからより多くのチップを形
成することができ、コストの低減を図ることができる。Since the forward voltage vF can be reduced in this way, the chip area can be reduced, and together with the use of a large wafer, more chips can be formed from a single wafer, reducing costs. can be achieved.
(実施例)
第1図(a)〜(dlは本発明による半導体基体の一実
施例を用いたショットキバリア形ダイオードの順次の製
造工程における構造を示す断面図である。(Example) FIGS. 1A to 1D are cross-sectional views showing the structure of a Schottky barrier diode in successive manufacturing steps using an example of a semiconductor substrate according to the present invention.
先ず出発材料として、n型の不純物を含み、厚さが30
0〜400μmのシリコン基板11を用意し、その上下
の表面からシリコン不純物を高濃度に拡散し、n゛型型
数散層12よび13を形成した様子を第1図(alに示
す。このリン拡散は150〜200μmの深さに行うが
、この際上下のn゛型型数散層12よび13が第1図4
a)に示すように互いに離れていてもよいが、両者が互
いに連結するようにした方がより望ましい。したがって
、以下の説明では両n゛型拡散層12および13が互い
に接触する程度までリンを深く拡散するものとする。First, as a starting material, a material containing n-type impurities and having a thickness of 30 mm is used.
A silicon substrate 11 with a diameter of 0 to 400 μm is prepared, and silicon impurities are diffused in high concentration from the upper and lower surfaces of the substrate to form n-type scattering layers 12 and 13, as shown in FIG. Diffusion is performed to a depth of 150 to 200 μm, and at this time, the upper and lower n-type scattering layers 12 and 13 are as shown in FIG.
Although they may be separated from each other as shown in a), it is more desirable that they are connected to each other. Therefore, in the following description, it is assumed that phosphorus is diffused deeply to the extent that both n-type diffusion layers 12 and 13 come into contact with each other.
次に、両n゛型拡散層12および13の表面から、リン
ネ鈍物よりも拡散係数の小さいn型不純物、例えば砒素
(^S)またはアンチモン(Sb)を拡散し、例えば厚
さが1〜4μm程度のn+4拡散層14および15を形
成する。n″0半導体層14および15は、砒素または
アンチモン等の拡散係数の小さい不純物を含む半導体層
をエピタキシャル成長させて形成することもできる。こ
の場合の不純物濃度は、リンネ鈍物を拡散して形成した
n゛型型数散層12よび13の濃度よりも高い方が好適
であるが、必ずしも高くする必要はなく、これと同程度
またはこれよりも幾分低くしてもよい。Next, an n-type impurity, such as arsenic (^S) or antimony (Sb), whose diffusion coefficient is smaller than that of Linnean obtuse, is diffused from the surfaces of both n-type diffusion layers 12 and 13, and the thickness of the n-type impurity is 1 to 1. N+4 diffusion layers 14 and 15 of about 4 μm are formed. The n″0 semiconductor layers 14 and 15 can also be formed by epitaxially growing a semiconductor layer containing an impurity with a small diffusion coefficient such as arsenic or antimony. Although it is preferable that the concentration be higher than that of the n-type scattering layers 12 and 13, it does not necessarily have to be higher, and may be about the same level or somewhat lower.
次に、一方のn9゛拡散層14の上に、例えば0.5〜
1.5Ω−国の比抵抗を与えるように不純物濃度を低く
したn−型エピタキシャル層16を約5〜8μmの厚さ
に堆積形成して半導体基体を完成した様子を第1図(C
1に示す。Next, on one of the n9'' diffusion layers 14, for example, 0.5~
Figure 1 (C
Shown in 1.
本例では上述したようにして形成した半導体基体を用い
てショットキバリア形ダイオードを形成するものであり
、このためにテーパ状の開口部を持つ絶縁膜17を形成
した後、その上にモリブデン(Mo)等のバリアメタル
層18とアルミニウム電極膜19とをそれぞれ3000
〜5000人および5〜7μm程度の厚さに形成し、さ
らに裏面に裏面電極膜20を形成した様子を第1図(d
lに示す。さらに通常のようにアルミニウム電極膜19
の上にワイヤをボンディングしてショットキバリア形ダ
イオードを完成する。In this example, a Schottky barrier diode is formed using the semiconductor substrate formed as described above, and for this purpose, after forming an insulating film 17 having a tapered opening, molybdenum (Mo) is formed on the insulating film 17. ), etc., and the aluminum electrode film 19, each having a thickness of 3000
Figure 1 (d
Shown in l. Furthermore, as usual, the aluminum electrode film 19
Bond a wire on top to complete the Schottky barrier diode.
このようにして得られるショットキバリア形ダイオード
の耐圧は約40〜60Vで、順方向電圧v7は170〜
20011vである。The Schottky barrier diode thus obtained has a breakdown voltage of about 40 to 60V, and a forward voltage v7 of 170 to 60V.
It is 20011v.
第2図(a)〜(d)は本発明による半導体基体の他の
実施例を用いてショットキバリア形ダイオードを形成す
る際の順次の工程における構造を示すものである0本例
では、出発材料として10”〜1019原子/■コの不
純物濃度を有するn゛型シリコン基板21を用意し、そ
の両表面から、拡散時間を短くするために拡散係数の大
きいn型不純物、例えばリンネ鈍物を高濃度に拡散して
101ゞ原子/ ell ’以上の高不純物濃度を有す
るn″0型拡散拡散層22び23を約250μIの深さ
に形成した様子を第2図+8)に示す。FIGS. 2(a) to 2(d) show the structure in the sequential steps of forming a Schottky barrier diode using another embodiment of the semiconductor substrate according to the present invention. In this example, the starting materials An n-type silicon substrate 21 having an impurity concentration of 10" to 1019 atoms/cm is prepared, and an n-type impurity with a large diffusion coefficient, such as Linnean blunt, is highly concentrated on both surfaces of the substrate to shorten the diffusion time. FIG. 2+8) shows how n''0-type diffusion layers 22 and 23 having a high impurity concentration of 101 atoms/ell' or more are formed to a depth of about 250 μI.
次に一方のn゛拡散層220表面に、リンネ鈍物よりも
拡散係数の小さい砒素またはアンチモン不純物を含むn
+゛型エピタキシャル層24を形成する。Next, on the surface of one of the n diffusion layers 220, an n
A +゛ type epitaxial layer 24 is formed.
このエピタキシャル層24の不純物濃度はn04型リン
拡散層22の不純物濃度よりも高濃度とするかまたは同
程度とすることができる。また、本例ではエピタキシャ
ル成長によってn++層24を形成したが、拡散または
イオン打込みによって形成してもよい。次に、n=型エ
ピタキシャル層24の上に、これよりも低不純物濃度で
、例えば0.5〜1.0Ω−ロの比抵抗を有するn型エ
ピタキシャル層25を5〜8μm程度の厚さに形成して
半導体基体を完成した様子を第2図山)に示す。The impurity concentration of this epitaxial layer 24 can be higher than or about the same as that of the n04 type phosphorus diffusion layer 22. Furthermore, although the n++ layer 24 is formed by epitaxial growth in this example, it may be formed by diffusion or ion implantation. Next, on the n = type epitaxial layer 24, an n type epitaxial layer 25 having a lower impurity concentration and a specific resistance of, for example, 0.5 to 1.0 Ω-R is formed to a thickness of about 5 to 8 μm. A completed semiconductor substrate is shown in Fig. 2 (Fig. 2).
次に、前例と同様にテーパを有する開口部を設けた酸化
膜26と、バリアメタル膜27と、金属電極膜28とを
順次に形成した様子を第2図(C)に示す。Next, as in the previous example, an oxide film 26 provided with a tapered opening, a barrier metal film 27, and a metal electrode film 28 are sequentially formed, as shown in FIG. 2(C).
さらに、ショットキバリア形ダイオードの順方向電圧V
Fを小さくするために、半導体基体の裏面を、例えばサ
ーフェイスグラインダまたはラッピングマシーンによっ
て削り取り、基板21の一部分と下側のn″0型拡散拡
散層23除去し、さらに裏面電極膜29を形成した様子
を第2図(d)に示す。Furthermore, the forward voltage V of the Schottky barrier diode
In order to reduce F, the back surface of the semiconductor substrate is scraped off using, for example, a surface grinder or a lapping machine, a part of the substrate 21 and the lower n''0 type diffusion layer 23 are removed, and a back electrode film 29 is further formed. is shown in FIG. 2(d).
第3図は本発明による半導体基体を用いて形成したショ
ットキバリア形ダイオードのさらに他の実施例を示すも
のである。本例では、リンネ鈍物を比較的多量に含むシ
リコン基板31を出発材料として用い、その上下の表面
に、リンネ鈍物よりも拡散係数が小さいn型不純物、例
えば砒素またはアンチモンを含むn−型エピタキシャル
層32および33を形成する。この場合、砒素またはア
ンチモンの不純物濃度はシリコン基板31の不純物濃度
よりも高くするのが望ましいが、それと同程度とするか
またはそれよりも幾分低くても差支えない。FIG. 3 shows still another embodiment of a Schottky barrier diode formed using the semiconductor substrate according to the present invention. In this example, a silicon substrate 31 containing a relatively large amount of Linnean obtuse is used as a starting material, and the upper and lower surfaces of the silicon substrate 31 contain n-type impurities having a smaller diffusion coefficient than the Linnean obtuse, such as arsenic or antimony. Epitaxial layers 32 and 33 are formed. In this case, it is desirable that the impurity concentration of arsenic or antimony be higher than the impurity concentration of the silicon substrate 31, but it may be about the same level or somewhat lower.
またこのn+1型層32.33は拡散法またはイオン注
入法によって形成することもできるが、この場合には不
純物濃度はシリコン基板の濃度よりも高くなる。さらに
、一方のn=型エピタキシャル層32の上に比抵抗を0
.5〜1.0Ω−国とした低不純物濃度のn型エピタキ
シャル層34を成長し、その上にテーパ付き開口部を有
する酸化膜35、バリアメタル膜36、金属電極膜37
を順次に形成する。さらに、本例ではシリコン基板31
の不純物濃度が高いので裏面を削り取ることなく裏面電
橋[38を形成する。このようにして形成したショット
キバリア形ダイオードの順方向電圧V、は十分に低いも
のとなる。このようにn″3型エピタキシャル層を堆積
形成するのは、ショットキバリア形ダイオードのように
高温の熱処理を必要としない場合に特に好適である。The n+1 type layers 32 and 33 can also be formed by a diffusion method or an ion implantation method, but in this case, the impurity concentration will be higher than that of the silicon substrate. Furthermore, a resistivity of 0 is applied on one of the n=type epitaxial layers 32.
.. An n-type epitaxial layer 34 with a low impurity concentration of 5 to 1.0 Ω is grown, and an oxide film 35 having a tapered opening, a barrier metal film 36, and a metal electrode film 37 are formed thereon.
are formed sequentially. Furthermore, in this example, the silicon substrate 31
Since the impurity concentration is high, the backside electric bridge [38] is formed without scraping off the backside. The forward voltage V of the Schottky barrier diode thus formed is sufficiently low. Depositing an n''3 type epitaxial layer in this manner is particularly suitable for a Schottky barrier diode that does not require high-temperature heat treatment.
以上の実施例では本発明の半導体基体をシ!17トキバ
リア形ダイオードに適用した場合について説明したが、
パワー805 PETまたはパワートランジスタ、SI
T等の他の縦形半導体装置に適用することもできる。In the above embodiments, the semiconductor substrate of the present invention is used. 17 We have explained the case where it is applied to a barrier type diode, but
Power 805 PET or power transistor, SI
It can also be applied to other vertical semiconductor devices such as T.
(発明の効果)
上述した本発明の半導体基体によれば、出発材料として
の半導体基板の不純物濃度は低いものであるから、5イ
ンチまたは6インチと言った直径の大きなウェファを結
晶引上げ法によって形成することができ、コストの低減
が図れる。また、縦形半導体装置としてショットキバリ
ア形ダイオードを形成する場合には、その順方向電圧V
Fを小さくでき、それだけチップ面積を小さくすること
ができる。したがって、上述したように大きなフエツチ
を利用できることと相俟って、1枚のウェファから多数
のチップを形成することができ、歩留りが向上し、さら
にコストを低減することができる。また、縦形半導体装
置としてパワーMOS FETを形成する場合にはオン
抵抗を低く抑えることができる利点がある。(Effects of the Invention) According to the semiconductor substrate of the present invention described above, since the impurity concentration of the semiconductor substrate as a starting material is low, a wafer with a large diameter of 5 inches or 6 inches can be formed by the crystal pulling method. It is possible to reduce costs. Furthermore, when forming a Schottky barrier diode as a vertical semiconductor device, its forward voltage V
F can be made smaller, and the chip area can be made smaller accordingly. Therefore, in combination with the availability of large fetches as described above, a large number of chips can be formed from a single wafer, improving yields and further reducing costs. Furthermore, when a power MOS FET is formed as a vertical semiconductor device, there is an advantage that the on-resistance can be kept low.
第1図(a)〜(d)は本発明による半導体基体の一実
施例を用いてショットキバリア形ダイオードを形成する
際の順次の製造工程における構造を示す断面図、
第2図fat〜(dlは同じその他の実施例を用いてシ
ョットキバリア形ダイオードを形成する際の順次の製造
工程における構成を示す断面図、第3図は本発明の半導
体基体のさらに他の実施例を用いて形成したショットキ
バリア形ダイオードの構成を示す断面図、
第4図は従来のショットキバリア形ダイオードの一例の
構成を示す断面図である。
11・・・n型シリコン基板 12.13・・・n゛型
型数散層1415・・・n〜型型数散
層6・・・n−型エピタキシャル層
17・・・酸化膜 1日・・・バリアメタル
膜工9・・・金属電極膜 20・・・裏面電極膜
21・・・n゛゛半導体基板 22.23・・・n+−
型拡散層24・・・n〜〜エピタキシャル層
25・・・n型エピタキシャル層
26・・・酸化膜27・・・バリアメタル膜28・・・
金属電極膜 29・・・裏面電極膜31・・・n
゛゛半導体基板
32.33・・・n〜〜エピタキシャル層34・・・n
型エピタキシャル層
35・・・酸化膜 36・・・バリアメタル
膜37・・・金属電極膜 38・・・金属電極膜
第1図
第2図
(a)1(a) to 1(d) are cross-sectional views showing the structure in sequential manufacturing steps when forming a Schottky barrier diode using an embodiment of the semiconductor substrate according to the present invention; 3 is a cross-sectional view showing the structure of a Schottky barrier diode formed in the sequential manufacturing process using another embodiment of the present invention, and FIG. A cross-sectional view showing the structure of a barrier type diode. FIG. 4 is a cross-sectional view showing the structure of an example of a conventional Schottky barrier diode. 11...n-type silicon substrate 12.13...n-type number Scattered layer 1415...n-type scattered layer 6...n-type epitaxial layer 17...oxide film 1st...barrier metal film 9...metal electrode film 20...back electrode Film 21...n゛゛Semiconductor substrate 22.23...n+-
Type diffusion layer 24...n~ Epitaxial layer 25...N type epitaxial layer 26...Oxide film 27...Barrier metal film 28...
Metal electrode film 29... Back electrode film 31...n
゛゛Semiconductor substrate 32, 33...n ~ Epitaxial layer 34...n
Type epitaxial layer 35...Oxide film 36...Barrier metal film 37...Metal electrode film 38...Metal electrode film Fig. 1 Fig. 2 (a)
Claims (1)
電型の不純物を含む半導体基板と、この半導体基板中に
、その一方の表面から一導電型の不純物を深く拡散して
形成した第1半導体層と、この第1半導体層上に形成さ
れ、前記第1導電体層に含まれる一導電型の不純物より
も拡散係数が小さい一導電型の不純物を含む第2半導体
層と、この第2半導体層上に形成され、一導電型の不純
物を低濃度で含む第3半導体層とを具えることを特徴と
する縦形半導体装置用半導体基体。 2、縦形半導体装置に用いる半導体基体において、一導
電型の不純物を含む半導体基板と、この半導体基板の両
表面に、前記不純物の拡散係数よりも小さい拡散係数を
有する一導電型の不純物を含むように形成された第1お
よび第2の半導体層と、第1の半導体層上に形成され、
一導電型の不純物を低濃度で含む第3の半導体層とを具
えることを特徴とする縦形半導体装置用半導体基体。 3、縦形半導体装置に用いる半導体基体を製造するに当
たり、一導電型の不純物を含む半導体基板の両表面から
一導電型の不純物を高濃度で導入して第1および第2の
半導体層を形成する工程と、 第1の半導体層の表面に、そこに含まれる不純物よりも
拡散係数が小さい一導電型の不純物を含む第1のエピタ
キシャル層を形成する工程と、 このエピタキシャル層上に一導電型の不純物を低濃度で
含む第2のエピタキシャル層を形成する工程とを具える
ことを特徴とする縦形半導体装置用半導体基体の製造方
法。[Claims] 1. In a semiconductor substrate used for a vertical semiconductor device, a semiconductor substrate containing an impurity of one conductivity type, and an impurity of one conductivity type formed by deeply diffusing into the semiconductor substrate from one surface thereof. a second semiconductor layer formed on the first semiconductor layer and containing an impurity of one conductivity type having a smaller diffusion coefficient than an impurity of one conductivity type contained in the first conductor layer; A semiconductor substrate for a vertical semiconductor device, comprising a third semiconductor layer formed on the second semiconductor layer and containing impurities of one conductivity type at a low concentration. 2. In a semiconductor substrate used for a vertical semiconductor device, a semiconductor substrate containing an impurity of one conductivity type, and a semiconductor substrate containing impurities of one conductivity type having a diffusion coefficient smaller than the diffusion coefficient of the impurity on both surfaces of the semiconductor substrate. first and second semiconductor layers formed on the first semiconductor layer;
1. A semiconductor substrate for a vertical semiconductor device, comprising: a third semiconductor layer containing impurities of one conductivity type at a low concentration. 3. When manufacturing a semiconductor substrate for use in a vertical semiconductor device, first and second semiconductor layers are formed by introducing impurities of one conductivity type at a high concentration from both surfaces of the semiconductor substrate containing impurities of one conductivity type. a step of forming, on the surface of the first semiconductor layer, a first epitaxial layer containing an impurity of one conductivity type whose diffusion coefficient is smaller than that of the impurity contained therein; A method for manufacturing a semiconductor substrate for a vertical semiconductor device, comprising the step of forming a second epitaxial layer containing impurities at a low concentration.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61285479A JPS63138767A (en) | 1986-11-29 | 1986-11-29 | Semiconductor substrate for vertical type semi-conductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61285479A JPS63138767A (en) | 1986-11-29 | 1986-11-29 | Semiconductor substrate for vertical type semi-conductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63138767A true JPS63138767A (en) | 1988-06-10 |
Family
ID=17692049
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61285479A Pending JPS63138767A (en) | 1986-11-29 | 1986-11-29 | Semiconductor substrate for vertical type semi-conductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63138767A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04261065A (en) * | 1991-01-29 | 1992-09-17 | Mitsubishi Electric Corp | Semiconductor device |
JP2005191247A (en) * | 2003-12-25 | 2005-07-14 | Nec Electronics Corp | Semiconductor substrate and semiconductor device using the same |
JP2008500744A (en) * | 2004-05-21 | 2008-01-10 | フェアチャイルド・セミコンダクター・コーポレーション | Semiconductor device having a spacer layer doped with less diffusing atoms than the substrate |
-
1986
- 1986-11-29 JP JP61285479A patent/JPS63138767A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04261065A (en) * | 1991-01-29 | 1992-09-17 | Mitsubishi Electric Corp | Semiconductor device |
JP2005191247A (en) * | 2003-12-25 | 2005-07-14 | Nec Electronics Corp | Semiconductor substrate and semiconductor device using the same |
JP2008500744A (en) * | 2004-05-21 | 2008-01-10 | フェアチャイルド・セミコンダクター・コーポレーション | Semiconductor device having a spacer layer doped with less diffusing atoms than the substrate |
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