JP2765867B2 - Dielectric separation substrate and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor integrated device (hereinafter referred to as an IC),
In particular, the present invention relates to a substrate suitable for a high-voltage, high-current power IC and a method for manufacturing the same.

[Conventional technology]

The conventional substrate is characterized in that no insulator is formed on the bottom surface, as described in Japanese Patent Application Laid-Open No. 60-80243, thereby preventing an increase in parasitic series resistance and further improving heat dissipation.

However, in this conventional example, when a vertical element is formed, it is necessary to take out electrodes from the back surface of the substrate, and when an IC is used, it is necessary to process the back surface or prepare a special package. There was.

[Problems to be solved by the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and reduce the resistance and improve the heat dissipation of a large current output element formed in a vertical single crystal region.

[Means for solving the problem]

The object is to provide a first region in which a vertical single crystal region is exposed on a front surface of a dielectric isolation substrate and a second region in which a vertical single crystal region is exposed on a front surface and a back surface of a dielectric isolation substrate and has a higher impurity concentration than the first region. This is achieved by having the following regions.

Further, the above object is to make the depth of the isolation trench surrounding the vertical single crystal region forming the output element deeper than the isolation trench surrounding other single crystal islands, and then remove the insulator to remove the high concentration Si layer. High concentration on the surface side of the substrate by depositing, grinding and polishing
This is achieved by exposing the Si region.

[Action]

According to the present invention, the electrode is formed by exposing the high-concentration region of the vertical single-crystal region forming the element to the surface of the substrate, so that the resistance is reduced and the bonding can be performed in the same manner as a normal IC.

〔Example〕

 Hereinafter, embodiments of the present invention will be described.

FIG. 1 (a) is a part of a plan view of a dielectric isolation substrate having a new structure, and FIG. 1 (b) is a sectional view taken along the line AA '.

The substrate is composed of a single crystal region 103 (single crystal island) electrically insulated and separated from the other by an insulator 102 formed along the separation groove 101 and a periphery of another single crystal island buried by Si deposition. A vertical single-crystal region 104 made of single-crystal Si from the front surface 110 to the back surface 120 of the substrate and a polycrystalline Si region 105 deposited on an insulator. The width of the exposed Si region exposed on the surface is
Is determined by the width of

Next, the manufacturing method of this embodiment will be described in order with reference to FIG.

First, an n-type (100) single crystal Si wafer 100 is oxidized to form an oxide film 99. The oxide film is partially removed by photoetching to provide an opening, and a V-shaped groove is formed with an alkaline etching solution. At this time, since the depth of the groove is determined by the width W of the opening of the oxide film, if the width is changed, a shallow groove 101 and a deep groove 108 can be formed (FIG. 7A).

Next, a buried layer (shown in Sez) is formed in a necessary portion,
An oxidized oxide film 102 is formed again. This oxide film is a separation oxide film for electrically insulating and separating the single crystal island. Next, the portion of the oxide film 102 where the vertical single crystal region 104 is to be formed is removed (FIG. 2B).

Next, when Si is epitaxially grown, a polycrystalline Si region 105 grows in the remaining portion of the oxide film, a single crystal Si layer grows in a portion where the oxide film is removed, and a vertical single crystal region 104 is grown.
(Fig. (C)).

Next, the substrate of FIG. 1 is completed by grinding and polishing.

In this substrate, an n-type Si wafer having a plane orientation (100) and a resistivity of 20 Ω-cm was placed on the first single-crystal Si wafer, and arsenic was added in an amount of 5 × 10
Implantation is performed at ¹⁵ cm ⁻² to form an n ⁺ buried layer, and at the time of epitaxy, phosphorus (P) is introduced so that n having a resistivity of 0.05 Ω-cm or less is formed.
⁺⁺ region was formed.

When an npn transistor was formed in the vertical single crystal region of the substrate completed as described above and its characteristics were examined, it was found that _{VCER was} 400 V and collector resistance was 5 Ω, which was equivalent to the case where the substrate having the structure of the conventional example was used.

Further, since an IC incorporating this output element can take a potential from the surface of the substrate, a conventional package can be used.

Furthermore, this substrate depends on the type of single-crystal Si wafer used first, the buried layer, and the type and concentration of impurities during epitaxy.
Substrates suitable for output devices such as transistors, MOSFETs, etc., and structures suitable for devices are possible.

FIG. 3 is a sectional view illustrating a second embodiment of the present invention.

The substrate is composed of an n-type single crystal Si island 103 electrically insulated and separated from the other by an insulator 102 formed along the separation groove 101 and an n ⁺ single crystal layer 104 deposited by the first epitaxial.
a, p ⁺ single crystal layer 10 deposited by second epitaxy
A vertical single crystal region in which n ⁻ −n ⁺ −p ⁺ layers of 4b overlap, and an n ⁺ polycrystalline region 105a, p ⁺ polycrystalline region deposited simultaneously with the single crystal layer by the first and second epitaxials Consists of 105b.

This board uses IGBT (Insulated Gate Bipolar Tronsisto)
It is suitable for forming r) and can form a vertical IGBT on a dielectric isolation substrate. Further, the potential can be obtained from both the front and back of the substrate.

〔The invention's effect〕

According to the present invention, by forming the low resistance layer, the on-resistance of the output element is reduced, the thermal resistance is reduced, and the potential is obtained from the surface of the substrate. You can use normal ones.

[Brief description of the drawings]

1 (a) and 1 (b) are a plan view and a sectional view of a first embodiment of the present invention, FIG. 2 is an explanatory view of a manufacturing method of the first embodiment, and FIG. 3 is a second embodiment. FIG. 3 shows a cross-sectional view of an example. 99 ... oxide film, 100 ... starting base material, 101 ... separation groove, 102
... oxide film, 103 single crystal island, 104 vertical single crystal region, 104a n ⁺ single crystal layer, 104b n ⁺ polycrystalline layer, 10
5a …… p ^{+ type} single crystal layer, 105b …… p ^{+ type} polycrystal layer, 108 ……
Separation groove, 110 … front side, 120 … back side.

Continuation of the front page (72) Inventor Toru Ishikawa 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-63-199454 (JP, A) (58) Fields investigated (Int) .Cl. ⁶ , DB name) H01L 21/76-21/765 H01L 21/336 H01L 29/78

Claims (3)

(57) [Claims] 1. A dielectric isolation substrate, comprising: a single crystal island that is insulated and separated by an insulator and is exposed on a surface of the dielectric isolation substrate; and a vertical single island penetrating from the front surface to the rear surface of the dielectric isolation substrate. A first region exposed on the front surface, and a second region exposed on the front surface and the back surface and having a higher impurity concentration than the first region. And a dielectric separation substrate. 2. The vertical single crystal region according to claim 1, wherein the vertical single crystal region is an n ⁻ layer, an n ⁺ layer,
The dielectric isolation substrate, wherein the second region is the p ⁺ layer, and the structure is such that a potential can be all taken from the surface. 3. A method for manufacturing a dielectric isolation substrate, comprising the following steps: (A) A step of forming a protective film for etching on a single crystal Si wafer. (B) a step of partially removing the protective film to provide a plurality of openings having different widths; (C) forming a plurality of separation grooves having different depths in the plurality of openings by etching; (D) forming a separation insulator on the single crystal surface on the side where the separation groove is formed; (E) a step of removing the insulator on a single crystal surface surrounded by the deep separation groove and a single crystal surface in the deep separation groove among the plurality of separation grooves. (F) a step of, after the step (e), growing Si on the insulator and on the single crystal surface from which the insulator has been removed. (G) A step of completing a dielectric isolation substrate by grinding and polishing.