JPH0437132A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0437132A
JPH0437132A JP14405890A JP14405890A JPH0437132A JP H0437132 A JPH0437132 A JP H0437132A JP 14405890 A JP14405890 A JP 14405890A JP 14405890 A JP14405890 A JP 14405890A JP H0437132 A JPH0437132 A JP H0437132A
Authority
JP
Japan
Prior art keywords
nitride film
oxide film
film
element isolation
nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14405890A
Other languages
Japanese (ja)
Inventor
Teruto Onishi
照人 大西
Yoshiaki Kato
義明 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14405890A priority Critical patent/JPH0437132A/en
Publication of JPH0437132A publication Critical patent/JPH0437132A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To form an element isolation oxide film design specifications by depositing a 1st oxide film and a 2nd nitride film one after another after etching a 1st nitride film in an element isolation region and then, forming a sidewall consisting of the 2nd nitride film at the pattern side face of the 1st nitride film after performing anisotropic etching in the 2nd nitride film and further, taking the like measures for forming the element isolation oxide film. CONSTITUTION:In forming an element isolation region through oxidation of a silicon substrate 1, the manufacture of this device requires respective processes, i.e., a process for depositing a 1st nitride film 2 on the silicon substrate 1; a process for depositing a 1st oxide film 3 and a 2nd nitride film 4 one after another on the 1st nitride film 2 after etching the 1st nitride film 2 in the element isolation region; a process for forming a sidewall 4' consisting of the 2nd nitride film 4 at the pattern side face of the 1st nitride film 2 after performing anisotropic etching in the 2nd nitride film 4; a process for forming a 2nd oxide film 5 after performing oxidation by making the 1st and 2nd nitride films 2 and 4' act as masks. In this way, the length of element isolation is not larger than the size of each mask and further, the dispersion of the sidewall is reduced by the 1st oxide film and the element isolation region is formed as designed a mask.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法、特にシリコン基板の酸
化により素子分離領域を形成する方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming element isolation regions by oxidizing a silicon substrate.

従来の技術 従来の上記素子分離領域の形成方法を第3図(a)〜(
el)の半導体装置の断面図にしたがって順に説明する
BACKGROUND OF THE INVENTION A conventional method of forming the above element isolation region is shown in FIGS.
The explanation will be given in order according to the cross-sectional view of the semiconductor device of el).

まず、第3図(8)に示すシリコン基板21上に酸化膜
22を形成する(第3図(b))。続いて窒化膜23を
形成し、フォトリソグラフィーの技術を用いてレジスト
の素子分離パターンを形成し、ドライエツチング技術を
用いて窒化膜23だけをエツチングする(第3図(C)
)。その後レジストを除去して酸化を行い、素子分離用
の酸化膜24を形成する。
First, an oxide film 22 is formed on the silicon substrate 21 shown in FIG. 3(8) (FIG. 3(b)). Next, a nitride film 23 is formed, a resist element isolation pattern is formed using a photolithography technique, and only the nitride film 23 is etched using a dry etching technique (FIG. 3(C)).
). Thereafter, the resist is removed and oxidized to form an oxide film 24 for element isolation.

窒化膜23は酸化されにくいため、窒化膜23のない部
分が酸化されて第3図(d)に示すような酸化膜24の
構造がつくられ、この酸化膜24で素子分離を行う。最
後に窒化膜23の除去を行う(第3図(e))。このよ
うな素子分離形成法は、LOCO8法とよばれている。
Since the nitride film 23 is difficult to be oxidized, the portions without the nitride film 23 are oxidized to form an oxide film 24 structure as shown in FIG. 3(d), and the oxide film 24 performs device isolation. Finally, the nitride film 23 is removed (FIG. 3(e)). Such an element isolation formation method is called the LOCO8 method.

発明が解決しようとする課題 しかし、LOCO3法で素子分離用の酸化を行うと、酸
化は等方的に起こるために窒化膜23の下も酸化される
。そのときの酸化膜24の入り込みをバーズビークと呼
ぶ。このバーズビークにより、素子が微細化してくると
設計通りの寸法が得られず、素子特性の悪化またはそれ
を避けるためにチップサイズの増加という問題が生じて
くる。
Problems to be Solved by the Invention However, when oxidation for element isolation is performed using the LOCO3 method, the oxidation occurs isotropically, so that the bottom of the nitride film 23 is also oxidized. The penetration of the oxide film 24 at this time is called a bird's beak. Due to this bird's beak, as the device becomes finer, it becomes impossible to obtain the designed dimensions, resulting in the problem of deterioration of device characteristics or an increase in chip size to avoid this.

また、酸化膜24がシリコン基板2工の面より上方にで
るためにシリコン基板210表面に凹凸が生じ、その後
の配線形成でステップカバレッジの悪化の問題を生じる
Furthermore, since the oxide film 24 is exposed above the surface of the silicon substrate 2, unevenness occurs on the surface of the silicon substrate 210, causing a problem of deterioration of step coverage in subsequent wiring formation.

本発明は上記問題を解決するものであり、設計寸法通り
の素子分離酸化膜を形成する方法と素子分離酸化膜の平
坦化を実施することが可能な半導体装置の製造方法を提
供することを目的とするものである。
The present invention solves the above problems, and aims to provide a method for forming an element isolation oxide film according to design dimensions and a method for manufacturing a semiconductor device in which the element isolation oxide film can be planarized. That is.

課題を解決するための手段 上記課題を解決するため本発明の半導体装置の製造方法
は、シリコン基板の酸化により素子分離領域を形成する
工程に於て、シリコン基板上に第1の窒化膜を堆積する
工程と、素子分離領域の前記第1の窒化膜をエツチング
した後、前記第1の窒化膜の上に第1の酸化膜と第2の
窒化膜を順に堆積する工程と、前記第2の窒化膜を異方
性エツチングして前記第1の窒化膜のパターン側面に前
記第2の窒化膜でできたサイドウオールを形成する工程
と、前記第1、第2の窒化膜をマスクにして酸化を行い
、第2の酸化膜を形成する工程と、を有することを特徴
とするものである。
Means for Solving the Problems In order to solve the above problems, the method for manufacturing a semiconductor device of the present invention includes depositing a first nitride film on a silicon substrate in the step of forming an element isolation region by oxidizing the silicon substrate. a step of depositing a first oxide film and a second nitride film in order on the first nitride film after etching the first nitride film in the element isolation region; forming a side wall made of the second nitride film on the side surface of the pattern of the first nitride film by anisotropically etching the nitride film; and oxidizing using the first and second nitride films as masks. and forming a second oxide film.

さらに第2の発明の半導体装置の製造方法は、上記第1
の発明の工程に、さらに上記第1、第2の窒化膜をマス
クにして前記第2の酸化膜をエツチングする工程と、第
3の酸化膜と第3の窒化膜を順に堆積する工程と、前記
第3の窒化膜を異方性エツチングして第2の酸化膜の側
面に第3の窒化膜のサイドウオールを形成する工程と、
前記第1、第2、第3の窒化膜をマスクにして酸化を行
い第4の酸化膜を形成する工程とを加えたことを特徴と
するものである。
Furthermore, the method for manufacturing a semiconductor device according to the second invention includes the method for manufacturing a semiconductor device according to the first invention.
The process of the invention further includes a step of etching the second oxide film using the first and second nitride films as a mask, and a step of sequentially depositing a third oxide film and a third nitride film, forming a third nitride film sidewall on the side surface of the second oxide film by anisotropically etching the third nitride film;
The present invention is characterized by adding a step of performing oxidation using the first, second, and third nitride films as masks to form a fourth oxide film.

作用 上記第1および第2の発明において、第1の窒化膜を形
成し、第2の窒化膜によるサイドウオールを形成するこ
とにより、素子分離用酸化膜を形成したときにバーズビ
ークができてもサイドウオールにより寸法が短くなって
おり、第1の窒化膜がシリコン基板上に直接形成されて
いるために素子分離長がマスクサイズより大きくなるこ
とはなく、さらに、中間の第1の酸化膜が窒化膜のエツ
チングストッパになり膜厚のバラツキ、エツチングの不
均一性によるサイドウオールのバラツキが減少しサイド
ウオール形成が安定し、マスク通りの素子分離領域が形
成される。
Effect In the first and second inventions described above, by forming the first nitride film and forming the sidewall of the second nitride film, even if a bird's beak is formed when the element isolation oxide film is formed, the side wall can be avoided. The dimensions are shortened by the wall, and since the first nitride film is formed directly on the silicon substrate, the device isolation length will not be larger than the mask size. Furthermore, the first oxide film in the middle is nitrided. This acts as an etching stopper for the film, reduces variations in film thickness and sidewall variations due to non-uniformity of etching, stabilizes sidewall formation, and forms element isolation regions as per the mask.

また第2の発明において、第2の酸化膜形成後にこの酸
化膜をエツチングすることにより、素子分離領域のシリ
コン基板は掘り下げられることから、その後の酸化によ
り素子分離領域4の酸化膜を形成してもこの素子分離酸
化膜がシリコン基板面より盛り上がることを防げる。
Furthermore, in the second invention, by etching this oxide film after forming the second oxide film, the silicon substrate in the element isolation region is dug down, so that the oxide film in the element isolation region 4 is formed by subsequent oxidation. This also prevents the element isolation oxide film from rising above the silicon substrate surface.

実施例 以下、本発明の一実施例を図面の簡単な説明する。Example Hereinafter, one embodiment of the present invention will be briefly described with reference to the drawings.

第1図(1)〜(h)は第1の発明の一実施例における
半導体装置の製造方法を順に示す半導体装置の断面図で
ある。
FIGS. 1(1) to 1(h) are cross-sectional views of a semiconductor device sequentially showing a method for manufacturing a semiconductor device in an embodiment of the first invention.

まず、第1図(1)に示すシリコン基板1上に減圧CV
D法により窒化膜2を約150nm形成し、フォトリソ
グラフィ技術を用いてレジストパターンを形成し、ドラ
イエツチング技術を用いて窒化膜2だけをエツチングし
、その後レジストはアッシングにより除去する(第1図
(b))。その上に減圧CVD法により酸化膜3を約5
0nm堆積しく第1図(C) ) 、さらにその上に減
圧CVD法により窒化膜4を約20hm堆積しく第1図
(d) ) 、ドライエツチングの異方性エツチングに
より窒化膜4をエツチングする。このエツチングにより
窒化膜2の開口部に、第1図(e)に示すように窒化膜
4によるサイドウオール4′が形成される。このとき酸
化膜3がエツチングストッパになるために膜厚のばらつ
き、エツチングのばらつきがあっても多めにオーバーエ
ツチングを行うことによりばらつきを抑えることができ
る。酸化膜3をウェットエツチングにより除去後(第1
図(f))、窒化膜2゜4′をマスクとして酸化を行い
、素子分離用の酸化膜5を600nm形成しく第1図(
g))、熱燐酸で窒化膜2.4′を除去すると、第1図
(h)のような酸化膜形状が得られる。
First, a low pressure CVD film was applied onto the silicon substrate 1 shown in FIG. 1(1).
A nitride film 2 of approximately 150 nm is formed using method D, a resist pattern is formed using photolithography, only the nitride film 2 is etched using dry etching, and then the resist is removed by ashing (see Fig. 1). b)). Approximately 50% of the oxide film 3 is formed on top of it by low pressure CVD method.
Further, a nitride film 4 of about 20 hm is deposited thereon by a low pressure CVD method (FIG. 1(d)), and the nitride film 4 is etched by anisotropic dry etching. By this etching, a sidewall 4' of the nitride film 4 is formed in the opening of the nitride film 2, as shown in FIG. 1(e). At this time, since the oxide film 3 serves as an etching stopper, even if there is variation in film thickness or variation in etching, the variation can be suppressed by performing a large amount of overetching. After removing the oxide film 3 by wet etching (first
Figure 1 (f)), oxidation is performed using the nitride film 2°4' as a mask, and an oxide film 5 for element isolation is formed to a thickness of 600 nm.
g)) When the nitride film 2.4' is removed with hot phosphoric acid, an oxide film shape as shown in FIG. 1(h) is obtained.

酸化を行うと、酸化は等方的に起こるために窒化膜のサ
イドウオール4′の下も酸化されるが、窒化膜のサイド
ウオール4′により寸法が減少しているため、サイドウ
オール4′の大きさを最適化することによりマスク寸法
通りの素子分離領域が形成できる。また、窒化膜2はシ
リコン基板1に直接堆積しているため窒化膜のストレス
により酸化が窒化膜の下まで伸びることが防げる。しか
しこの窒化膜2のストレスのためにシリコン基板1に欠
陥が生じやすいが、欠陥の入りやすいサイドウオール4
′の下には酸化膜3が形成されているために応力の緩和
ができて欠陥が生じることはない。またサイドウオール
4′の形状も緩やかに増加しているためにサイドウオー
ル4′の下に形成される酸化膜3にかかるストレスも減
少させることができる。
When oxidation is performed, the oxidation occurs isotropically, so the bottom of the sidewall 4' of the nitride film is also oxidized, but since the dimension is reduced by the sidewall 4' of the nitride film, the sidewall 4' is By optimizing the size, element isolation regions can be formed according to the mask dimensions. Further, since the nitride film 2 is directly deposited on the silicon substrate 1, oxidation can be prevented from extending below the nitride film due to the stress of the nitride film. However, due to the stress of this nitride film 2, defects are likely to occur in the silicon substrate 1, but the sidewall 4, which is prone to defects, is
Since the oxide film 3 is formed under ', the stress can be relaxed and no defects will occur. Furthermore, since the shape of the sidewall 4' increases gradually, the stress applied to the oxide film 3 formed under the sidewall 4' can also be reduced.

次に第2の発明の一実施例を、第2図(り〜(n)に示
す半導体装置の断面図にしたがって順に説明する。
Next, an embodiment of the second invention will be described in order according to the cross-sectional views of the semiconductor device shown in FIGS.

まず、第2図(1)に示すシリコン基板11に減圧CV
D法により窒化膜12を約150nm形成し、フォトリ
ソグラフィ技術を用いてレジストパターンを形成し、ド
ライエツチング技術を用いて窒化膜12だけをエツチン
グし、その後レジストはアッシングにより除去する(第
2図(b))。その上に減圧CVD法により酸化膜13
を約50nm堆積しく第2図(c) ) 、さらにその
上に減圧CVD法により窒化膜14を約200nm堆積
しく第2図(d))、ドライエツチングの異方性エツチ
ングにより窒化膜14をエツチングする。このエツチン
グにより窒化膜12の開口部に第2図(e)に示すよう
に窒化膜14によるサイドウオール14′が形成される
。酸化膜13をウェットエツチングにより除去後(第2
図(1))、窒化膜12.14’をマスクにして酸化を
行い、酸化膜5を約40onの形成しく第2図(g) 
) 、さるに窒化膜12.14’をマスクにして酸化膜
15をドライエツチングする(第2図(h))。次に約
50nmの酸化膜16を堆積し、(第2図(i) ) 
、その上に窒化膜17を約200 nm堆積する(第2
図(j))。次に異方性エツチングにより窒化膜17だ
けをエツチングすると第2図(k)に示すような形状に
なり、窒化膜17によるサイドウオール17′が形成さ
れる。ウェットエツチングにより酸化膜16を除去しく
第2図(I))、素子分離用の酸化を行うと第2図(m
)のような酸化膜18が形成され、窒化膜12.14’
17′ をすべて除去すると第2図(n)に示す最終形
状が得られる。
First, the silicon substrate 11 shown in FIG. 2(1) is coated with a low pressure CV
A nitride film 12 of approximately 150 nm is formed using method D, a resist pattern is formed using photolithography, only the nitride film 12 is etched using dry etching, and then the resist is removed by ashing (see Fig. 2). b)). On top of that, an oxide film 13 is formed by low pressure CVD method.
A nitride film 14 of about 200 nm is deposited thereon to a thickness of about 50 nm (FIG. 2(c)), and then a nitride film 14 of about 200 nm is deposited thereon by a low-pressure CVD method (FIG. 2(d)), and the nitride film 14 is etched by anisotropic dry etching. do. By this etching, a sidewall 14' of the nitride film 14 is formed in the opening of the nitride film 12, as shown in FIG. 2(e). After removing the oxide film 13 by wet etching (second
Figure (1)), oxidation is performed using the nitride films 12 and 14' as masks, and the oxide film 5 is formed to a thickness of about 40 on (Figure 2 (g)).
) Then, using the nitride films 12 and 14' as a mask, the oxide film 15 is dry-etched (FIG. 2(h)). Next, an oxide film 16 of about 50 nm is deposited (Fig. 2(i)).
, on which a nitride film 17 of about 200 nm is deposited (second
Figure (j)). Next, when only the nitride film 17 is etched by anisotropic etching, the shape shown in FIG. 2(k) is obtained, and a sidewall 17' of the nitride film 17 is formed. The oxide film 16 is removed by wet etching (FIG. 2(I)), and the oxide film 16 is removed by oxidation for element isolation (FIG. 2(I)).
), an oxide film 18 is formed, and a nitride film 12,14' is formed.
When all 17' are removed, the final shape shown in FIG. 2(n) is obtained.

このように酸化工程が2度入り複雑になるが、第2図(
n)のように酸化膜18をシリコン基板1より上に盛り
上がる量を減らすことができる。このことはシリコン基
板11の表面の凹凸を減少させることができ、その上に
形成する配線の断線を減少させることができる。シリコ
ン基板11を直接エツチングしても同様の効果は得られ
るがエッチングの均一性などでまた問題がある。
In this way, the oxidation process is complicated twice, but as shown in Figure 2 (
As shown in (n), the amount of the oxide film 18 raised above the silicon substrate 1 can be reduced. This can reduce unevenness on the surface of the silicon substrate 11, and can reduce disconnections in the wiring formed thereon. A similar effect can be obtained by directly etching the silicon substrate 11, but there are also problems with etching uniformity.

発明の詳細 な説明したように、第1および第2の発明によれば、セ
ルファラインでマスクサイズが変更可能で、バーズビー
クを気にすることなくマスク寸法通りに素子分離ができ
、その実用的効果は大きい。さらに、第1と第2の窒化
膜の間に酸化膜を形成することで窒化膜のエツチング均
一性が向上し、さらに従来用いていた窒化膜とシリコン
基板の間の酸化膜を省略することでバーズビークの入り
込みを抑えることが可能になり安定して素子分離を形成
できその実用的効果は大きい。
As described in detail of the invention, according to the first and second inventions, the mask size can be changed in the self-line, element isolation can be performed according to the mask dimensions without worrying about bird's beak, and the practical effects thereof are achieved. is big. Furthermore, by forming an oxide film between the first and second nitride films, the etching uniformity of the nitride film is improved, and furthermore, by omitting the oxide film between the nitride film and the silicon substrate, which was conventionally used. It is possible to suppress the bird's beak from entering, and stable element isolation can be formed, which has a great practical effect.

さらに第2の発明によれば、第2の酸化膜をエツチング
することでシリコン基板を掘り下げることにより次の酸
化での膨らみを減少でき、したがってシリコン基板表面
の凹凸を減少させることができることから配線不良を減
少させることができ、その実用的効果は大きい。
Furthermore, according to the second invention, by etching the second oxide film and digging into the silicon substrate, it is possible to reduce the bulge caused by the next oxidation, and therefore, it is possible to reduce unevenness on the surface of the silicon substrate, thereby reducing wiring defects. can be reduced, and its practical effects are significant.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(h)は第1の発明の一実施例における
半導体装置の製造方法を順に示す半導体装置の断面図、
第2図(1)〜(n)は第2の発明の一実施例における
半導体装置の製造方法を順に示す半導体装置の断面図、
第3図(1)〜(e)は従来の半導体装置の製造方法を
順に示す半導体装置の断面図である。 1.11・・・シリコン基板、2.12・・・(第1の
)窒化膜、3.13・・・(第1の)酸化膜、4,14
・・・(第2の)窒化膜、4’ 、 14’ ・・・サ
イドウオール、5゜15・・・(第2の)酸化膜、16
・・・(第3の)酸化膜、エフ・・・(第3の)窒化膜
、17′・・・サイドウオール、18・・・(第4の)
酸化膜。 代理人   森  本  義  弘 第を 図(−7ブυ Δ′ 5− ($2#)j−睡しイL1」( 第 2図(っブき) 14′ イ162の)![イと露)− 第2図(7ブさ) 18・・・C略4時)#I4と職 第3図
1(a) to (h) are cross-sectional views of a semiconductor device sequentially showing a method for manufacturing a semiconductor device in an embodiment of the first invention,
FIGS. 2(1) to (n) are cross-sectional views of a semiconductor device sequentially showing a method for manufacturing a semiconductor device in an embodiment of the second invention;
FIGS. 3(1) to 3(e) are cross-sectional views of a semiconductor device sequentially showing a conventional method of manufacturing a semiconductor device. 1.11... Silicon substrate, 2.12... (first) nitride film, 3.13... (first) oxide film, 4, 14
...(Second) nitride film, 4', 14'...Side wall, 5°15...(Second) oxide film, 16
...(third) oxide film, F...(third) nitride film, 17'...side wall, 18...(fourth)
Oxide film. Agent Morimoto Yoshihiroki (-7 bu υ Δ' 5- ($2#)j-sleeping L1' (Fig. 2 (buki) 14' I162)! ) - Figure 2 (7bsa) 18...C approx. 4 o'clock) #I4 and position Figure 3

Claims (1)

【特許請求の範囲】 1、シリコン基板の酸化により素子分離領域を形成する
工程において、シリコン基板上に第1の窒化膜を堆積す
る工程と、素子分離領域の前記第1の窒化膜をエッチン
グした後、前記第1の窒化膜の上に第1の酸化膜と第2
の窒化膜を順に堆積する工程と、前記第2の窒化膜を異
方性エッチングして前記第1の窒化膜のパターン側面に
前記第2の窒化膜でできたサイドウォールを形成する工
程と、前記第1、第2の窒化膜をマスクにして酸化を行
い、第2の酸化膜を形成する工程と、を有することを特
徴とする半導体装置の製造方法。 2、シリコン基板の酸化により素子分離領域を形成する
工程において、シリコン基板上に第1の窒化膜を堆積す
る工程と、素子分離領域の前記第1の窒化膜をエッチン
グした後、前記第1の窒化膜の上に第1の酸化膜と第2
の窒化膜を順に堆積する工程と前記第2の窒化膜を異方
性エッチングして前記第1の窒化膜のパターン側面に前
記第2の窒化膜でできたサイドウォールを形成する工程
と、前記第1、第2の窒化膜をマスクにして酸化を行い
、第2の酸化膜を形成する工程と、前記第1、第2の窒
化膜をマスクにして前記第2の酸化膜をエッチングする
工程と、前記第1、第2の窒化膜の上に第3の酸化膜と
第3の窒化膜を順に堆積する工程と、前記第3の窒化膜
を異方性エッチングして前記第2の酸化膜のパターン側
面に前記第3の窒化膜でできたサイドウォールを形成す
る工程と、前記第1、第2、第3の窒化膜をマスクにし
て酸化を行い第4の酸化膜を形成する工程と、を有する
ことを特徴とする半導体装置の製造方法。
[Claims] 1. In the step of forming an element isolation region by oxidizing a silicon substrate, the step of depositing a first nitride film on the silicon substrate and etching the first nitride film in the element isolation region are performed. After that, a first oxide film and a second oxide film are formed on the first nitride film.
a step of sequentially depositing nitride films, and a step of anisotropically etching the second nitride film to form a sidewall made of the second nitride film on a side surface of the pattern of the first nitride film; A method for manufacturing a semiconductor device, comprising the step of performing oxidation using the first and second nitride films as masks to form a second oxide film. 2. In the step of forming an element isolation region by oxidizing the silicon substrate, a step of depositing a first nitride film on the silicon substrate, and after etching the first nitride film in the element isolation region, a step of depositing the first nitride film on the silicon substrate; A first oxide film and a second oxide film are formed on the nitride film.
a step of sequentially depositing a nitride film, and a step of anisotropically etching the second nitride film to form a sidewall made of the second nitride film on a side surface of the pattern of the first nitride film; A step of performing oxidation using the first and second nitride films as masks to form a second oxide film; and a step of etching the second oxide film using the first and second nitride films as masks. a step of sequentially depositing a third oxide film and a third nitride film on the first and second nitride films; and anisotropically etching the third nitride film to form the second oxide film. A step of forming a sidewall made of the third nitride film on the side surface of the film pattern, and a step of performing oxidation using the first, second, and third nitride films as masks to form a fourth oxide film. A method for manufacturing a semiconductor device, comprising:
JP14405890A 1990-06-01 1990-06-01 Manufacture of semiconductor device Pending JPH0437132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14405890A JPH0437132A (en) 1990-06-01 1990-06-01 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14405890A JPH0437132A (en) 1990-06-01 1990-06-01 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0437132A true JPH0437132A (en) 1992-02-07

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP14405890A Pending JPH0437132A (en) 1990-06-01 1990-06-01 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0437132A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002134604A (en) * 2000-10-27 2002-05-10 Oki Electric Ind Co Ltd Method for forming element isolating region in semiconductor device
US6872664B2 (en) * 2003-03-13 2005-03-29 Promos Technologies, Inc. Dual gate nitride process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002134604A (en) * 2000-10-27 2002-05-10 Oki Electric Ind Co Ltd Method for forming element isolating region in semiconductor device
US6872664B2 (en) * 2003-03-13 2005-03-29 Promos Technologies, Inc. Dual gate nitride process

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