JPH0437048A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To exclude the possibility that it becomes difficult to increase the integration degree of a semiconductor integrated circuit, by making each transistor element independent in an island like shape by using trenches, and forming a channel stopper in the trench bottom part. CONSTITUTION:Each transistor element forming region 3 is separated by trenches 2. A P<+> type channel stopper 4 is formed in the bottom part of the trench 2. By this structure, the possibility that an element isolation region is widened by a bird's beak is excluded. Since the height of a transistor forming position is different from the stopper 4, the possibility that the channel width is narrowed is excluded when the stopper 4 is stretched in the lateral direction. As to a gate insulating film 6, the part 6a on the trench 2 bottom surface is made thicker than the other part. Hence said insulating film 6a functions as a mask preventing arsenic As from being added to the stopper 4. Hence the possibility that the impurity concentration of the stopper 4 is remarkably decreased by ion implantation to form a source 8 and a drain 9 does not exist at all.

Description

[Detailed description of the invention] The present invention will be described in the following order.

A. Industrial field of application B1 Overview of the invention C1 Prior art [Figure 4] B1 Problems to be solved by the invention E, Means for solving the problems F1 Effects G, Examples [Figures 1 to 4] [Figure 3] H0 Effects of the Invention (A, Industrial Application Field) The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit in which an element isolation region and a channel stopper are enlarged and the channel width of a transistor is narrowed.

(B. Summary of the Invention) The present invention provides a semiconductor integrated circuit in which each transistor element is made independent in the form of an island by a trench, in order to prevent the channel width of the transistor from becoming narrower due to expansion of the element isolation region and channel stopper. A channel stopper is formed at the bottom of the trench.

(C, Prior Art) [FIG. 4] For element isolation of semiconductor integrated circuits, the LOCO5 method, in which isolation is performed using a selective oxide film, has been used as shown in FIG.

In the figure, a is a p-type semiconductor substrate, b is a p3-type channel stopper, C is a selective oxide film formed by selectively oxidizing the surface of the semiconductor substrate a, d is a gate insulating film, and e is a polycrystalline This is a gate electrode made of silicon.

(D. Problem that the invention attempts to solve) By the way, the fourth problem
In a conventional semiconductor integrated circuit in which elements are isolated by a selective oxide film C as shown in the figure, the effective channel width of the MOS transistor is narrowed due to the extension and expansion of the bird's beak of the selective oxide film and the channel stopper b, and the current capacity is reduced. There was a problem.

Furthermore, there is also the problem that the area of the element isolation region becomes wide due to the extension of the bird's beak of the selective oxide film C, which also hinders high integration.

The present invention has been made to solve these problems, and an object of the present invention is to prevent the channel width of the transistor from becoming narrower due to the expansion of the element isolation region and the channel stopper.

(E. Means for Solving the Problems) In order to solve the above problems, the semiconductor integrated circuit of the present invention is characterized in that each transistor element is made independent in the form of an island by a trench, and a channel stopper is formed at the bottom of the trench. do.

(F. Effect) According to the semiconductor integrated circuit of the present invention, since the trenches are used to isolate the elements, there is no risk that the channel width will become narrower due to the extension of the birthbeak, unlike when the elements are isolated by the selective oxide film. Furthermore, since the channel stopper is located at the bottom of the trench, even if it expands, it will not have the same effect on the channel width of the transistor, which is located at the same height as the top of the trench.

Therefore, there is no risk that the channel width will become narrower and the current capacity will decrease.

Furthermore, since there is no risk that the bird's beak will be extended as in the conventional case, there is no risk that the area occupied by the element isolation region will become larger and that it will be difficult to increase the degree of integration of the semiconductor integrated circuit. , it becomes easier to achieve high integration.

(G. Embodiment) [FIGS. 1 to 3] Hereinafter, the semiconductor integrated circuit of the present invention will be described in detail according to the illustrated embodiment.

1 and 2 show one embodiment of the semiconductor integrated circuit of the present invention, with FIG. 1 being a sectional view and FIG. 2 being an enlarged perspective view showing the main parts of a transistor. In the drawing, 1 is a p-type semiconductor substrate, 2 is a trench formed by anisotropically etching the surface of the semiconductor substrate 1, and each transistor element forming region 3 is separated into islands by the trench 2. . 4 is a p'' type channel stopper formed at the bottom of the trench 2; 5 is a p'' type semiconductor region for taking out the substrate electrode selectively formed on the surface of one channel stopper 4; 6 is a gate insulating film; 6a
is an insulating film formed on the bottom surface of the trench 2 at the same time as the gate insulating film 6. The insulating film 6a is the gate insulating film 6
The film thickness is considerably thicker than that of the previous one, but this point will be explained later.

7 is a gate electrode made of tungsten polycide, 8 is a source of a MOS transistor, 9 is a drain, 1
According to the semiconductor integrated circuit having such a structure, 0 is an interlayer insulating film and 11 is a contact electrode, the trench 2
Since the transistors are isolated from each other by a selective oxide film formed by a selective oxidation method, there is no risk that the element isolation region will become wider due to bird's beaks, unlike in the conventional case where elements are isolated by a selective oxide film formed by a selective oxidation method. There is no risk that the area will become wider (and the degree of integration of semiconductor integrated circuits will become lower).

Even if the channel stopper 4 extends in the lateral direction, the channel stopper 4 and the transistor formation position are different in height, so there is no risk that the channel width will become narrower.

Furthermore, the gate electrode 7 has a vertical portion along the side surface of the square columnar element isolation region 3 separated into islands, so that the effective channel width Weff is widened. That is, as is clear from FIG.
The sum W1+2W2 of the width W1 in the direction orthogonal to the channel and twice the depth W2 of the source 8 and drain 9 is the effective channel width Weff, and the effective channel width We
ff is 2W2 wider than that of a normal semiconductor integrated circuit (
Become. As described above, when the effective channel width Weff becomes wide, the current capacity inevitably becomes high.

FIGS. 3A to 3C are cross-sectional views showing the method for manufacturing the semiconductor integrated circuit shown in FIGS. 1 and 2 in order of steps.

(A) A trench 2 is formed by selectively etching the surface of the semiconductor substrate 1 using the resist film 12 as a mask, and then a channel stopper 4 is formed by ion-implanting, for example, boron B into the bottom of the trench 2. do. FIG. 3(A) shows the state after the channel stopper 4 is formed.

(B) Next, a gate insulating film 6.6a is formed by thermal oxidation, and then a gate electrode 7 made of tungsten polycide is formed. FIG. 3(B) shows the state after the gate electrode 7 is formed.

Note that the gate insulating film 6 is thicker at a portion 6a on the bottom surface of the trench 2 than at other portions. This is because the growth rate of a thermally oxidized film on a region doped with a high concentration of p-type impurities is faster than that on a semiconductor region where no impurities are added or at a low concentration.

(C) Thereafter, a source 8 and a drain 9 are formed by ion-implanting an n-type impurity, for example, arsenic As, as shown in FIG. 2C. In this case, arsenic As is also implanted into the trench 2 forming region, but since a thick insulating film 6a exists on the bottom surface of the trench 2, unless the ion implantation energy is too strong, the insulating film 6a will be implanted into the channel stopper 4. It functions effectively as a mask moss that prevents arsenic As from being added. Therefore, there is no possibility that the impurity concentration of the channel stopper 4 will be significantly reduced by the ion implantation for forming the source 8 and drain 9. It is not necessary at all to form and mask.

After that, for example, a p'' type diffusion layer 5 is formed and annealed by heat treatment in an N2 atmosphere to form a glabellar insulating film 1.
0 is formed, contact holes are formed, and electrodes 11 are formed. Then, the semiconductor integrated circuit shown in FIGS. 1 and 2 is produced.

(H, Effect of the Invention) As described above, in the semiconductor integrated circuit of the present invention, a trench is formed on the surface of a semiconductor substrate to make each transistor element independent in an island shape, and a channel stopper is formed at the bottom of the trench. The semiconductor device is characterized in that an insulating film thicker than the gate insulating film of the transistor is formed on the bottom surface of the trench.

Therefore, according to the semiconductor integrated circuit of the present invention! - Since elements are isolated using a wrench, the channel width becomes narrower due to the extension of the bird's beak, as in the case where elements are isolated using a selective oxide film7. There is no risk of that happening. Furthermore, since the channel stopper is located at the bottom of the trench, even if it expands, it will not have the same effect on the channel width of the transistor located at the same height as the top of the trench.

Therefore, there is no risk that the current capacity will decrease due to the channel width becoming short.

Furthermore, unlike in the conventional case, there is no risk that the bird's beak will be extended, so there is no risk that the area occupied by the element isolation region will be wide (and that it will be difficult to increase the degree of integration of the semiconductor integrated circuit).

[Brief explanation of drawings]

1 to 3 are for explaining two embodiments of the semiconductor integrated circuit of the present invention, in which FIG. 1 is a sectional view, FIG. 2 is a perspective view showing a transistor element, and FIG. 3 (A,). ~(C
) is a cross-sectional view showing the manufacturing method in the order of steps, and FIG. 4 is a cross-sectional view showing a conventional example. Explanation of symbols 1... 2... 4... 6... 7... 9... Semiconductor substrate, trench, 3... Element formation region, channel stopper, gate insulating film, 6a...・Insulating film, gate electrode, 8. ・Source. drain. Figure 3

Claims (1)

[Claims] (1) A trench is formed on the surface of the semiconductor substrate to make each transistor element independent in the form of an island, a channel stopper is formed at the bottom of the trench, and an insulating film thicker than the gate insulating film of the transistor element is formed on the bottom of the trench. A semiconductor integrated circuit characterized by being formed