JPH04369844A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase a gate breakdown strength by a method wherein an impurity is ion-implanted in an ohmic junction region and in the vicinity of the ohmic junction region and an annealing for activating the introduced impurity, such as an RTA, is performed as the profile in the depth direction of the introduced impurity is kept. CONSTITUTION:An intentionally impurity non-doping GaAs epitaxial layer 3 is formed. After the I-type layer 3 in the vicinity of a gate is selectively removed with a sulfuric acid solution in a desired thickness, an inter-element isolation is performed, Si ions are selectively ion-implanted in an ohmic junction formation region and in the vicinity of the ohmic junction formation region, an RTA is performed and the impurity is electrically activated. After that, the layer 3 at a gate formation region is selectively removed with a sulfuric acid solution in a desired thickness. After that, a WSi film is deposited as a gate metal film 5, AuGe-Au metals are alloyed at 400 deg.C to form an electrode metal film 6 and a GaAs MESFET is formed. Thereby, as a gate breakdown strength can be increased, the MESFET can be actuated at a high voltage.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to MESFET (Metal-Semiconductor) devices.
orField Effect Transister
, Schottky gate field effect transistor).

0002

[Prior Art] In conventional GaAs MESFETs, a SiO2 film or a Si3 N4 film is grown directly on the channel and used as a passivation film, but since these films have a different crystal structure from GaAs, the GaAs/passivation film interface This results in a high density of surface defects. This interface repeatedly captures and releases electrons as the gate bias changes. However, since the time constant for electron emission is on the order of several milliseconds, during large-amplitude operation in the high-frequency range such as microwaves, the electron emission cannot be followed, and as a result, the operation continues with electrons captured at the interface around the gate. Become. Therefore, the potential of the interface increases,
This causes channel narrowing and limits both output power and efficiency.

[0003] In order to solve the above-mentioned problem caused by the interface states localized at the interface between the passivation film and GaAs, two main attempts have been made in the past. There are two methods: an active method of reducing interface states and a passive method of avoiding interface states. The former involves surface treatment with a solvent containing sulfur, and the latter includes a multi-stage recess structure and a structure in which a layer (hereinafter referred to as an i-layer) not intentionally doped with carriers is placed on a channel. In particular, in a structure with an i-layer, S. Srira
m et al. IEEE Cornell Con
f. 218 IV-5 (1989) and M. Taki
Kawa et al “Semi-Insulatin
g III-V Materials “Ohmsha
Ltd. There is a report called 603 (1986). The former is GaA with a thickness of 2000 angstroms as the i-layer.
s is used. The latter is made of 1000 angstrom AlGa as the i-layer.
As is regrown and used.

0004

[Problems to be Solved by the Invention] The above-mentioned conventional GaAs MESFET structure with an i-layer has an n-type GaAs epitaxial layer 2 on a semi-insulating GaAs substrate 1, as shown in FIG. A gate metal 5 is connected to the GaAs epitaxial layer 2 in a Schottky junction. n-type G
The other surface of the aAs epitaxial layer 2 is a GaAs epitaxial layer (i-layer) 3 that is not intentionally doped with impurities.
It has an n-type GaAs contact layer 4 and an electrode metal 6 thereon. As shown in FIG. 2, the thickness of the layer under the n-type GaAs contact layer 4 is 500 Å to 1.
When the channel has an epitaxial structure with an i-GaAs layer 3 of 000 angstroms and has a profile where the concentration is constant in the depth direction, it becomes insensitive to changes in the channel surface and the linear region of the input/output characteristics becomes wide. Although characteristics such as higher saturation output are improved, on the other hand, the gate breakdown voltage is approximately 1
There was a problem that the voltage was only 4V, which was too low to operate the FET at a high voltage of 10V or higher. Further, when the thickness of the i-layer 3 increases, the source resistance Rs and the drain resistance Rd increase, which has a negative effect on the characteristics.

[0005]

[Means for Solving the Problems] The present invention provides a step of selectively introducing impurities into an ohmic junction forming region and its vicinity by ion implantation in an epitaxial structure in which an i-GaAs layer is disposed on a channel; An annealing process, such as RTA (Rapid Thermal Annealing), is used to activate the impurities while maintaining their depth profile.
al).

The effects of impurity ion implantation into the ohmic junction forming region and its vicinity and impurity activation annealing will be described below. FIG. 3 shows the relationship between gate breakdown voltage and drain current Idss when gate bias Vg=0V. Group A is the conventional structure with the i-layer 3 shown in FIG. 2, group B is the conventional structure without the i-layer, and group C is the conventional structure without the i-layer.
is the structure according to the invention shown in FIG. 1e or FIG. 4e. As is clear from the figure, group C of the present invention exhibits the highest gate breakdown voltage for the same Idss. From this, it becomes possible to increase the gate breakdown voltage while maintaining the advantages of the conventional structure in which the i-layer 3 is arranged, and it becomes possible to operate at a high voltage. Furthermore, increases in source resistance Rs and drain resistance Rd can also be suppressed.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of one embodiment of the present invention. In this example, we consider the case of the epi structure shown in FIG. 1a. Figures 1a, b, c, and d are main cross-sectional views of the manufacturing method of this embodiment. As shown in Figure 1a, semi-insulating GaA
An n-type GaAs epitaxial layer 2 with an impurity concentration of 3.5×10 17 cm −3 is formed on an s-substrate 1 using a crystal growth apparatus such as MBE using a technique of stacking atomic layers of 1200 angstroms layer by layer. Next, using the same equipment, a GaAs epitaxial layer (
Form i-layer) 3 with a thickness of 4000 angstroms. Figure 1b
As shown in , after selectively removing the i-layer 3 near the gate to a desired thickness of 3000 angstroms using a sulfuric acid solution,
After separating the elements, 28Si+ was selectively applied to the ohmic junction formation region and its vicinity at 300 keV as shown in Figure 1c.
8×1013cm-2,120keV, 2×1013c
Ion implantation and RTA were performed under the conditions of m-2, 50 keV, and 2 x 1013 cm-2 to electrically activate the impurities. After that, as shown in Fig. 1d, the gate formation area i is coated with a sulfuric acid solution.
Layer 3 is selectively removed to the desired thickness (here 1000 angstroms). After that, WS is used as gate metal 5.
The electrode metal 6 was formed by depositing AuGe-Au metal at 400°C, and forming the Ga of the present invention as shown in FIG.
As MESFET was formed.

GaAs MESFTE according to this embodiment
The gate withstand voltage has been dramatically improved to 26.3V, and Vds=
High voltage operation of 15V is now possible. RF characteristics are 1 chip, Idss=1.9A, 12.575GHz, Vds
= 15V, a high output of 36.3 dBm was obtained at the 2 dB compression point.

Next, another embodiment of the present invention will be explained. This example deals with the case of an epitaxial structure in which a 1000 angstrom contact layer is grown on the i-layer as shown in FIG. 4a. As shown in FIG. 4b, epitaxial substrates 1, 2, 3, including an i-layer thickness of 1000 angstroms,
After selectively removing the contact layer 4 in the gate formation region and its vicinity with a sulfuric acid-based solution using a sulfuric acid-based solution, device isolation was performed, and as shown in FIG. 8×1013cm-2
,120keV, 2×1013cm-2,50keV,
Ion implantation and RTA were performed under conditions of 2×10 13 cm −2 to electrically activate impurities. Thereafter, as shown in FIG. 4d, 1000 angstroms of the i-layer in the gate forming area was selectively removed using a sulfuric acid-based solution, and a gate metal 5 was deposited in the same manner as in the first embodiment, and an electrode metal 6 was formed, as shown in FIG. 4e. A GaAs MESFET of the present invention shown in FIG. The gate breakdown voltage of the GaAs MESFET according to the present invention is 26
．． At 8V, RF characteristics are 1 chip, Idss=2.8A,
At 12.575 GHz and Vds=15V, 37.6 dBm was obtained at the 2 dB compression point.

[0011]

Effects of the Invention As explained above, the present invention provides an ohmic junction formation region and the vicinity thereof of an epitaxial substrate containing an epitaxial layer of a compound semiconductor that is not intentionally doped with impurities or doped with a very small amount of impurities. The gate breakdown voltage can be improved from about 14V to about 27V by applying a process of ion-implanting impurities and applying an annealing process such as RTA to activate the introduced impurities while maintaining their depth profile. , 12.57
At a high potential of 5 GHz and Vds = 15 V, we were able to obtain high-level characteristics of approximately 37 dBm of output power at the point of 2 dB compression per chip.

[Brief explanation of drawings]

FIG. 1: Figures a to d are cross-sectional views showing the manufacturing method according to an embodiment of the present invention in order of steps, and Figure e is a cross-sectional view of a FET according to an embodiment of the present invention.
cross-sectional view of

[Figure 2] Cross-sectional view of a conventional FET

[Figure 3] Graph showing the relationship between gate breakdown voltage and drain current Idss when gate bias Vg = 0V

[Figure 4]
Figures a to d are cross-sectional views showing the manufacturing method of other embodiments of the present invention in order of steps, and figure e is a cross-sectional view of an FET according to a second embodiment of the present invention.

[Explanation of symbols]

1 Semi-insulating GaAs substrate 2 N-type GaAs epitaxial layer 3 GaAs epitaxial layer not intentionally doped with impurities 4 N-type GaAs contact layer (region) 5
Gate metal 6 Electrode metal

Claims (3)

[Claims] 1. (a) forming an epitaxial layer including a channel layer on a semi-insulating compound semiconductor substrate using a crystal growth technique controlled at the atomic level, and (b) forming an epitaxial layer including a channel layer using the crystal growth technique; (c) successively after the epitaxial growth of the layer, growing an epitaxial layer of a compound semiconductor which is intentionally undoped or very lightly doped with impurities over the entire surface; and (c) after the epitaxial layer growth, an ohmic junction is formed. selectively introducing impurities into the formation region and its vicinity by ion implantation; (d) activating the ion-implanted impurities while maintaining the depth profile of the introduced impurities; (e) Selectively isotropic or anisotropic etching is performed on the portion of the epitaxial substrate where the gate electrode is to be formed, and the entire epitaxial layer of the compound semiconductor which is not intentionally doped with impurities or doped with a very small amount of impurities is etched. A method of manufacturing a semiconductor device, comprising the step of selectively depositing metal on a portion where the gate electrode is to be formed after removing a portion of the gate electrode. 2. The method according to claim 1, further comprising the step of using the crystal growth technique to continuously grow a contact layer on the entire surface after the epitaxial layer growth, with a concentration equal to or as high as that of the channel layer. Semiconductor manufacturing method. 3. Before depositing the gate electrode, selectively isotropic or anisotropic etching is performed on the epitaxial substrate including the contact layer in a certain region between the source and drain, or the selective etching is performed in different regions. 2. A method for manufacturing a semiconductor according to claim 1, which includes the step of repeating the steps.