JPH04368999A - Signal processor - Google Patents

Abstract

PURPOSE:To execute the signal processing of a reverberation whose delay time is long and a delay, etc., by a small storage area. CONSTITUTION:A storage part of the signal processor is constituted by containing a main memory 91 for storing data in a difference format, a sub- memory 92 for storing input data before a prescribed sampling period, a modulating means 106 for storing a value obtained by subtracting data stored in advance in the sub-memory 92 from the data inputted to the storage part, in the main memory 91 as difference data, and also, storing the storage data in the sub- storage means 92, and a demodulating means 107 for adding the data stored in the main memory 91 and the sub-memory 92 and outputting it as storage data, and also, storing the added data in the sub-memory 92.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to a signal processing device, and more specifically to a DSP (Digital Signal P
The present invention relates to a signal processing device called a "roccesor" and used, for example, in an effect circuit of an electronic musical instrument.

0002

2. Description of the Related Art In general, there are many effect devices that process sound and produce certain effects by applying input signal delay. Against this background, signal processing devices that digitally process musical sound signals generated from electronic musical instruments, etc. in order to add effects such as reverberation and delay to musical sound signals have been known. A typical method is a method using a DSP used in the audio field.

FIG. 12 is a schematic block diagram of an electronic musical instrument using such a DSP. In the figure, the electronic musical instrument is divided into blocks: CPU1, ROM2, RAM3,
It is composed of a keyboard 4, a sound source 5, a DSP 6, a D/A converter 7, and a sound generation circuit 8, and these parts are connected by a data bus 9. The CPU 1 controls the entire electronic musical instrument based on the program stored in the ROM 2 and uses the RAM 3 as a work memory. Pitch data of a song is supplied to the CPU 1 from the keyboard 4 as calculation information. Then, the CPU 1 performs necessary processing on this pitch data and sends it to the sound source 5, and the sound source 5 generates a digital musical tone signal based on the supplied pitch data and outputs it to the DSP 6 at a constant sampling period.

[0004] Here, if a musical tone signal is directly sent from the sound source 5 to the D/A converter 7 and converted into an analog signal, and then supplied to the sound generation circuit 8 consisting of a speaker amplifier, etc., a musical tone will be generated. When the digital musical tone signal from the sound source 5 is sent to the DSP 6 as shown in FIG. 2, the DSP 6 can add effects such as reverberation to the digital musical tone signal.

Although the detailed configuration of the DSP 6 is not shown in the drawings, the DSP 6 includes a memory section for storing input musical tone data, processed data, or various coefficient data, and a memory section for storing input data and memory section. It is roughly divided into an arithmetic unit that adds, subtracts, and multiplies data, and a control unit that stores a program to control the overall operation and controls each part according to this program. The input musical tone data is calculated and output according to a program until the next musical tone data is input (for example, within a certain sampling period).

[0006] The above-mentioned calculation not only multiplies the data input at the previous sample timing by a predetermined coefficient, but also multiplies the data input and processed at the previous sample timing (that is, multiple (for example, reverb or delay), it is necessary to store previously processed musical tone data in the DSP 6. For this reason, the memory section of the DSP 6 includes a memory area called a data processing memory (hereinafter referred to as delay memory). Note that this delay memory may be externally attached. The processed musical tone data is stored in this delay memory.

[0007]

[Problems to be Solved by the Invention] By the way, when trying to obtain a reverberation sound with a long reverberation time, for example, the delay memory in the conventional DSP described above has a large number of input signals at a plurality of previous sample timings. The storage area must be extremely large because it is necessary to store this data, but there is a problem in that the memory capacity is limited and it is difficult to add sound effects that require long delay times. Ta.

[0008] That is, to obtain reverberation sound, a storage area is required that is given by the formula: [delay time length] x [sampling rate] x [number of bits]. For example, if the sampling rate is 40KHz and the number of bits is 24,
If the delay time (time length) is 1 second, [1 second] x [40
A storage area of 960,000 bits (KHz]×[24]=960,000 bits is required. However, it is difficult to have such a large storage area, and conventional DSPs cannot add reverb, delay, etc. that require too long a delay time.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a signal processing device that can perform signal processing that provides acoustic effects such as reverb and delay with a long delay time using a small storage area.

0010

[Means for Solving the Problems] A signal processing device according to the present invention includes a program storage means for storing a program for controlling signal processing, data input from the outside at a constant sampling period, and processing data subjected to signal processing. a storage means for storing the data as stored data; and arithmetic processing of the stored data stored in the storage means and input data inputted and stored from the outside according to a signal processing procedure based on a program stored in the program storage means. In the signal processing device, the storage means includes a main storage means for storing data in a differential format, a sub-storage means for storing input data before a predetermined sampling period, and an input data input to the storage means. modulating means for storing a value obtained by subtracting data stored in advance in the sub-storage means from the data stored in the sub-storage means as difference data in the main storage means; and a modulation means for storing the stored data in the sub-storage means; The apparatus is characterized in that it is configured to include demodulation means for adding the data stored in the sub-storage means and outputting the resultant data as the stored data, and for storing the added data in the sub-storage means.

[0011]

[Operation] In the present invention, when data is read into the storage means, the data stored in the sub storage means is subtracted from the input data and stored in the main storage means in a differential format, and the input data at this time is The data is stored in the sub-storage means and becomes data from a predetermined sampling period (for example, one sampling period) before the next reading. On the other hand, when writing data to the storage means, the data from the sub-storage means is added to the data from the main storage means to return to the original value, and the addition result is written to the sub-storage means and used as a predetermined value the next time it is read. The data is from before the sampling period.

[0012] Therefore, since data is stored as a differential value, the storage area required as a delay memory can be reduced. Furthermore, with a certain storage area, signal processing that produces acoustic effects such as reverb and delay that have a longer delay time than before can be performed.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an internal configuration diagram of an embodiment of a signal processing device according to the present invention. The signal processing device of this embodiment is D
It is called SP, and as shown in Figure 1, it is broadly divided into RA that stores input data and processed data.
M section 11 and a coefficient RO that stores coefficients used in calculations.
M12, and ALU 13 that performs arithmetic processing on input data and data stored in the RAM unit 11, etc. according to processing procedures.
and a microcode ROM 14 that stores a program for controlling signal processing. Here, the RAM section 11 corresponds to a storage means, the ALU 13 corresponds to a calculation means, and the microcode ROM 14 corresponds to a program storage means.

First, the microcode ROM 14 will be explained in order. Microcode ROM14 contains DS
A microprogram for controlling the operation of P is stored, and this microprogram is sequentially read out by the outputs CT1 to CT7 of the counter 22, which is an address counter. Note that the first output CT0 of the counter 22 is used to control write/read (W/R) of the memory in the RAM section 11, as will be described later. On the other hand, the upper bits CT8 to CT23 are used for addressing when reading data into the RAM section 11. In this case, the upper bits CT8 to CT23 are 16 bits, so it is possible to specify [1048576] addresses. Note that the numbers attached to each data line in FIG. 1 represent the number of bits.

The counter 22 is a clock generator 23
It operates in synchronization with clock signals CK1 and CK2 from
These clock signals CK1 and CK2 are also output to the operation decoder 24. The operation decoder 24 decodes the instructions read from the microcode ROM 14 and converts various control signals into clock signals CK1 and CK.
Output at a timing synchronized with 2. On the other hand, the microprogram read from the microcode ROM 14 is input to the coefficient ROM 12 via the MC register 25. The coefficient ROM 12 stores coefficients used in calculations designated by the lower 0 to 4 bits of the microprogram read from the microcode ROM 14. Coefficient R.O.
The coefficients for the calculation stored in M12 are read out via the CONST register 26 and supplied to the multiplier (MPY) 27.

The multiplier 27 multiplies the data from the coefficient ROM 12 by the data input from the data bus 28 via the MPY register 29 and outputs the result to terminal A of the ALU 13. The ALU 13 has terminals A and B, and adds and subtracts data input from these two terminals A and B. In detail, the output of the multiplier 27 and its own calculation output (terminal B
), or the offset data from the offset address ROM 30 read by the 0 to 4 bit data from the microcode ROM 14 and the upper bit addressing CT8 to CT23 (PCU) from the counter 22. Add and subtract.

[0017] The above calculation switching in the ALU 13 is as follows:
The operation is performed based on the output signal GOFST of the operation decoder 24, and this output signal GOFST is supplied to the three-state gates 31 and 32 as well as to the three-state gates 34 and 35 via the inverter 33. These three-state gates 31 to 34 operate in a so-called high active state, and when an "H" pulse is supplied, the gates open and allow the input signal to pass through, and an "L" pulse is supplied. When this happens, the gate is closed to prevent (or block) the signal from passing through. Such a function also applies to the three-state gate described later.

Offset data from the offset address ROM 30 is supplied to terminal A of the ALU 13 via a three-state gate 31, and the output from the multiplier 27 is supplied via a three-state gate 34. Furthermore, the upper bit address designations CT8 to CT23 (PCU) from the counter 22 are supplied to the terminal B of the ALU 13 via the three-state gate 32, and its own output data is sent to the ACC register via the three-state gate 35. 36. on the other hand,
Switching between addition and subtraction in the ALU 13 is performed based on the output signal SUB of the operation decoder 24. The calculation result of the ALU 13 is output to the data bus 28 via the ACC register 36.

Further, the calculation result of the ALU 13 is output to the RAM section 11 via the MA register 37, and
is 0 to 4 bits (i.e., 5 bits long) input from the microcode ROM 14 via the SA register 38
The command data and the operation data inputted from the ALU 13 through the MA register 37 are used as addresses to read data coming through the data bus 28 through the MW register 39, or read data through the MR register 40. Output to data bus 28. data bus 28
Data is taken in from the outside via the IN register 41, or data is output from the data bus 28 to the outside via the OUT register 42.

In this case, the signal line for transmitting and receiving data to and from the data bus 28 includes a three-state gate 4.
3, 44, and 45 are intervening. That is, the signal from the ACC register 36 is output to the data bus 28 via the three-state gate 43, and the three-state gate 43 receives the output signal GA of the operation decoder 24.
Passage of the same signal is permitted/blocked based on the CC. Similarly, the signal from the MR register 40 is output to the data bus 28 via the three-state gate 45, and the three-state gate 45 allows or blocks passage of the signal based on the output signal GMEM of the operation decoder 24. . Furthermore, the signal from the IN register 41 is input to the data bus 28 via a three-state gate 44, and the three-state gate 44 allows or blocks passage of the signal based on the output signal GIN of the operation decoder 24.

Note that each of the registers 25, 26, 29,
36, 37, 38, 39, 40, 41, and 42 each latch data at the falling edge of the input clock signal. Further, the ACC register 36 is reset based on the output signal ARST of the operation decoder 24.

FIGS. 2 and 3 are internal configuration diagrams of the operation decoder 24. Operation decoder 24
The instruction O read from the microcode ROM 14 is
P0 to OP7 and outputs CT1 to CT7 of counter 22
is entered. The logic configuration for decoding instructions OP0-OP7 is shown in FIG. 2, and is comprised of AND gates 51-73 and latches 74-83. and gate 5
1 to 64 input two or three of the commands OP0 to OP7 at the same time as necessary. Note that each instruction O for the AND gates 51 to 64
Regarding the inputs of P0 to OP7, inverters are provided on the input side of the gate so as to invert the signal levels as necessary (however, the numbers are omitted). Below, the signals output by decoding the instructions OP0 to OP7 will be explained in detail.

First, AND gates 51 to 53 are used for instruction OP.
2, OP3, and OP7 to generate signals GACC, GMEM, and GIN, respectively. Here, the signal GACC is outputted to the three-state gate 43 as a logical result of the AND gate 51, and controls passage/blocking of the signal between the ACC register 36 and the data bus 28. And each instruction OP2, OP3
, OP7 all go to "L" level, the logical result of AND gate 51 becomes "H" and is supplied to three-state gate 43. That is, when this signal GACC is supplied to the three-state gate 43 in the "H" state,
Three-state gate 43 opens and ACC register 36
The data latched in is output to the data bus 28. This operation is indicated by ACC in the data bus section in the timing chart of FIG. 8, which will be described later, and means that the data from the ACC register 36 is on the data bus 28.

The following explanation will be made in the same manner as above. Next, the signal GMEM is outputted to the three-state gate 45 as the logical result of the AND gate 52, and the signal GMEM is outputted to the three-state gate 45 as the logical result of the AND gate 52.
It controls passage/cutoff of signals between the data bus 28 and the data bus 28. That is, when this signal GMEM is supplied to the three-state gate 45 in the "H" state,
Three-state gate 45 opens and the data latched in MR register 40 is output to data bus 28. This operation is indicated by MR in the data bus section in the timing chart of FIG. 8, which will be described later, and means that data is read from the RAM section 11 and is placed on the data bus 28.

Further, the signal GIN is outputted to the three-state gate 44 as a logical result of the AND gate 53, and
It controls passage/cutoff of signals between the N register 41 and the data bus 28. That is, when this signal GIN is supplied to the three-state gate 44 in the "H" state, the three-state gate 44 opens and data is allowed to pass from the IN register 41 to the data bus 28. This operation is indicated by IN in the data bus section in the timing chart of FIG. 8, which will be described later, and means that external input data latched in the IN register 41 is transferred to the data bus 28.

AND gates 54 to 56 are used for instructions OP0, O
Necessary logic is selected from P1 and OP7, and its output is supplied to latches 74-76, respectively. Latch 74~
76 is an AND gate 65 which latches the signal input at the falling timing of the clock signal CK1.
~Send to 67. AND gates 65-67 generate signals ΦMW, ΦOUT, and ΦMPY based on signals supplied from latches 74-76, respectively, in synchronization with clock signal CK2.

Here, the signal ΦMW is synchronized with the clock signal CK2 as a logical result of the AND gate 65, and is output as a similar single pulse to the MW register 39,
The data latch timing of this MW register 39 is controlled. This is the timing at which data from the data bus 28 is latched into the MW register 39. Signal ΦOUT
is the logical result of the AND gate 66, which is the clock signal CK.
2 and is output as a similar single pulse to the OUT register 42 to control the timing at which data from the data bus 28 is latched into the OUT register 42. The signal ΦMPY is synchronized with the clock signal CK2 as a logical result of the AND gate 67, and is output as a similar single pulse to the MPY register 29 and connected to the data bus 28.
Controls the timing of latching data from MPY into the MPY register 29.

AND gates 57 to 64 are used for instructions OP5 and O
The necessary logic is taken from P6 and OP7, and the output of AND gate 57 is sent to signal SUB, and the output of AND gate 5 is
The output of 9 is connected to the signal GOFST, and further to the AND gate 58
The output of the signal is passed through the AND gate 68 and becomes the signal ARST. Here, the signal SUB is supplied to the ALU13, and the ALU
The addition/subtraction switching in step 13 is as described above. As described above, the signal GOFST is supplied to the inverter 33 and the three-state gates 31 and 32, and switches the operation data in the ALU 13. Signal ARST is synchronized to clock signal CK1 as the logical result of AND gate 68 and is provided as a similar single pulse to ACC register 36 to control the timing of resetting ACC register 36.

The outputs of AND gates 60-64 are supplied to latches 77-81, respectively.
latches signals input at the timing of falling of one or both of clock signals CK1 and CK2, and sends the signals to the subsequent elements. and gate 69~7
1 is the signal ΦAC in synchronization with the clock signal CK2.
Generate C, ΦCNST, and ΦMA.

Here, the signal ΦACC is connected to the AND gate 69
is synchronized with the clock signal CK2 and is supplied as a similar single pulse to the ACC register 36 to control the data latch timing of the ACC register 36. Signal ΦCNST is synchronized with clock signal CK2 as the logical result of AND gate 70 and is provided as a similar single pulse to CONST register 26,
Controls the data latch timing of the ONST register 26. Signal ΦMA is synchronized with clock signal CK2 as the logical result of AND gate 71 and is supplied as a similar single pulse to MA register 37 and SA register 38 to control the data latch timing of these registers 37,38.

The outputs of the latches 80 and 81 are further supplied to the subsequent latches 82 and 83, respectively.
2 and 83 latch the signals input at the falling timing of the clock signal CK1 and send them to AND gates 72 and 73, respectively. AND gates 72 and 73 generate signals ΦMR and MW based on signals supplied from latches 82 and 83, respectively, in synchronization with clock signal CK2. Note that the latch 80 generates a signal MEMW.

Here, the signal ΦMR is synchronized with the clock signal CK2 as a logical result of the AND gate 72, and is supplied as a similar single pulse to the MR register 40,
Controls the data latch timing of the MR register 40. The signal MW is supplied to the RAM section 11 in synchronization with the clock signal CK2 as a logical result of the AND gate 73, and is
The level of a terminal WT in a main memory 91 and a sub-memory 92 (described later) in the M section 11 is controlled (see FIG. 5). Specifically, in the case of the main memory 91, the signal MMW is supplied to the terminal WT, and in the case of the sub memory 92, the signal SMW is supplied to the terminal WT (the operation will be described later). The signal MEMW is sent to the RAM section 1 as the output of the latch 80.
1, and controls the timing of storage control in a main memory 91 and a sub-memory 92, which will be described later, in the RAM section 11 (details will be described in the description of FIG. 5).

On the other hand, the outputs CT1 to CT7 of the counter 22
The logical configuration for decoding is shown in FIG. 3, and the AND gate 8
4, 85 and a latch 86. The AND gate 84 takes all the AND logics of the outputs CT1 to CT7 of the counter 22, and the logic result is input to the latch 86. The latch 86 latches the signal input at the falling timing of the clock signal CK1 and sends it to the AND gate 85, and the AND gate 85 outputs the signal ΦIN based on the signal supplied from the latch 86 in synchronization with the clock signal CK. generate. The signal ΦIN is output to the IN register 41 and controls the data latch timing in the IN register 41.

The meanings of the instructions OP0 to OP7 based on their logical levels are represented by the instruction configuration diagrams shown in FIGS. 4(a) and 4(b). This can be explained as follows. The following commands are explanations of those shown in FIG. 4(a), among which S and D are processing targets, and when they take the logic level of FIG. 4(b), the targets themselves are indicated.

ADD: This is an addition instruction of the ALU 13, and is characterized in that three bits of instructions OP5 to OP7 are [000]. The target to be added is determined by the lower 4 bits of the instructions OP0 to OP3. This instruction OP5~O
When P7 becomes [000], the output SUB of the operation decoder 24 becomes [0], and the ALU 13 enters the addition state. Further, a signal ΦACC is outputted from the operation decoder 24 in synchronization with the clock signal CK2, and the addition result of the ALU 13 is latched in the ACC register 36.

At this time, for example, if the lower OP3 to OP0 are [1011] (specifying the value of the IN register 41 and the value of the multiplier 27), the signal GIN becomes [1] and the value of the IN register 41 is is input to the data bus 28. Also, since the signal ΦMPY becomes [1], this I
The value of N register 41 is latched into MPY register 29. This value is then multiplied by multiplier 27. Furthermore, since the signal GOFST is [0] at this time, the ALU
13 adds the value of the ACC register 36 and the value of the multiplier 27 and latches it into the ACC register 36 at the timing when the signal ΦACC falls. Initially, if the value of the ACC register 36 is [0], the value input to the terminal A of the ALU 13 will be input to the ACC register 36. Also, when lower OP3 to OP0 are [0000], AC
The value obtained by adding the value of the C register 36 and the data input to the terminal A at that time is latched in the ACC register 36 and output to the data bus 28. This is the signal ΦACC
= [1].

SUB: Only the ALU 13 enters the subtraction state (SUB=[1]), and the rest is the same as ADD.

ACC RESET: Instructions OP5 to OP
The 3 bits of 7 become [010], and the ACC register 36
is reset at the timing of clock signal CK1 (ARST=1). Also, lower bits OP3~
At this time, data is moved between registers in the OP0 state. Specifically, the state of lower bits OP3 to OP0 is [0
000], the value of the ACC register 36 is moved to the data bus 28. When [1011], signal GIN=[
1], and when the value of the IN register 41 becomes ΦMPY=1, it is latched in the MPY register 29 (IN→
MPY). When [0111], signal GMEM=[1]
When the value of the MR register 40 becomes ΦMPY=1 via the data bus 28, it is latched into the MPY register 29 (MR→MPY). [0001], the signal GACC becomes [1], and when the value of the ACC register 36 becomes ΦMW=1 via the data bus 28, the MW
It is latched into the register 39 (ACC→MW). When [0010], signal GACC=[1], and A
The value of the CC register 36 is transferred to ΦOU via the data bus 28.
When T=1, it is latched in the OUT register 42 (ACC→OUT).

Coefficient No. SET: Latch data from the coefficient ROM 12 into the CONST register 26. In other words, the coefficient R is determined by the 5 bits of instructions OP4 to OP0.
Specify the address of OM12 and execute instructions OP7, OP6=[
10], the signal ΦCNST is generated at the timing of the clock signal CK2, and the coefficient data is latched.

RAM READ: This is for outputting the stored contents of the RAM section 11 to the MR register 40. The data of the lower bits OP4 to OP0 is designated to the SA register 38, and the value of the state (offset value + PCU) where the signal GOFST=[1] is supplied to the MA register 37. Then, these values become SA when the signal ΦMW=[1].
, MA registers 38 and 37. After that, 1
The signal ΦMR is output after a sample delay, and the MR register 4
Data from the RAM section 11 is latched to 0.

RAM WRITE: M in RAM section 11
This is to write the value latched by the W register 39. The lower bits OP4 to OP0 become address values, which are the same as when reading (READ).

NOP: This is a so-called no operation, which does nothing. Therefore, lower bits OP3~
Data is only transferred between registers specified by OP0 (4 bits).

Next, FIG. 5 is a diagram showing a detailed circuit configuration of the RAM section 11. In this figure, the RAM section 11 includes a main memory 91, a sub memory 92, and an A.
LU93, ROM94, ROM95 and register 96
It consists of: Below, the details of the circuit configuration will be explained while adding other circuit elements in addition to these. First, the main memory 91 stores data in a differential format and corresponds to main storage means. Further, the sub-memory 92 stores input data before a predetermined sampling period (in this embodiment, one sampling period before), and corresponds to a sub-storage means. A common function of these memories 91 and 92 is that data can be written when the level of each terminal OE is [1], and data is input to the terminal D at the timing when the level of the terminal WT becomes [1]. is stored in the area specified by the address input to terminal A. Each terminal WT
As described above, the signal MW from the operation decoder 24 is supplied to the main memory 91 as the signal MMW, and the sub memory 92 as the signal SMW. Note that the terminal A of the main memory 91 is connected to the MA register 37, and the terminal A of the sub memory 92 is connected to the SA register 38.

The ROM 94 has an exponent conversion table and compresses and converts input 16-bit data into 8-bit data. The ROM 95 also has an external number conversion table, and converts input 8-bit data back to 16-bit data. Terminal D of main memory 91 is connected to output port DO via three-state gate 97 and ROM 94 in sequence, and to one input terminal of ALU 93 via ROM 95 and three-state gate 98 in sequence. Further, one input terminal of the ALU 93 is connected to the input port DI via a three-state gate 99. The three-state gate 98 opens when the signal MEHW from the operation decoder 24 is "H", and the three-state gate 99 similarly opens when the inverted value of the signal MEHW supplied via the inverter 100 is active. On the other hand, the three-state gate 97 operates based on the output signal of the AND gate 101.
01 is supplied with signals CT0 and MEMW. Note that the output signal of the AND gate 101 is also supplied to the terminal OE of the main memory 91.

The other input terminal of ALU 93 is connected to terminal D of submemory 92, which is further connected to output port DO via three-state gate 102. Note that the output port DO is also connected to the output side of the register 96. Further, the other input terminal of ALU 93 is also connected to input port DI via three-state gate 103. Three-state gate 102 operates based on the output signal of AND gate 104, and three-state gate 103 operates based on the output signal of AND gate 105. AND gates 104 and 105 have a signal C
T0 and MEMW are supplied. However, and gate 1
The signal MEMW is inverted and supplied to 05.

The ALU 93 is an adder/subtracter, and performs addition when the control signal MEMW is [1], and MEMW=
When [0], subtraction is performed. When adding, ROM95,
Data from the main memory 91 via the three-state gate 98 is input to terminal A, and data output one sampling period ago is input from the sub-memory 92 to terminal B, and each of these data is input to the ALU 93. will be added. Thereafter, the added data is latched into register 96 and output from output port DO. The ALU 93 performs addition when reading data. Also,
At this time, the value latched in the register 96 by the output signal of the AND gate 104 is transferred to the three-state gate 102.
The data is input to the submemory 92 at the timing when the data is opened, and is stored as data from one sampling period before.

On the other hand, the subtraction corresponds to data writing, and data from the input port DI is input to the terminal A via the three-state gate 99, and from this value is input to the terminal B.
The data inputted from the submemory 92 and outputted one sampling period ago is subtracted. After that, the subtraction data is latched into the register 96 and compressed by the ROM 94, and then the second half of the sampling period (CT0=[1])
The signal is input to the main memory 91 at the timing when the three-state gate 97 is opened by the output signal of the AND gate 101. Then, it is written in synchronization with the subsequent clock signal CK2. At this time, the three-state gate 103 is also opened, and the data from the input port DI is also transferred to the signal MW.
The data is written into the submemory 92 in synchronization with . Here, the ROM 94, the AND gate 101, the three-state gates 97, 98, 99, the inverter 100 and the ALU 9
3 corresponds to the modulation means 106 as a whole. Also, the ROM 95, AND gates 104, 105, three-state gates 98, 99, 102, 103, inverter 1
00 and ALU 93 correspond to demodulation means 107 as a whole.

Next, FIG. 6 shows a circuit diagram of the operation when delay processing of a signal is performed using the DSP described above. The delay processing circuit shown in this figure is a delay circuit 11.
0, multipliers 111 to 113 and an adder 114. α, β, and γ are coefficients stored in the coefficient ROM 12, and are respectively multiplied by the data inputted in the multipliers 111 to 113. This multiplication process corresponds to the process of the multiplier 27 when shown in correspondence with FIG. Furthermore, the addition process of the adder 114 is performed by the ALU.
This corresponds to No. 13 processing. The delay circuit 110 is like a shift register that sequentially shifts input data to the right one bit at a time, and corresponds to the RAM section 11. Data OFST0 on the input side of the delay circuit 110,
Data OFST2 on the output side and data OFST1 in the middle correspond to the address of the RAM section 11, and (OFST1-OFST1)
ST0) corresponds to the offset value stored in the offset address ROM 30. In such a delay processing circuit, an input signal is added to data delayed by an offset value and is sequentially input.

FIG. 7 is a program list stored in the microcode ROM 14 to cause the DSP to operate the delay processing circuit. Each instruction from address 0 to address D is executed sequentially.

Next, the operation of this embodiment with the above configuration will be explained. The operation when performing signal delay processing using the DSP of this embodiment is shown in circuit form in FIG. 6, and will be described with reference to FIG. In other words, the input to the delay processing circuit is given as an impulse waveform, and when this impulse input is input to the delay processing circuit, subjected to delay processing, and circulated again, the input signal is delayed by the offset value. It will be added to the data and input, and the delay processing circuit in Figure 6 will calculate the coefficient by β<
When set to 1, the output signal gradually becomes smaller.

The detailed operation will be described below with reference to the overall timing chart of the operation of the delay processing circuit shown in FIG. 8 and the timing chart of the main operation of the RAM section 11 shown in FIGS. 9 and 10.

When the DSP performs the above-mentioned delay processing, each instruction (microprogram) from address 0 to address D is sequentially executed according to the program list shown in FIG. 7 stored in the microcode ROM 14. That is, the microprogram stored in the microcode ROM 14 is sequentially read out by the outputs CT1 to CT7 of the counter 22. At this time, the counter 22 operates as an address counter and receives the clock signals CK1 and CK1 shown in FIG.
Outputs CT1 to CT7 are sent to the microcode ROM 14 in synchronization with CK2. The microprogram read from the microcode ROM 14 is clock signal CK2.
The signal is latched into the MC register 25 at a timing synchronized with , and then supplied to the offset address ROM 30 , SA register 38 , coefficient ROM 12 and operation decoder 24 .

Then, by specifying an address in the lower 0 to 4 bits of the microprogram in the offset address ROM 30 and reading out the offset value corresponding to the delay time, the value of the offset data from the offset address ROM 30 and the counter 22 are output CT of
By adding the value 8 to 22 (PCU), data delayed by the offset with respect to the signal input from the RAM section 11 is read out. Further, at this time, the values of the lower 0 to 4 bits of the microprogram are latched as they are in the SA register 38 in synchronization with the signal ΦMA. Coefficient R.O.
In M12, the coefficients used for calculation are designated and stored by the lower 0 to 4 bits of the microprogram. Furthermore, the operation decoder 24 reads out the instruction O.
P0 to P7 are decoded and various control signals are generated and output.

First, in the first instruction cycle (address 0) of delay processing, as shown in the detailed timing chart in FIG. Output processing is performed. In this case, instructions OP5 to OP7
3 bits become [011]. Offset address R
Offset value stored in OM30 (address OF
ST1) is connected to the ALU 13 via the three-state gate 31 which is open at the timing when the signal GOFST becomes "H".
is supplied to one terminal A of the counter 22, and the output C from the counter 22
The values of T8 to T23 (PCU) are also transferred to the other terminal B of the ALU 13 via the three-state gate 32 at the same timing.
supplied to Then, these two values are added by the ALU 13, and the result is supplied to the MA register 37. In addition, the SA register 38 contains the lower 0 to
A 4-bit value is supplied as is, and this is used to select data in the submemory 92. Then the signal ΦM
The data supplied to the MA register 37 and the SA register 38 are each latched at the timing when A becomes "H".

Next, in the processing of address 1, coefficient β is set. That is, instructions OP7, OP6=[
10], the signal ΦCNST is generated at the timing of the clock signal CK2 and the CONST register 2 is generated.
At the same time, the address of the coefficient ROM 12 is specified by the 5 bits of the instructions OP4 to OP0, and the coefficient β is read from the coefficient ROM 12 using OP4 to 0 as the address and supplied to the CONST register 26. Next, the coefficient β is latched into the CONST register 26 in synchronization with the signal ΦCNST from the operation decoder 24. Also, at this time, the data read at address 0 is MR
It is latched into register 40.

Now, to explain the operation of the internal circuit of the RAM section 11 when reading data at address 0 and address 1, the RAM section 11 receives data input from the microcode ROM 14 via the SA register 38. The MR register 4 uses 0 to 4 bits (i.e., 5 bits long) instruction data and operation data input from the ALU 13 via the MA register 37 as an address.
Read data is output to data bus 28 via 0. That is, during this read, the signal MEMW from the operation decoder 24 becomes [1], and the ROM 95,
Data from the main memory 91 via the three-state gate 98 is input to terminal A of the ALU 93, and data output one sampling period ago is input from the sub memory 92 to terminal B. A
After being added in LU93, the added data is stored in register 9.
6 and output from output port DO.

At this time, the value latched in the register 96 by the output signal of the AND gate 104 is stored in the submemory 92 at the timing when the three-state gate 102 opens.
, and is stored as data from one sampling period before. Note that the timing of latching from the RAM section 11 to the MR register 40 at the time of reading is delayed by one instruction cycle. This is because it takes one cycle of time to output data from main memory 91 to output port DO. Furthermore, in the write command cycle, data is read into the main memory 91 in the next cycle until it is latched into the MW register 39.

Next, when moving to the next instruction cycle (processing address 2), the 3 bits of instructions OP5 to OP7 become [0
10], and data is moved between registers in the state of the lower 4 bits of instructions OP0 to OP3. That is, when the instructions OP5 to OP7 become [010], the signal ARST outputted from the operation decoder 24 to the ACC register 36 becomes "H", so that the ACC
Register 36 is reset (cleared). Furthermore, when the lower 4 bits of the instructions OP0 to OP3 become [0111], the level of the signal GMEM rises, the three-state gate 45 becomes open, and the MR register 45
The data latched in the M
The signal is supplied to the PY register 29. Then, data from the data bus 28 is latched into the MPY register 29 at the timing when the signal ΦMPY from the operation decoder 24 becomes "H". Therefore, the data latched in the MR register 45 is transferred to the MP via the data bus 28.
It will be transferred to the Y register 29. As a result, the multiplier 27 outputs a value obtained by multiplying the data latched in the MPY register 29 by the coefficient β.

Next, in the processing of address 3, the ALU 13
Perform addition by. At this time, instructions OP5 to OP7 3
The bit is [000], and the target to be added is determined by the lower 4 bits of the instructions OP0 to OP3. And command O
When P5 to OP7 become [000], the signal S output from the operation decoder 24 to the ALU 13
UB becomes [0] and the ALU 13 enters the addition state. At this time, the lower OP3 to OP0 are [1011], and the value of the IN register 41 and the value of the multiplier 27 are specified, so the signal GIN becomes [1] and the three-state gate 44 is in the open state. , the data latched in the IN register 41 is input to the data bus 28, and the signal ΦMPY becomes [1], so that at that timing, the data on the data bus 28 is input to the MPY register 29.
latched to. This value is then multiplied by multiplier 27.

Furthermore, at this time, the signal GOFST becomes [0]
Therefore, when this inverted signal is supplied to the three-state gates 34 and 35 via the inverter 33, these gates 34 and 35 open, so that the output data of the multiplier 27 and the value of the ACC register 36 (=0 ) are added by the ALU 13 and output to the ACC register 36. Also, the clock signal CK2 is output from the operation decoder 24.
The signal ΦACC is output in synchronization with , and the above addition result is
It is latched into the ACC register 36 at the timing when the signal ΦACC falls. As a result, the value of the multiplier 27 is A
It is the same as if it were transferred to the CC register 36.

Next, the process moves to address 4, where the coefficient α is read out from the coefficient ROM 12 using OP4-0 as addresses in the same manner as address 1, and is set in the CONST register 26. As a result, the data latched from the multiplier 27 to the MPY register 29 (i.e.
The value obtained by multiplying the data transferred from the IN register 41 by the coefficient α is output.

Next, in the processing of address 5, the value of the multiplier 27 is transferred to the ACC register 36 as in the case of address 3.
will be forwarded to. In addition, in the processing of address 6, the signal GA
In order to raise the level of CC, the three-state gate 43 opens, the data latched in the ACC register 36 is transferred to the MW register 39 via the data bus 28, and the signal ΦMW becomes "H" at the end timing of address 6.
”, the data supplied in the MW register 39 is latched. This data is then stored in the RAM section 11.
will be memorized.

Next, in the processing of address 7, the signal GO
FST level rises and three-state gate 31
, 32 are open, the offset data read from the offset address ROM30 using the input side data OFST0 as an address and the PCU (CT8 to CT23) are AL
It is added in U13, and the addition result is stored in MA register 37.
Since the signal ΦMA becomes "H" at the end of this instruction cycle, the addition result is
It is latched into the A register 37. Furthermore, the values of OP4 to 0 are set in the SA register 38 at the same latch timing.

Next, the next instruction cycle (address 8)
Then, following the above operation, the value of the MW register 39 is stored in the RAM section 11 in the area indicated by the MA register 37 and the SA register 38. In addition, data OFST2 is stored in the MA register 37 and the SA register 38.
The offset data corresponding to OP4 and the data of OP4 to OP0 are respectively set. That is, the RAM unit 11 receives 0 to 4-bit instruction data inputted from the microcode ROM 14 via the SA register 38 and operation data inputted from the ALU 13 via the MA register 37 as addresses and connects the data bus 28. Data coming through is read via the MW register 39.

Details of this part are shown in the timing chart of FIG. This data writing process will be explained using the internal circuit of the RAM section 11. During data writing, the signal MEMW becomes [0], so the ALU 93 enters the state of subtraction processing, and the signal MEMW is transferred to the inverter 100.
is supplied to the three-state gate 100 via the input port D, so the three-state gate 99 opens and the input port D
The input data led to I is supplied to one terminal A of the ALU 93, and the data output from the sub-memory 92 is supplied to the other terminal B. Then, in the ALU 93, the sub memory 9 receives input data led to the input port DI.
The output data of 2 is subtracted and latched into the register 96 in synchronization with the clock signal CK1. After that, this data is compressed in the ROM 94, and in the second half of the sampling period (CT0=[1] part), the AND gate 10
The output signal 1 is input to the main memory 91 at the timing when the three-state gate 97 is opened. and,
The data is then written into the main memory 91 in synchronization with the signal MMW. At this time, the output signal of the AND gate 105 also becomes "H", so the three-state gate 103 is opened and the data from the input port DI is written into the sub-memory 92 in synchronization with the signal SMW. In this way, when reading data (writing), the data stored in the sub memory 92 is subtracted from the input data and stored in the main memory 91.

At the next instruction cycle (address 9), the coefficient ROM 12 is
is read from OP4~0 as the address and CONS
T register 26 and operation decoder 2
The data indicated by the MA register 37 and the SA register 38 are set in the CONST register 26 in synchronization with the signal ΦCNST from the RAM section 1.
1 and latched into the MR register 40.

Next, as in the case of address 2, ACC
Register 36 is cleared (cycle at address A),
Further, the value of the MR register 40 is transferred to the MPY register 29, and then multiplied by the coefficient γ in the multiplier 27 (cycle of address B). Therefore, the output of the multiplier 27 is the value of the MPY register 29 times the coefficient γ. Next, as in the case of address 5, the output of multiplier 27 is transferred to ACC register 36 and output to the outside via data bus 28 (cycle of address C).

In this way, in this embodiment, when reading data, the data stored in the sub memory 92 is subtracted from the input data and stored in the main memory 91 in differential format, and the input data at this time is is stored in the sub-memory 92, and becomes data from one sampling cycle before the next reading. On the other hand, when writing data, the data from the sub memory 92 is added to the data from the main memory 91 to return to the original value, and the addition result is written to the sub memory 92 so that the next time the data is read, it is one sampling period earlier. This is the data.

Therefore, since data is stored as a differential value, the storage area of the RAM unit 11 as a delay memory can be reduced. Furthermore, with a certain storage area, it is possible to perform signal processing that produces acoustic effects such as reverb and delay that have a longer delay time than conventional ones.

Furthermore, as a unique effect of this embodiment, the output address of the RAM unit 11 as a delay memory can have the value of data input or output one sampling period ago for each input address. Therefore, there is no need to change the hardware configuration in devices such as reverb processing where the address for inputting and outputting data from delay memory must be varied depending on the form of reverberant sound. Any data at the delay address can be input/output freely, increasing the versatility of the DSP.

Although the above embodiment is an example in which the present invention is applied to delay processing of an electronic musical instrument, the present invention is not limited to this, and may be used to perform other signal processing and to store previously processed data. It can be widely applied to devices used for this purpose. Further, the modulation means and the demodulation means may have common parts, or may be configured as separate and independent circuits.

[0072]

[Effects of the Invention] According to the present invention, externally input data and processed data are stored in a differential format to compress the amount of data, so the storage area required for signal processing can be reduced. can. Further, if this signal processing device is used for effect processing of an electronic musical instrument, it is possible to perform signal processing that produces acoustic effects such as reverb and delay that have a longer delay time than conventional ones.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of a signal processing device of the present invention.

FIG. 2 is a circuit diagram showing the internal configuration of the operation decoder of the same embodiment.

FIG. 3 is a circuit diagram showing the internal configuration of the operation decoder of the same embodiment.

[Figure 4] Microprogram instructions OP0 to O of the same embodiment
It is a figure which shows the meaning content of P7.

FIG. 5 is a circuit diagram showing a detailed configuration of a RAM section of the same embodiment.

FIG. 6 is a diagram showing a circuit configuration when performing delay processing using the DSP of the same embodiment.

FIG. 7 is a diagram showing the contents of a command when performing the delay processing of FIG. 6;

FIG. 8 is a timing chart showing the overall operation of the same embodiment.

FIG. 9 is a timing chart showing the operation of the portion mainly commanded by addresses 0 and 1 in the same embodiment.

FIG. 10 is a timing chart showing the operation of the portion mainly commanded by addresses 7 to 9 in the same embodiment.

FIG. 11 is a block diagram of a conventional electronic musical instrument.

[Explanation of symbols]

11: RAM section (storage means) 12: Coefficient ROM 13: ALU (calculation means) 14: Microcode ROM (program storage means) 2
2: Counter 24: Operation decoder 25, 26, 29, 36, 37, 38, 39, 40, 4
1, 42, 96: Register 27: Multiplier 30: Offset address ROM 91: Main memory (main storage means) 92: Sub memory (sub storage means) 93: ALU 94, 95: ROM 106: Modulation means 107: Demodulation means

Claims (1)

[Claims] 1. A program storage means for storing a program for controlling signal processing; a storage means for storing data input from the outside at a constant sampling period and processing data subjected to signal processing as stored data; A signal processing device comprising a calculation means for processing stored data stored in a storage means and input data input and stored from the outside according to a signal processing procedure based on a program stored in the program storage means, The storage means includes a main storage means for storing data in a differential format, a sub-storage means for storing input data before a predetermined sampling period, and a sub-storage means for storing data inputted to the storage means in advance in the sub-storage means. modulating means for storing the value obtained by subtracting the data in the main storage means as difference data, and storing the stored data in the sub-storage means; and adding the data stored in the main storage means and the sub-storage means. and demodulating means for outputting the added data as the stored data and storing the added data in the sub-storage means.