JPH07334151A - Effect adding device and musical sound generating device using same - Google Patents

Abstract

PURPOSE:To provide the effect adding device which performs highly precise effect addition arithmetic and the musical sound generating device which includes the effect adding device and is easily LSIimplemented. CONSTITUTION:The effect adding device is equipped with a 1st arithmetic means 93 which inputs plural series of digital musical sound signals and performs arithmetic processing and a 2nd arithmetic means 94 which is shorter in arithmetic word length than the 1st arithmetic means 93 and can operates simultaneously with the 1st arithmetic means. The musical sound generating device is equipped with a waveform storage means, a musical sound generating means which reads waveform data out of the waveform storage means and generates a musical sound signal, an effect adding means which adds effect, and a delay data storage means which stores the delay data of the musical sound signal for the effect addition arithmetic; and the waveform storage means, musical sound generating means, effect adding means, and delay data storage means are connected to the same data bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an effect adding device and a tone generating device used for an electronic musical instrument and the like, and more particularly to a hardware configuration thereof.

[0002]

2. Description of the Related Art Conventionally, in a musical tone generator such as an electronic musical instrument, a musical tone waveform sample value is stored in a waveform memory and the waveform data is read at a read frequency (address interval) corresponding to a desired pitch. There was a method of generating musical sounds by doing so. And the generated tone signal is DS
An effect addition process such as reverberation has been performed using P (digital signal processor) or the like. Generally, in the reverberation sound generation and filtering processing, calculation processing including a feedback loop requires calculation with high accuracy (calculation word length), and the DSP is equipped with a calculation circuit having a word length necessary for this calculation. Further, in order to add this reverberation effect, it is necessary to delay many musical tone signal sample values, and therefore an external delay memory has been used for that purpose.

[0003]

For example, as the calculation for giving the reverberation effect, not only reverberation signal generation processing including a feedback loop, but also gain control and mixing processing for each tone generation channel do not require much accuracy. But,
There are some processes that require a large amount of processing. However, in the above-described conventional effect addition processing, since all the arithmetic operations are executed by the high-precision arithmetic circuit, it takes time even for the arithmetic operations that do not require precision, and as a result, the processing quality such as reverberation may be reduced. There was a problem that it was causing a decline. Further, when a circuit for performing digital signal processing such as a tone generation circuit or an effect adding circuit is to be integrated in one LSI, it is connected to the waveform memory or the delay memory for adding the effect by L
There was also the problem that the number of SI pins was extremely large, and the SI was large and the unit price was high.

An object of the present invention is to improve the above-mentioned problems of the prior art and to include an effect adding device capable of executing a highly accurate effect adding operation, and an effect adding device, and to generate a musical tone easily in an LSI. The purpose is to provide a device.

[0005]

According to a first aspect of the present invention, in an effect adding device for adding an effect to a musical tone signal, a plurality of series of digital musical tone signals are input and an effect adding operation including a feedback loop is performed. First and second sum-of-products calculation means,
And a second product-sum operation means for performing addition and synthesis processing of digital musical tone signals, the operation word length being shorter than the product-sum operation means of FIG. And

A second aspect of the present invention is, in the musical tone generating apparatus, a waveform storing means, a musical tone generating means for reading waveform data from the waveform storing means to generate a musical tone signal, and a musical tone signal generated by the musical tone generating means. In a musical tone generating device comprising an effect adding means for adding an effect to said effect and a delay data storing means for storing delay data of a musical tone signal for effect adding calculation, a waveform storing means, a musical sound generating means, an effect adding means, The delay data storage means is connected to the same bus.

[0007]

According to the first aspect of the invention, in the effect adding device, the second arithmetic means performs the reverberation signal generation processing including the feedback loop by the first arithmetic means, and has a short arithmetic word length and therefore a small circuit scale. By performing gain control, mixing processing, etc., it is possible to minimize increase in circuit scale and execute high-quality effect addition processing. In the second invention, a circuit for performing digital signal processing, such as a tone generating circuit or an effect adding circuit, is provided in one LSI.
In the case of the integration, it is sufficient that the number of pins of the LSI is equal to the number of signal lines of the bus. Therefore, it is possible to reduce the number of pins and the unit price. The waveform storage means,
To connect the tone generating means, the effect adding means, and the delay data storage means to the same bus and access the waveform storage means and the delay data storage means in a time-division manner, a memory with a high access speed is required. However, high-speed memory is available at low cost in recent years, and there is no problem in this respect.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a block diagram showing a hardware configuration of an electronic musical instrument to which the present invention is applied. The CPU 1 is a microprocessor that controls the entire electronic musical instrument such as key assignment and sound generation control. It also has a timer interrupt circuit. The ROM 2 stores a control program, a tone color parameter, a frequency information table, an operation control microprogram for the effect adding circuit, performance data for automatic performance, and the like. Tone parameters are waveform address information,
The waveform sample initial value, the waveform sampling rate, the envelope control information, and the like relating to the present invention. The frequency information table is a data table for determining the waveform read frequency (address interval) from the pitch (key number) and the waveform sampling rate.

The RAM 3 stores various control data in the musical instrument,
The current state of the panel circuit 4, the input performance data, etc. are stored. The panel circuit 4 includes various switches such as a tone color selection switch, an effect selection switch, an effect addition amount setting switch, a volume setting switch, a display device such as an LED or LCD, and an interface circuit thereof. The keyboard circuit 5 includes, for example, a plurality of keys each having two switches, a scan circuit for reading the states of the switches,
It is composed of a key event detection circuit for detecting key on / off according to a change in the state of a switch, a touch detection circuit for detecting the strength of key depression, and the like.

The tone generation circuit 6 is a circuit for reading out waveform information from a waveform ROM 8 in which waveforms are stored in advance at address intervals corresponding to the pitch of input performance information, and generating a digital tone signal. By the time division operation, 64 channels of tone signals are independently generated at the same time. The effect adding circuit 7 is a circuit for adding, for example, a reverberation effect to the musical tone signal, is composed of an arithmetic circuit, etc., as will be described later, and uses the delay RAM 9 as signal delay means. As shown by the dotted line in FIG. 2, when the musical tone generating circuit 6 and the effect adding circuit 7 are integrated into one LSI, the CPU 1 is connected (bus 12) in order to reduce the number of terminals.
At the same time, the waveform ROM 8 and the delay RAM 9 are also connected by the memory bus 13.

The D / A converter 10 converts the digital musical tone signal into D
/ A convert. The sound system 11 includes an amplifier and a speaker (or headphones, earphones, etc.), amplifies a musical tone signal, and generates a musical tone. In addition to this, MI
A DI interface circuit, a floppy disk, a driver (reading / writing device) for a storage medium such as a memory card may be provided.

FIG. 1 is a block diagram showing the configuration of the tone generation circuit 6. The waveform address generation circuit 20, which will be described in detail later, accumulates frequency information, which is set by the CPU 1, in proportion to the frequency of the musical tone to be generated, and outputs the waveform ROM.
The address WA for reading the waveform sample value from 8 is time-divisionally output for each channel. It also outputs the step signal inc of the fractional part (the fractional part of the address) fr of the phase information of the tone signal and the integer part i for interpolation. The sample interpolation circuit 21, which will be described in detail later, temporarily stores a plurality of waveform sample values read from the waveform ROM 8,
The waveform sample value is interpolated based on the fractional part fr of the phase information output from the waveform address generation circuit 20, and a sample value output W (i + fr) corresponding to the phase information is output.

The envelope generating circuit 22 generates a desired envelope signal by a known method based on the parameters set by the CPU 1. The multiplier 23 multiplies the sample value output W from the interpolation circuit 21 and the envelope signal to generate a digital tone signal, and outputs it to the effect adding circuit 7. The interface circuit 24 is the CPU 1
The data transfer means is provided with a synchronizing circuit for synchronizing the data transfer from the musical tone generating circuit 6 with the operation timing, and the data to be set is supplied to each circuit by the internal bus CD. The timing control circuit 25 includes a counter for designating the time division operation timing of each channel, and generates a clock, an address, a latch signal, etc. for controlling the operation timing of the tone generating circuit 6.

FIG. 3 is a block diagram showing a circuit related to the memory bus 13. Although not shown in FIG. 2, an address control circuit 30 exists between the tone generating circuit 6 and the effect adding circuit 7 and the memory bus 13. This circuit inputs the read address WA of the waveform ROM 8 output from the tone generating circuit 6 and the read or write address DA of the delay RAM 9 output from the effect adding circuit 7, and inputs a common address signal MA and individual enable signals. The signals -CED and -CEW are output.

FIG. 4 is a timing chart showing the relationship between the address signal MA and each enable signal. WA and DA are alternately output to MA, and the waveform sample values of all channels from WA (0) to WA (63) are read in one sampling cycle. Also, -CEW becomes 0 (valid) at the time of WA output, and -CE at the time of DA output.
D becomes 0 (valid). The waveform sample value is read from the waveform ROM 8 to the data bus MD in synchronism with -CEW and is taken into the tone generating circuit 6, and the effect adding circuit 7 accesses the delay RAM 9 in synchronism with -CED.

FIG. 5 shows the waveform address generation circuit 20 of FIG.
3 is a block diagram showing the configuration of FIG. The FN-RAM 40 is
Waveform read frequency (address interval) information (a value smaller than 1 in this embodiment) is stored for each channel 6
This is a 4-word memory, and the content of this memory is the CPU1.
Set by. In cases other than the writing by the CPU 1, the address is designated by the channel designation counter, the read frequency information is latched in the register 41, and is added to the fractional part fr of the phase information by the adder 42. The adder 42 outputs only the fractional part of the addition result,
When the addition result is 1 or more, a carry signal is output as the step signal inc. The output of the adder 42 is written in the ΣaF-RAM 44 via the selector (SEL) 43 as the fractional part fr of the new phase information. In the selector 43, the CPU 1 has a RAM 4
It switches when setting data to 4.

The step signal inc activates an incrementer (+1 adder) 46, and the incrementer 46 adds a value of 1 to the current read address WA to generate a comparator 51.
And to the selector 47. When the step signal inc is not generated, the incrementer 46 outputs WA as it is. The comparator 51 is an incrementer 46.
Is compared with the loop end address read from the LE-RAM 54. If the comparison result does not match, the output value of the incrementer 46 is set to the selector 47.
Output, and if they match, LT-RAM
A selector control signal is generated so that the loop top address read from 52 is output. Selector 47
Output is ΣaI-R as a new read address WA.
It is stored in AM49. The ΣaI-RAM 49 stores the integer part i of the phase information of the musical tone waveform for each channel 64.
It is a word RAM. The waveform address WA is set so that strictly speaking WA = i + 3 because pre-reading for interpolation is required (the CPU sets it as start address information at the start of sound generation). The contents of the five RAMs can all be set from the CPU 1 via the internal bus CD.

FIG. 11 is a conceptual diagram showing the waveform data stored in the waveform ROM 8. The waveform data corresponding to one timbre is stored for a predetermined length from the start of sounding in order to reduce the storage capacity, and the loop top address is set at the beginning of the portion where there is almost no timbre change in the second half. . At the time of reading, reading is started from the start address, the attack part in the first half with a large tone change is read only once, and when the loop end address is reached, it returns to the loop top address again and the waveform of the part with almost no tone change is read. Repeat as many times as necessary. (Fig. 11
The waveform in is for the purpose of description, and is different from the actual one.) Next, the interpolation will be described. FIG. 12 is a conceptual diagram for explaining the interpolation calculation. FIG. 12 (J) shows the relationship between the waveform sample value and the output tone signal level at the start of sound generation (J in FIG. 11), and is shown in FIGS. 12 (K1) and 12 (K2).
Indicates the case in the middle. In this example, 4
Interpolation is performed using one sampling value. Now, the four consecutive sampling values are W (i-1), W
(I), W (i + 1), W (i + 2), and the interpolation coefficients determined by the fractional part fr of the phase information are C (i-1), C
Assuming (i), C (i + 1), and C (i + 2), the interpolation output can be determined by the following formula (* represents multiplication).

W (i + fr) = C (i-1) * W (i-
1) + C (i) * W (i) + C (i + 1) * W (i +
1) + C (i + 2) * W (i + 2).

The interpolation coefficient C is C (i-1) = (1/6) * (fr * (fr * (f
r * (-1) +3) -2) +0), C (i) = (1 /
2) * (fr * (fr * (fr * (1) -2) -1) +
2), C (i + 1) = (1/2) * (fr * (fr *
(Fr * (-1) +1) +2) +0), C (i + 2) =
(1/6) * (fr * (fr * (fr * (1) +0)-
1) +0), and C (i-1) = (1/6) * (fr * (fr * (fr
* (-1) +3) -3) +1), C (i) = (1/6)
* (Fr * (fr * (fr * (3) -6) +0) +
4), C (i + 1) = (1/6) * (fr * (fr *
(Fr * (-3) +3) +3) +1), C (i + 2) =
(1/6) * (fr * (fr * (fr * (1) +0) +
0) +0). Any coefficient (or other coefficient) can be used in the present invention.

In FIG. 12 (K1), the waveform ROM 8 stores only the sample value corresponding to the integer part (i) of the address. When the current value of the phase information (address) is i + fr, the level of the current value Q is obtained from the four sample values (i-1) to (i + 2) and fr by the above-mentioned formula. Then, as shown in FIG.
As shown in 2), when the addresses are accumulated and the phase information exceeds (i + 1), a step signal inc is generated, and the sample value of (i + 3) necessary for interpolation of the current value R (i + 1 + fr) is stored in the waveform memory. It is read out from 8 and stored in the sample interpolation circuit. Note that the sample values from i to (i + 2) have already been read and accumulated.

FIG. 12 (J) shows the state at the start of sounding. When the current value P is between 0 and 1 of the address,
In order to perform the interpolation calculation, sample values W-1, W0, W1 and W2 corresponding to four address values -1, 0, 1, 2 are required. However, since the sample value is not read at the start of sound generation, correct interpolation calculation cannot be performed. Therefore, at the start of sound generation, the CPU 1 transfers the sample value required for the interpolation calculation to the sample interpolation circuit 21. The sample value required for this purpose is stored in the ROM 2, for example. Therefore, the waveform R
The data W3 and subsequent data corresponding to the address 3 may be stored in the OM8, and W-1 to W2 may be stored in the ROM2. At the start of sounding, one sample value is the waveform R
If it is possible to read from the OM8 and use it, it is sufficient to store the data W2 and subsequent data corresponding to the address 2 in the waveform ROM 8, and if the first sample value W0 corresponding to the address 0 is always 0. , W0 need not be stored in ROM2.

FIG. 6 is a block diagram showing the configuration of the sample interpolation circuit 21. 4 RAMs 62, 65, 68,
Reference numeral 71 is a 64-word memory for storing the waveform sample values read from the waveform ROM 8 for each channel. If the integer part of the current address is i, then W (i
The +2) RAM 62 stores the sample value W (i + 2), and similarly, the W (i + 1) RAM 65 stores W (i +).
1), W (i) RAM 68 stores W (i) in W (i-
1) The RAM 71 stores W (i-1). When the step signal inc is generated, the write signal WR is output from the timing control circuit 25, and the data MD (= W (i) read from the waveform ROM 8 is output to the W (i + 2) RAM 62.
+3)) is written and the subsequent W (i + 1) RAM6
5 has W (i + 2), and W (i) RAM68 has W (i + 2).
+1), but W (i) is written in the W (i-1) RAM 71.

Since irrelevant data remains in each RAM at the start of sound generation, a sample value required from the CPU 1 is sent to the internal bus CD and selectors (SEL) 61, 6.
Transfer to each RAM via 4, 67, 70. Registers 63, 65, 69, 72 hold the outputs of the respective RAMs, and a register 60 is for latching the waveform sample value data from the memory bus 13.

C (i + 2) ROM 78, C (i + 1) R
OM79, C (i) ROM80, C (i-1) ROM8
1 is the above-described interpolation coefficients C (i + 2) and C (i
+1), C (i), and C (i-1) are ROMs, and the corresponding interpolation coefficients are read with the phase information fr as an address. Multipliers 73, 74, 75 and 76 multiply the read interpolation coefficient and the interpolation sample value read from each RAM. The output of each multiplier is added by the adder 77, and the interpolated sample value W (i
+ Fr) is output.

FIG. 7 is a block diagram showing the configuration of the effect adding circuit 7. The interface circuit 90 uses the bus 12
And a data synchronization circuit for synchronizing the data transfer from the CPU 1 with the operation timing in the effect addition circuit 7, and the data is stored in each parameter RAM.
91, 92 or the arithmetic operation control circuit 100. The arithmetic operation control circuit 100 includes, for example, an instruction memory that stores an operation control microprogram,
The instruction decoder, which decodes the read instructions, generates various control signals for controlling the arithmetic operation of the effect adding circuit 7.

In the present embodiment, the instruction memory is composed of RAM, and the contents are set by the CPU 1. If it is not necessary to change the operation mode of the effect adding circuit 7, the instruction memory is set to R.
It may be an OM or the control circuit may be designed with wired logic. The parameter RAMs 91 and 92 are memories for storing operation parameters for the main and sub operation circuits 93 and 94, respectively. The stored parameters include input / output gain coefficients, filter coefficients, and reverberation sound creation operations. There are various coefficients, the delay length of the tone signal (the number of delay samples), and the like. These parameters are set by the CPU 1 via the interface circuit 90.

Register file 9 for main and sub
Reference numerals 5 and 96 are mainly composed of a plurality of registers for temporarily storing data in the middle of operation, and are IIRs of primary and secondary degrees.
It is also used as a delay means when implementing a filter.
Data is also exchanged between the input register 99, the output register 98, the external memory interface circuit 97, and the register file. The main register file 95 has a word length of about 32 bits, and the sub register file 95 has a word length of about 20 bits. External memory interface circuit 97
Is an access control circuit of the delay RAM 9 connected to the memory bus 13, and is address information DA of the delay RAM 9.
To send write data to the memory bus, or
Alternatively, the read data is fetched and transferred to the register file 95.

The main and sub arithmetic circuits 93 and 94 have a structure as shown in FIG. 8, for example. In FIG. 8, the multiplier 101 multiplies the data from the register file by the data from the parameter RAM and outputs the result to the barrel shifter 102. The barrel shifter 102 shifts the input data by a desired digit and outputs it to the adder 103. The adder 103 adds the output of the accumulator 104 and the output of the barrel shifter 102, and outputs the result to the accumulator 104. The accumulator 104 is a temporary data storage register, and its output is also output to the register file.

FIG. 9 is a functional block diagram showing the calculation contents of the effect adding process in the effect adding circuit of FIG. In block A, the tone signals of a plurality of channels generated from the tone generating circuit 6 are multiplied by a coefficient corresponding to a desired gain ratio by a multiplier 110, and an adder 11
1 adds and synthesizes. Note that all triangles in FIG. 9 are multipliers, and circles and pluses are adders. The same calculation is performed in the B block, but the coefficient of the multiplier determines how much the signal of the channel is input to the reverberation sound creating unit. In the C block, the tone signals generated from the A block and the D block are respectively multiplied by the coefficient corresponding to the mixing ratio of the reverberation sounds, and added by the adder to obtain the output signal. Above A, B,
The operation of the C block is executed by the sub-arithmetic circuit 94. Therefore, the sub-arithmetic circuit 94 has a multiplier of 16 × 1.
The 2-bit adder has an accuracy of about 24 bits.

In the D block, reverberation sound creation processing is performed. Although various methods of creating reverberation have been proposed,
As an example, the signals delayed by a plurality of delay elements 112 (implemented by the delay RAM 9) having different delay times are respectively multiplied by a predetermined coefficient, and the output signals of the respective multipliers are delayed by the respective delay elements. A reverberant sound is created by adding the output signals of the respective delay elements together and combining them together with the input signal of. This reverberation sound creation calculation is executed by the main calculation circuit 93. Large calculation accuracy is required for the production of reverberant sound as shown in the figure or for calculation including a feedback loop such as an IIR filter. Therefore, the main arithmetic circuit 93 has 24 multipliers.
× 16 bits, and the adder has an accuracy of about 36 bits. Further, it is generally necessary to delay hundreds to tens of thousands of samples as a delay RAM.

FIG. 10 shows a C of an electronic musical instrument to which the present invention is applied.
It is a flow chart which shows the main processing of PU1. When the power is turned on, the CPU 1,
The RAM 3, the tone generation circuit 6, and the registers and memories in the effect addition circuit 7 are initialized. In step S2,
It is determined whether or not there is a panel event, and if the result is affirmative, the process proceeds to step S3. A panel event is a change in the state of a switch on the panel (from off to on or vice versa). In step S3, corresponding panel event processing is performed based on the change in the state of each switch.

In step S4, it is determined whether or not there is a key event. If the result is negative, the process proceeds to step S14, but if the result is affirmative, the process proceeds to step S5. In step S5, key number information and touch information are generated. In step S6, it is determined whether or not the key event is key-on. If the result is affirmative, the process proceeds to step S8. The process proceeds to S7. In step S7, the tone ending process is executed, and when the tone is sufficiently attenuated, the channel assignment is released. If the key is turned on in step S6, the process proceeds to step S8, and the sound corresponding to the key on is assigned to the vacant tone generation channel of the tone generation circuit 6.

In step S9, the tone frequency, tone color, envelope information, etc. are determined based on the key information and the touch information. In step S10, the read start address, the loop top address, and the loop end address, which are determined by the tone color information and the like, are stored in the waveform address generating circuit 20 as ΣaI-RAM 49, LT-
The RAM 52 and the LE-RAM 54 are set. Step S
In 11, the waveform sample initial value corresponding to the read start address of step S10 stored in the ROM 2, for example, is set in each RAM in the sample interpolation circuit 21. In step S12, the frequency information is set in the FN-RAM 40 in the waveform address generation circuit 20. In step S13, envelope information is set in the envelope generation circuit 22. In step S14, MIDI processing, automatic performance processing, effect addition processing, etc. are executed, and the flow returns to step S2.

Although the embodiment has been described above, the following modifications are also possible. Regarding the interpolation calculation, an example of using four sample values before and after is disclosed, but the interpolation calculation using an arbitrary number of sample values of two samples or more before and after is possible. Although the example in which the interpolation coefficient C is stored in the ROM is disclosed, the interpolation coefficient C can also be calculated from the fractional part fr of the phase information based on the above-described equation. Waveform memory is CPU
If it can be accessed from, the plurality of waveform sample values required for the interpolation calculation at the start of sounding may be stored in the waveform memory. Although the reverberation sound addition circuit is disclosed as the effect addition circuit, any effect addition processing such as filter processing can be performed by changing the microprogram of the effect addition circuit, for example.

[0036]

According to the first aspect of the present invention, in the effect addition device, the second arithmetic operation is performed by the first arithmetic means to generate a reverberation signal including a feedback loop, and the arithmetic word length is short and therefore the circuit scale is small. By performing gain control, mixing processing, and the like by means, it is possible to minimize an increase in circuit scale and execute high-quality effect addition processing. In the second invention,
When trying to integrate a circuit that performs digital signal processing such as a tone generation circuit or an effect addition circuit into one LSI, the LS
Since the number of I pins is the same as the number of bus signal lines, it is enough.
It is possible to reduce the number of pins, which has the effect of reducing the unit price.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a musical sound generating circuit 6.

FIG. 2 is a block diagram showing a hardware configuration of an electronic musical instrument of the present invention.

FIG. 3 is a block diagram showing a circuit related to a memory bus 13.

FIG. 4 is a timing chart showing a relationship between an address signal MA and each enable signal.

5 is a block diagram showing a configuration of a waveform address generation circuit 20. FIG.

FIG. 6 is a block diagram showing a configuration of a sample interpolation circuit 21.

FIG. 7 is a block diagram showing a configuration of an effect adding circuit 7.

FIG. 8 is a block diagram showing a configuration of an arithmetic circuit.

FIG. 9 is a functional block diagram showing calculation contents of effect addition processing.

FIG. 10 is a flowchart showing a main process of the CPU 1 of the electronic musical instrument.

FIG. 11 is a conceptual diagram showing waveform data stored in a waveform ROM 8.

FIG. 12 is a conceptual diagram for explaining an interpolation calculation.

[Explanation of symbols]

1 ... CPU, 2 ... ROM, 3 ... RAM, 4 ... Panel circuit, 5 ... Keyboard circuit, 6 ... Tone generating circuit, 7 ... Effect adding circuit, 8 ... Waveform ROM, 9 ... Delay RAM, 10 ... D / A conversion Container, 11 ... Sound system, 12 ... Bus, 13 ... Memory bus

Claims (3)

[Claims] 1. An effect adding device for adding an effect to a musical tone signal, comprising: first product-sum calculating means for inputting a plurality of series of digital musical tone signals and performing an effect adding operation including a feedback loop; And a second product-sum operation unit that has a shorter operation word length than the product-sum operation unit, can operate simultaneously with the first product-sum operation unit, and performs addition and synthesis processing of digital tone signals. Effect adding device. 2. A waveform storage means, a tone generation means for reading out waveform data from the waveform storage means to generate a tone signal, and an effect adding means for adding an effect to the tone signal generated by the tone generation means. In a musical tone generator having a delay data storage means for storing delay data of a musical tone signal for effect addition calculation, a waveform storage means, a musical tone generation means, an effect addition means and a delay data storage means are connected to the same bus. A tone generating device characterized by being 3. The effect adding means according to claim 1 or 2.
3. The tone generating apparatus according to claim 2, wherein the tone generating means and the effect adding means are formed on one integrated circuit.