JPS6140117B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic musical instrument that transfers a set of calculated data to a buffer memory and converts the contents of the buffer memory into musical sounds. As a recent digital waveform generation method, a set of waveform data is calculated, and the data is stored in a group of readable and writable buffer memories corresponding to the number of channels of the tone detection and allocation circuit. A method is used in which the signal is transmitted using an asynchronous frequency/N clock. Here, a specific musical tone frequency assigned to one buffer memory is shown, and N indicates a value twice the maximum harmonic order of the musical waveform. As an electronic musical instrument of this kind, the "double-tone synthesizer" disclosed in Japanese Patent Application Laid-Open No. 52-27621, invented by Ralph Deutschier, converts the output of the tone shift register, which is the buffer memory mentioned above, into a D-A converter to generate musical tones. There is. Based on the detection information of the tone detection and assignment circuit which stores the opening and closing of the keyboard switch as information, the tone shift register is circulated in response to the tone clock, and the contents of the tone shift register are output. At the same time, the system operates to calculate a new set of waveform data. When the waveform data is calculated, the waveform data calculated in the transmission cycle is transmitted to the tone shift register using the tone clock, but it takes time to start or finish transmitting the waveform data to the register. Data that had previously been stored in the buffer memory is directly output by the shift, producing unnecessary musical tones and causing inconvenience in performance. The purpose of the present invention is to improve the above-mentioned drawbacks, and the purpose is to transmit calculated waveform data to a designated buffer memory in a transmission cycle so that correct waveform data is output without generating unnecessary musical tones. The purpose of the present invention is to provide a controlled electronic musical instrument. In order to achieve the above object, the electronic musical instrument of the present invention calculates waveform data for a pressed key, transmits the calculated data to a buffer memory, and transmits the data transmitted to the buffer memory at a speed corresponding to the musical tone frequency. In an electronic musical instrument that reads the data and sends the read data to the acoustic system, the output of the content before the key press in the buffer memory is prevented, and the calculated waveform data is transmitted to the buffer memory and read out from the buffer memory. The present invention is characterized by comprising means for controlling the output data of the buffer memory to be sent to the audio system at the point when the calculated data becomes calculated waveform data. The present invention will be described in detail below with reference to examples. FIG. 1 is an explanatory diagram in which the present invention is applied to the previously proposed Japanese Patent Laid-Open Publication No. 52-27621 "Multiphonic Synthesizer". The proposed example will be outlined below to explain additional parts of the present invention. The double-tone synthesizer 10 shown in the figure causes a sound system 11 to produce a musical tone selected by operating one switch connected to a keyboard switch 12 of an electronic musical instrument. Waveform data is generated by first calculating a set of main data. That is, circuit 10
It operates to synthesize the main data set calculated by the following discrete Fourier series. In equation (1), N = 1, 2, ..., 2W is the number of words in the main data set, q = 1, 2, ..., M is the harmonic number (order), and M = W is the number of words to synthesize the main data set. Cq is the harmonic coefficient for timbre No. 1, and dq is the harmonic coefficient for timbre No. 2. After the main data set has been calculated, the circuit 10 of FIG.
That is, whenever one of the keyboard switches 12 is operated, the tone detection and assignment circuit 1
4 and transmits the detection information to the execution control circuit 16 via line 59. Execution control circuit 16 provides timing to the system and clocks main clock 1.
5 through line 17. A fairly wide range of clock frequencies may be used, but 1.1352MHz is preferred. Execution control circuit 16 provides control signals to predetermined circuits to operate synchronously, and provides control signals through line 18 to tone detection and assignment circuit 14. At the beginning of the calculation cycle, word counter 1
9, the harmonic counter 20, and the adder-accumulator 21 all start operating from their initial states.
That is, each circuit is set to have a value of one. Table 1 below shows the contents of logic blocks within the system used in calculation cycles. The memory address decoder 23 receives the numerical value from the adder-accumulator 21 and decodes the value
sin2π(1×1)/W in sine wave function table 24
Read from. In summary, Table 1 uses the following equation: S _Nq =sinπNq/W (2), and the address of the sine wave function table 24 is abbreviated using the symbolic notation of the following equation. (N×q)≦πNq/W (3) The memory address decoder 25 uses the numerical value contained in the word counter 19 to select either the harmonic coefficient memory Cq26 or the harmonic coefficient memory _dq27 . receive. In addition to selecting the harmonic coefficient memory, the memory address decoder 2
5 addresses the appropriate harmonic number corresponding to each bit time during the calculation cycle as shown in Table 1. In Table 1, the contents of logical blocks in the system are indicated by the following symbols. t: bit time in calculation cycle N: content of word counter 19 q: harmonic number, content of harmonic counter 20 Nq: content of adder-accumulator 21 SA: address of sine wave function table HC: input to multiplier 28 Harmonic coefficient input ADD; input to multiplier 33 MR; word address for input to main register MRC; content of main register at address MR (N×q); πNq/W

[Table] As shown in the above table, the memory address decoder 25 reads the harmonic coefficient C ₁ from the harmonic coefficient memory 26 at time t ₁ . The input signals to multiplier 28 are C ₁ on line 29 and S ₁ on line 30. The output of the multiplier 28 is therefore the number C ₁ S ₁ . The output of the multiplier 28 is input to an adder 33 via a complementer 31 controlled by a phase shifter 32, which will be described later. The main register 34 is a read/write register consisting of a circular shift register whose contents begin with a value of 0 at the beginning of a calculation cycle and whose contents are
At t ₁ , the numerical value C ₁ S ₁ is placed in word address number 1. At time _t2 , word counter 19 is increased to a value of two. The harmonic counter 20 holds the value 1, and this value remains the same for the first 32 cycles of its calculation cycle.
Retained for bit time. Adder-accumulator 21 receives a value q from harmonic counter 20 at each bit time. At time _t2 , the adder-accumulator 21 therefore has the value N=2. The value of S ₂ that matches address (2×1) is transmitted from sine wave function table 24 to multiplier 28 . Also, at time t ₂ , the harmonic coefficient C ₁
is read out from the harmonic coefficient memory 26. The output signal from the multiplier 28 is the number C ₁ S ₂ , which is added to the initial value 0 of word No. 2 in the main register 34, so that the value of C ₁ S ₂ is placed in the word position at time t ₂ . It will be done. The first subroutine of the calculation cycle is repeated for 32 bit times. The contents of the main register 34 at the end of this subroutine are the values shown in the columns t ₁ to t ₃₂ of Table 1 MRC (main register contents). At time _t33 , the second subroutine of the calculation cycle begins. At time t ₃₃ , word counter 19
returns to the initial value 1 because W=32 is selected by the modulo W counter. The second round of the counter 19 is detected by the memory address decoder 25. This detection causes memory address decoder 25 to operate to address harmonic coefficient memory 27 for the next consecutive 32-bit period in this calculation cycle. The second round of word counter 19 is detected by adder-accumulator 21;
The counter 19 is returned to a zero value. Therefore, time
At t ₃₃ adder-accumulator 21 receives the current value 1 from harmonic counter 20 . This value causes the number S ₁ to appear on the next line 30. At the same time, the harmonic coefficient d ₁ appears on the line 29. After multiplication, the number d ₁ S ₁ is added to the first word in the main register 34 according to the first table for bit time t ₃₃ .
This produces the numerical value C ₁ S ₁ +d ₁ S ₁ as shown in the MRC column. The second subroutine of the calculation cycle is repeated in 32 bit times, and at the end of the second subroutine the contents of main register 34 are t ₃₃ as shown in MRC in Table 1.
~t The value shown in the column ₆₄ will be obtained. Similarly, the third and fourth subroutines are
As shown in the table, each time is repeated for 32 bits, and the contents of the first word in main register 34 at time t ₆₅ and time t ₉₇ result in the values shown in the table. This calculation cycle proceeds through a number of subroutines until the last 64 bit time is completed for the value q=32 contained in harmonic counter 20. At the end of this calculation cycle, the value of each address number in the main register 34 is N=1,
2, . . . , 32 are the values given by equation (1) that match the main register address number. However, as shown by equation (1), there is no need to have 64 word numbers in main register 34. As a characteristic of point symmetry of a sine wave function, if half value Zn is found during the calculation cycle, the remaining value can be obtained by the following equation. Zn = −Z ₆₅ − _{N N} = 33, 34, ..., 64 (4) The calculation cycle requires 32 × U × 32 bit times in total, and U synthesizes the data for a complex musical tone. , where U=2. The sine wave function table 24 is the numerical value sin (π/32)
It is composed of a fixed memory that stores θ (θ=1, 2, . . . , 64). Also, the multiplier 28
is configured to operate when the multiplier and multiplicand are both positive. The sine wave function table 24 has a positive value when 0≦θ≦32, and a negative value when 33≦θ≦64, so the memory address decoder tells the phase shifter 32 to indicate “0” in the former case. In the latter case, a "1" signal is sent, and 32 values of "1" and "0" are accumulated. The phase shifter 32 allows operation with only positive input values of the multiplier 28 and also serves to minimize the peak values of the main data set. The phaser 32 then combines the quadrant data received from the memory address decoder 23 with the aforementioned accumulation addressed by q from the harmonic counter 20 using an exclusive OR gate to generate a control signal sent to the complementer 31. Combines with phase data and outputs. In this way, the positive product from multiplier 28 is passed unmodified from complementer 31 to adder 33, or by complementer 31, the input value is complemented and its algebraic sign is effectively invert it. When the above calculation cycle is completed, the execution control circuit 16 starts a data transfer cycle. During a data transfer cycle, the contents of main register 34 are:
Tonal shift register 3 in a carefully controlled manner
5 and 36. Although two tone shift registers are illustrated here, the number can be expanded to any number. Tone clock 37 is designated by tone detection and assignment circuit 14 when the first key is pressed and keyboard switch 12 is actuated. tone clock 37
Preferably, a voltage controlled oscillator VCO is used for and 38. In this embodiment, the tone clock is not regulated by the main clock 15 and operates asynchronously. Tone detection and assignment circuit 14 detects that the key switch is closed and applies a control voltage or detection signal to tone clocks 37, 38, which clocks these clocks at a rate of 64 times the fundamental frequency corresponding to the pressed key. make it work. Tone clocks 37, 38 cause data in tone shift registers 35, 36 to be transferred cyclically at their respective independent clock speeds. When a word containing a sync bit is read from the tone shift register 35, it is detected by the sync bit detector 39. When the sync bit is detected, a phase time signal is sent to tone selector 40. Tone selector 40 designates a particular tone shift register to begin the first subcycle of the data transfer cycle. Once a subcycle is started, it is detected by the synchronization bit detector 39.
The detection of another synchronization bit, such as from tone shift register 36, does not terminate. At the beginning of the first subcycle of the data transfer cycle, the tone selector 40 uses the information signal 41 from the sync bit detector 39 to
The output signal from clock selector 42 is sent over line 43 to main register 34 for varying the clock rate from 5 to the clock rate generated by acoustic clock 37. The word contents of main register 34 are transferred successively to complementer 44. During data transfers from main register 34, adder 33 simply moves the data from one end of the main register to the other without modifying the data. The signal is then sent to the tone selector 40 without being modified by the complementer 44. After the first 32 words are read from main register 34, main register 34
reverses the direction of the second subcycle of the duty cycle so that the remaining 32 words are read back as 32, 31, 30, . . . , 1. In the second subcycle, the contents of the main register are read later in the duty cycle and the complementer 4
4 serves to output the complement (negative value) of each input data word. Tone selector 40 sends data to load selector 45 . Load selectors 45 and 46 either serve to load the respective tone shift registers 35 and 36, or operate the tone shift registers in a circular mode after the corresponding data transfer subcycle is completed. Main register 34 preferably uses a reversible counter to provide bidirectional read control. The above configuration and operation are as in the proposed example, but
As mentioned above, it takes time to start or finish transmitting the waveform data to the tone shift register, and in order to prevent the data previously stored in the tone shift register from being output during that time, the present invention uses the tone shift register. Gates 60 and 61 are provided between 35 and 36 and digital-to-analog (D-A) converters 47 and 48, respectively, for control. Tone shift register 35 shifts main register 34 at a clock rate determined by tone clock 37.
After being loaded with waveform data transferred from the data transfer cycle, the first subcycle of the data transfer cycle is completed.
At the same time, execution control circuit 16 sends a signal on line 62 to open gate 60 and send the waveform data in tone shift register 35 to DA converter 47. The gate 60 is then closed by a signal on line 62 from the execution control circuit 16 when the tone detection and assignment circuit 14 is no longer specified by the release of the keyboard switch 12. The second subcycle begins when a sync bit is detected by sync bit detector 39 from the waveform data read from tone shift register 36. The operation of the second subcycle is similar to that of the first subcycle, with the tone clock 38 used to time the transfer of data from the main register 34, as described above. When the subcycle ends, the execution control circuit 16
sends a signal on line 63, opens gate 61 and transfers the waveform data in tone shift register 36 to D-A.
to converter 48. Then, when the gate 61 is no longer specified by the tone detection and assignment circuit 14 due to key release, the line 6 from the execution control circuit 16 is
Closed at the signal above 3. When a data transfer cycle is completed, execution control circuit 16 initiates a new calculation cycle. While the new calculation cycle is being performed, the waveform data is processed under the control of separate tone clocks 37 and 38.
It is read independently from both tone shift registers 35 and 36. The main data set computed and temporarily stored in the main register 34 in the manner described so far is now expanded into a musical sound waveform corresponding to a switch actuated by a keyboard operation. The waveform data output from each tone shift register 35 and 36 is sent to the gate 60 controlled by the above.
and 61, and is converted into an analog voltage by DA converters 47 and 48. Similarly to the proposed example, the musical sound waveform is amplified in amplifiers 51 and 52, and the necessary rise/release envelope waveform is provided using rise/release generating circuits 53 and 54. The two signals from the two amplifiers are summed in a summer 55 and the output signal is sent to the audio system 11. Although calculation cycles and data transfer cycles are independent of each other, they are programmed to work together. The output tone is generated continuously and without interruption during the calculation cycle. Furthermore, since individual tones are not interrupted during the data transmission cycle, musical tones do not exhibit any discontinuities unless the harmonic coefficients are changed. FIG. 2 is an explanatory diagram showing the configuration of another embodiment of the present invention. The difference from Figure 1 is gates 60 and 61.
are provided after the DA converters 47 and 48, respectively, and similarly controlled by the execution control circuit 16, and the effect is the same as in the case of FIG. Although the tone shift register 16 shown in the embodiments of FIGS. 1 and 2 is comprised of a shift register, it may also be comprised of a read/write memory RAM. Since this read/write memory outputs data when data is written, if the gates 60 and 61 are opened by a signal from the execution control circuit 16 at the start of transmission, correct data will be output. . As explained above, according to the present invention, the proposed example It is possible to prevent the generation of unnecessary sounds due to transfer time lag in the transfer time and generate high-quality musical tones.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention,
FIG. 2 is an explanatory diagram showing the configuration of another embodiment of the present invention, in which 10 is a multitone synthesizer, 11 is an audio system, 12 is a keyboard switch, 14 is a tone detection and assignment circuit, and 15 is a main clock. ,1
6 is an execution control circuit, 19 is a word counter, 20 is a harmonic counter, 21 is an adder-accumulator,
22 is a gate, 23 is a memory address decoder,
24 is a sine wave function table, 25 is a memory address decoder, 26 is a harmonic coefficient memory Cq, 27
is a harmonic coefficient memory dq, 28 is a multiplier, 31 is a complementer, 32 is a phaser, 33 is an adder, 34 is a main register, 35 and 36 are tone shift registers, 3
7 and 38 are tone clocks, 39 is a synchronization bit detector, 40 is a tone selector, 42 is a clock selector,
44 is a complementer, 45 and 46 are load selectors, 47,
48 is a digital-to-analog converter, 51 and 52 are amplifiers, 53 and 54 are rise/release generating circuits, 55 is an adder, and 60 and 61 are gates.

Claims (1)

[Claims] 1. Calculating waveform data for a pressed key, transmitting the calculated data to a buffer memory, reading the data transmitted to the buffer memory at a speed corresponding to the musical tone frequency, and In an electronic musical instrument that sends data to a sound system, the output of the content before the key press in the buffer memory is prevented, the calculated waveform data is transmitted to the buffer memory, and the data read from the buffer memory is calculated. An electronic musical instrument characterized by comprising means for controlling output data of a buffer memory to be sent to an acoustic system when it becomes waveform data. 2. The buffer memory according to claim 1, wherein the buffer memory is configured with a shift register, and the contents of the buffer memory are output from the time when transmission of the calculated waveform data to the buffer memory is completed. electronic musical instrument. 3 Memory that can read and write the buffer memory
2. The electronic musical instrument according to claim 1, wherein the electronic musical instrument is comprised of a RAM, and is configured to output the contents of the buffer memory from the time when transmission of the calculated waveform data to the buffer memory is started.