JPH04367218A - Formation method for low-resistance semiconductor film - Google Patents

Abstract

PURPOSE:To provide a polycrystallatine low-resistance film having a large particle size and oriented grain boundaries. CONSTITUTION:An SiO2 film 2 as an insulator in a thickness of 4000Angstrom is first deposited on an Si substrate 1. The SiO2 film 2 is then resist-patterned; it is etched by a chemical etchant, e.g. buffered hydrofluoric acid or the like; a stepped part 3 at a difference in height of 2000Angstrom is formed. A polycrystalline Si film 4 in a film thickness of 2000Angstrom is formed, by a low-pressure chemical vapor deposition method (LPCVD), on the SiO2 film 2 having the stepped part 3. In addition, As ions are implanted into the whole surface of the polycrystalline Si film 4 under conditions of 5E 15 pieces/cm<2> and 150keV. Thereby, parts 5 other than a part near the edge part of the stepped part 3 are made amorphous, and a polycrystalline region 6 is left near the edge part. Lastly, this specimen is annealed at 650 deg.C for one hour. Thereby, a low- resistance Si film is formed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a low resistance semiconductor film by a so-called recrystallization method.

0002

[Prior Art] The speed response of electronic devices such as LSI is determined by the product of resistance (R) and stray capacitance (C).
RC) is generally determined.

However, if atoms are simply introduced (diffused) into a polycrystalline film, many grain boundaries will occur due to the small grain size, which will act as a potential barrier and reduce the mobility of carriers. is small, many grain boundaries occur,
A problem arises in that atoms precipitate at grain boundaries and active carriers decrease, resulting in high resistance.

In order to solve these problems, conventionally, when forming a polycrystalline Si film on an insulator such as a SiO2 film, one method is to form a polycrystalline Si film on the SiO2 film and A method is adopted in which impurities such as As ions are implanted into the entire surface of the crystalline Si film to form a region in which part of the thickness is amorphous, and then heat treatment is performed to thermally diffuse the impurities throughout the entire thickness to form a polycrystalline film. It was getting worse.

Another method is to form a SiO2 film on a portion of the Si substrate, form an amorphous Si film thereon, and then perform heat treatment to form a solid phase laterally from the Si substrate. The method of growth was adopted.

[0006]

[Problems to be Solved by the Invention] However, with such conventional methods, Si crystal grains can only be grown to a size (~1000 Å) that is approximately the same as the thickness of amorphous Si crystal grains. It was not possible to form a Si film.

[0007] Furthermore, in such conventional methods, a Si substrate must be used, and other substrates such as amorphous cannot be used.

An object of the present invention is to provide a method for forming a polycrystalline low-resistance semiconductor film having crystal grains with large grain sizes and aligned grain boundaries.

[0009]

[Means for Solving the Problems] A method for forming a low-resistance polycrystalline film of the present invention that solves the above-mentioned problems includes forming a polycrystalline semiconductor film on a base material, and then forming a part of the polycrystalline semiconductor film. By ion-implanting impurities that serve as electrically active species into the polycrystalline semiconductor film, an amorphous region and a polycrystalline region in which a polycrystalline portion remains without being amorphous are formed throughout the entire thickness of the polycrystalline semiconductor film, and then The method is characterized in that the polycrystalline region is recrystallized by using the polycrystalline region as a nucleus by performing heat treatment.

A method for leaving a polycrystalline region is to form a step on an insulator, form a polycrystalline film, and implant impurity ions into the entire surface of the polycrystalline film to make it amorphous. Examples include a method of leaving the crystal part as a seed.

[0011] It is particularly preferable that such a polycrystalline region is formed so that it exists only under the step of the underlying material.

3 and 4 are graphs showing the relationship between the sheet resistance of poly-Si and the annealing temperature. FIG. 3 is a graph when the doped ion species is As, and FIG. 4 is a graph when the doped ion species is P. It is. As is clear from Figures 3 and 4, the temperature is 650°C when the doped ion species is As, and 650°C when the doped ion species is P.
The resistance becomes low at 00°C. Since it is desirable to lower the temperature of the process, the temperature of the heat treatment in the present invention is preferably 600 to 650°C.

[0013]

[Operation] In the present invention, by making the interface with the insulator amorphous, the probability of nucleation at the interface is reduced, so that during recrystallization, polycrystalline Si remains laterally crystallized using the remaining polycrystalline region as a nucleus. grow up. Here, since crystals grow laterally, crystal grains grow in the direction of higher growth rate, forming crystal grains with large grain sizes and uniform grain boundaries, resulting in a semiconductor film with low It becomes resistance.

[0014]

【Example】

Example 1 Hereinafter, a method for forming a low resistance semiconductor film will be described with reference to FIGS. 1(a) to 1(d).

First, as shown in FIG. 1(a), a SiO2 film 2 was deposited as an insulator on a Si substrate 1 to a thickness of 4000 Å. Next, as shown in FIG. 1(b), SiO2
The film 2 was patterned with a resist and etched at a temperature of 22°C using a chemical etching solution containing 4.5% buffered hydrofluoric acid.
Etched at an etching rate of 500 Å/min, with a height difference of 2
A step 3 of 000 Å was formed. Next, as shown in FIG. 1C, a polycrystalline Si film 4 having a thickness of 2000 Å was formed on the SiO2 film 2 having the steps 3 by low pressure chemical deposition (LPCVD) under the following conditions.

[0016] SiH4: 50sccm, pressure: 0.3T
orr, temperature: 620°C, deposition rate: 100 Å/min, and As shown in FIG.
Ion dose: 5E15/cm2, acceleration voltage: 150
By implanting under keV conditions, the portion 5 other than the vicinity of the edge of the stepped portion was made amorphous, and a polycrystalline region 6 remained in the vicinity of the edge. Finally, this sample was
C. for 1 hour.

When the plane of the sample prepared in this manner was observed using a transmission electron microscope, it was found that solid phase growth progressed in the lateral direction with the polycrystalline region 6 as the nucleus, resulting in crystals with large grain size and uniform grain boundary direction. A low resistance Si film with grains was formed. Further, the sheet resistance of this sample was 55 Ω·cm.

On the other hand, when the ion implantation conditions are changed to a dose of 5E15/cm2 and an acceleration voltage of 70 keV, and only 1200 Å of the surface is made amorphous, the sheet resistance becomes 650 Ω·cm, and amorphous Si is used instead of poly-Si. When using the method of the present invention, the resistance was 90 Ω·cm, which shows that the resistance of the sheet formed by the method of the present invention is low.

Example 2 The integrated circuit shown in FIG. 2 was fabricated by a conventional method. In FIG. 2, 21 is a p-type substrate, 22 is the collector of the n+ layer, 23 is the n layer, 24 is the base of the p layer, and 25 is the emitter of the n+ layer. 26 is a polycrystalline Si wiring, which was manufactured by the method of the present invention. 27 and 28 are SiO2 films, 29 and 30 are A
1 film, and serve as a collector electrode and a base electrode, respectively.

Next, the manufacturing process of the semiconductor device shown in FIG. 2 will be explained. (1) By ion-implanting As, Sb, P, etc. into the substrate 21 of a predetermined conductivity type (p-type or n-type) (impurity diffusion etc. is also acceptable), the impurity concentration is reduced to 1015 to 1019.
An n+ buried region 22 of [cm-3] is formed. (2) Due to epitaxial technology, etc., the impurity concentration is 10
An n region 23 of 14 to 10<17>[cm<-3>] is formed. (3) n+ region 40 to reduce collector resistance
(impurity concentration is 1017 to 1020 [cm-3]). (4) An insulating film 27 for element isolation is manufactured by a selective oxidation method, a CVD method, or the like. (5) A p region 24 serving as a base region is formed in the active region by ion implantation or the like. (6) After opening an emitter contact in the insulating film 100, a Si polycrystalline layer 2 with a thickness of 200 Å is formed using a low pressure chemical deposition method.
Deposit 6. (7) As ion 5E15/cm2, acceleration voltage 150
After ion implantation at keV, annealing is performed at 650° C. for 1 hour in N2 gas, followed by patterning. (8) After depositing the insulating film 28 and annealing it,
Open the contact. (9) Sputter Al-Si (1%) which will become the electrodes 29 and 30, and then pattern the Al-Si. (10) After alloying the Al-Si electrode, a passivation film is formed.

BPT is completed by the above procedure.

The integrated circuit manufactured in this manner has a low resistance and an improved speed response.

[0023]

According to the method of the present invention, since crystal growth occurs in the lateral direction from the polycrystalline Si region in the amorphous region, only the crystal grains in the direction where the growth rate is high grow large, and the grains A low-resistance Si film is formed that has crystal grains that are large in diameter and have grain boundaries aligned in the same direction. Furthermore, if the method of the present invention is applied to polycrystalline Si wiring of integrated circuits, BPT emitters, etc., high performance can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of each step of the method of the present invention.

FIG. 2 is a schematic cross-sectional view of an integrated circuit manufactured according to the present invention.

FIG. 3 is a graph showing the relationship between annealing temperature and sheet resistance of polycrystalline Si when As is used as the doping ion species.

FIG. 4 is a graph showing the relationship between annealing temperature and sheet resistance of polycrystalline Si when P is used as the doping ion species.

[Explanation of symbols]

1 Si substrate 2　SiO2 film 3 Steps 4 Polycrystalline film 5 Amorphous region 6 Polycrystalline region

Claims (4)

[Claims] 1. A polycrystalline semiconductor film is formed on a base material, and an impurity that becomes an electrically active species is ion-implanted into a part of the polycrystalline semiconductor film, thereby making the polycrystalline semiconductor film amorphous throughout its entire thickness. Formation of a low-resistance semiconductor film characterized by forming an amorphous region and a polycrystalline region in which a polycrystalline portion remains without being amorphized, and performing heat treatment to recrystallize the polycrystalline region using the polycrystalline region as a core. Method. 2. The method according to claim 1, wherein the polycrystalline region has a wide straight line or curved shape. 3. A method as claimed in claim 1 or 2, characterized in that the polycrystalline regions are present over only part of the total thickness. 4. The method according to claim 1, wherein the heat treatment temperature is 600 to 650°C.