JPH04365327A - Manufacture of semiconductor integrated circuig device - Google Patents

Abstract

PURPOSE:To manufacture a MOS-type field effect transistor which includes LDD structure by the ion implantation of only one time. CONSTITUTION:A doped oxide film doped with first conductivity type of donor is deposited on a silicon substrate 1 which includes a gate electrode 3, and then specified heat treatment is performed to diffuse and form each low- concentration first conductivity type region 5 and 6. Moreover, each side wall 7 and 8 is made by etching the doped oxide film 4, and with the mask of each sidewall 7 and 8, the ions of the second conductivity type of donor are implanted under specified conditions into the applicable section of each low-concentration first conductivity type region 5 and 6 so as to change each applicable section into high-concentration second conductivity type region 9 and 10. Furthermore, the heat treatment under specified condition is performed to make the low- concentration first conductivity type regions 11 and 12 low-concentration second conductivity regions 13 and 14.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION This invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for manufacturing a semiconductor integrated circuit device, particularly a MOS (Metal Oxide Semi
LDD (Lightly Doped Drain) in conductor type field effect transistors
This relates to structural improvements.

0002

2. Description of the Related Art Conventionally, in miniaturized MOS type field effect transistors, in order to improve the drain breakdown voltage, it has been common practice to form the drain diffusion layer into an LDD structure. LD of this drain diffusion layer
In the D structure, avalanche breakdown occurs by reducing the impurity concentration in the region near the gate electrode in the drain diffusion layer to be lower than the impurity concentration in other regions, thereby relaxing the electric field in the region. This increases the drain breakdown voltage.

As a conventional method for manufacturing a P-channel MOS field effect transistor having this type of LDD structure, in order to form a drain diffusion layer, first, after forming a gate electrode, an N-type region is formed. There is a method in which a P+ type region is formed and a heat treatment is performed after forming a sidewall for the gate electrode.

A method of manufacturing a conventional P-channel MOS field effect transistor as described above will be explained in detail below with reference to FIGS. 7 to 11.

7 to 11 show a method for manufacturing a P-channel MOS field effect transistor according to the conventional example, in which main steps of the method for manufacturing a P-channel MOS field effect transistor including an LDD structure are sequentially shown. Each is a cross-sectional view schematically shown.

That is, in the conventional method for manufacturing a P-channel MOS field effect transistor including an LDD structure, first, with a gate electrode 3 formed on a silicon substrate 1 via a gate oxide film 2, Using the gate electrode 3 as a mask, arsenic ions are implanted onto each main surface of the silicon substrate 1 to form N- type regions 15 and 16, respectively (FIG. 7). A typical dose at this time is approximately 3 x 1013 cm-2.

[0007] Also, a non-doped oxide film 1 is formed on these entire surfaces.
7 to a thickness of about 3,000 angstroms (FIG. 8), the non-doped oxide film 17 is etched using a predetermined etching technique to form a layer of about 3,000 angstroms on both sides of the gate electrode 3. (FIG. 9).

Next, using each of the sidewalls 7 and 8 as a mask, boron is ion-implanted into the N- type regions 4 and 5 to form P+-type regions 9 and 10, respectively. , 8 are respectively assumed to be N-type regions 11 and 12 (
Figure 10). Again, a typical dose is approximately 5 x 1014 cm-2.

[0009] Thereafter, by performing heat treatment at 900°C for about 30 minutes, a large amount of boron is diffused from each P+ type region 9, 10 because the diffusion coefficient of boron is larger than that of arsenic. Each of the N-type regions 11, 12 at the bottom of each of the sidewalls 7, 8 is changed into a respective P-type region 13, 14 (FIG. 11), thus forming a P-type region containing the desired LDD structure. A channel MOS type field effect transistor is obtained.

0010

[Problems to be Solved by the Invention] However, in the P-channel MOS type field effect transistor including the conventional LDD structure manufactured through the above-mentioned processes, ion implantation is required twice during its manufacture. This has led to the undesirable problem of poor productivity.

[0011] The present invention was made in order to solve the problems of the conventional art, and its purpose is to provide a new type of LDD structure that can be constructed by only one ion implantation. An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device, in particular a method for manufacturing a MOS field effect transistor including an LDD structure.

0012

[Means for Solving the Problems] In order to achieve the above object, a method for manufacturing a semiconductor integrated circuit device according to the present invention forms each sidewall with a doped oxide film doped with a donor of a first conductivity type. In addition, each sidewall is used as a diffusion source to form a required low concentration second conductivity type region.

That is, the present invention is a method for manufacturing a MOS field effect transistor including an LDD structure, in which a gate electrode is formed on a silicon substrate via a gate oxide film, and A step of depositing a doped oxide film doped with a donor of the first conductivity type onto the substrate to a required thickness, and heat treatment under predetermined conditions are performed to form a doped oxide film on the main surface of the silicon substrate using the doped oxide film as a diffusion source. After forming respective sidewalls on both sides of the gate electrode by diffusing a low concentration first conductivity type region into each region and etching the doped oxide film using a predetermined etching technique, A donor of the second conductivity type is ion-implanted under predetermined conditions into each corresponding portion of each of the low-concentration first conductivity type regions using a sidewall mask, and each of these corresponding portions is implanted with a high concentration second conductivity type region. A step of converting the low concentration first conductivity type region into a type region, and then a heat treatment under predetermined conditions to transform each low concentration first conductivity type region into a low concentration second conductivity type region using the ion-implanted second conductivity type donor as a diffusion source. A method of manufacturing a semiconductor integrated circuit device, comprising at least a step of forming a mold region.

[0014]

[Operation] Therefore, in the method of the present invention, in a MOS type field effect transistor including an LDD structure manufactured through the above steps, the device configuration can be easily manufactured by only one ion implantation. .

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention will be described in detail below with reference to FIGS. 1 to 6.

1 to 6 show a method for manufacturing a semiconductor integrated circuit device to which an embodiment of the present invention is applied, in which main steps of a method for manufacturing a P-channel MOS field effect transistor including an LDD structure are shown. FIG. In addition, these figures 1 to 6
In the method of the embodiment shown in FIG. 7, the same reference numerals as in the conventional method shown in FIGS. 7 to 11 indicate the same or corresponding parts.

That is, the method for manufacturing a P-channel MOS field effect transistor including an LDD structure according to this embodiment is to form a gate electrode 3 on a silicon substrate 1 via a gate oxide film 2 in the conventional manner. Condition (Figure 1)
First, the semiconductor substrate 1 including the gate electrode 3 is
Approximately 10wt. After depositing a doped oxide film 4 doped with approximately 3,000 angstroms of arsenic to a thickness of approximately 3,000 angstroms (FIG. 2), heat treatment is performed at 1,100° C. for approximately 30 minutes to remove the arsenic doped into the doped oxide film 4. is diffused onto the main surface of silicon substrate 1 to form N- type regions 5 and 6, respectively (FIG. 3).

Furthermore, by etching the doped oxide film 4 using a predetermined etching technique, side walls 7 and 8 each having a width of about 3000 angstroms are formed on both sides of the gate electrode 3. (Figure 4).

Next, using each of the sidewalls 7 and 8 as a mask, boron ions are implanted into the corresponding portions of the N-type regions 5 and 6 under conditions of approximately 5×10 14 cm −2 . Accordingly, each of these corresponding parts is changed to P+ type regions 9 and 10, and the other parts,
That is, the respective lower portions of the respective sidewalls 7 and 8 are respectively designated as N-type regions 11 and 12 (FIG. 5).

[0020] Thereafter, by performing heat treatment at 900°C for about 30 minutes, as in the conventional case, a large amount of boron is removed from each P+ type region 9, 10 because the diffusion coefficient of boron is larger than that of arsenic. of boron is diffused to transform each N-type region 11, 12 at the bottom of each sidewall 7, 8 into a respective P-type region 13, 14 (FIG. 6). In the method of this embodiment as well, it is possible to easily obtain a P-channel MOS field effect transistor including the desired LDD structure. Thus, a P-channel MOS field effect transistor including an LDD structure can be manufactured.

[0021] In the above embodiment method, a case was described in which a doped oxide film doped with arsenic was used as the doped oxide film of the N-type donor, but if the heat treatment conditions are appropriately set, other oxide films such as phosphorus can be used. A similar effect can be obtained by using a doped oxide film doped with the same N-type donor.
Of course, the effect can be obtained.

[0022]

[Effects of the Invention] As described above in detail through the examples,
According to the inventive method, a P-channel M including an LDD structure
In a method for manufacturing an OS-type field effect transistor, a doped oxide film doped with a donor of the first conductivity type is deposited to a desired thickness on a silicon substrate including a gate electrode, and then heat treatment is performed under predetermined conditions. Using the doped oxide film as a diffusion source, each low concentration first conductivity type region is diffused and formed on the main surface of the silicon substrate, and after the doped oxide film is etched to form each sidewall, each of these regions is A donor of the second conductivity type is ion-implanted under predetermined conditions into the corresponding portions of each low concentration first conductivity type region using a sidewall mask, and each of these corresponding portions is converted into a high concentration second conductivity type region. By changing the structure and performing heat treatment under predetermined conditions again, the donor of the second conductivity type is used as a diffusion source, and each low concentration first conductivity type region becomes a low concentration second conductivity type region.As a result, The method has an excellent feature that a desired semiconductor integrated circuit device can be manufactured extremely easily by just one ion implantation, and the productivity for the manufacturing can be significantly improved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view schematically showing aspects up to gate electrode formation in a method of manufacturing a P-channel MOS field effect transistor including an LDD structure to which an embodiment of the present invention is applied.

FIG. 2 is a cross-sectional view schematically showing an aspect up to depositing a doped oxide film doped with arsenic in the above manufacturing method.

FIG. 3 is a cross-sectional view schematically showing an aspect up to the formation of each N-type region in the above manufacturing method.

FIG. 4 is a cross-sectional view schematically showing an aspect up to the formation of each sidewall in the same manufacturing method.

FIG. 5 is a cross-sectional view schematically showing the steps up to the formation of each P+ type region in the same manufacturing method.

FIG. 6 is a cross-sectional view schematically showing the steps up to the formation of each P-type region in the same manufacturing method.

FIG. 7: After a gate electrode in a method for manufacturing a P-channel MOS field effect transistor including a conventional LDD structure,
FIG. 3 is a cross-sectional view schematically showing a state up to the formation of each N-type region.

FIG. 8 is a cross-sectional view schematically showing an aspect up to depositing a non-doped oxide film in the same manufacturing method.

FIG. 9 is a cross-sectional view schematically showing the steps up to the formation of each sidewall in the same manufacturing method.

FIG. 10 is a cross-sectional view schematically showing an aspect up to the formation of each P+ type region in the same manufacturing method.

FIG. 11 is a cross-sectional view schematically showing an aspect up to the formation of each P-type region in the above manufacturing method.

[Explanation of symbols]

1 Silicon substrate 2 Gate oxide film 3 Gate electrode 4 Doped oxide film 5, 6 doped with arsenic (first conductivity type donor) N- type (low concentration first conductivity type) regions 7, 8
side wall

Claims (1)

[Claims] 1. A method for manufacturing a MOS field effect transistor including an LDD structure, wherein a gate electrode is formed on a silicon substrate via a gate oxide film, and then a gate electrode is formed on the silicon substrate including the gate electrode. A step of depositing a doped oxide film doped with a donor of one conductivity type to a required thickness and a heat treatment under predetermined conditions are performed to form a low-concentration film on the main surface of the silicon substrate using the doped oxide film as a diffusion source. a step of diffusing one conductivity type region into each;
After etching the doped oxide film using a predetermined etching technique to form sidewalls on both sides of the gate electrode, each of the low concentration first conductivity type regions is etched using a mask for each sidewall. A step of ion-implanting donors of the second conductivity type into each corresponding portion under predetermined conditions to transform each corresponding portion into a highly concentrated second conductivity type region, and then heat treatment under predetermined conditions. , using the ion-implanted donor of the second conductivity type as a diffusion source,
A method of manufacturing a semiconductor integrated circuit device, comprising at least the step of converting each of the low concentration first conductivity type regions into a low concentration second conductivity type region.