JPH04364040A - Flattening of inter-layer insulating film - Google Patents
Flattening of inter-layer insulating filmInfo
- Publication number
- JPH04364040A JPH04364040A JP13810191A JP13810191A JPH04364040A JP H04364040 A JPH04364040 A JP H04364040A JP 13810191 A JP13810191 A JP 13810191A JP 13810191 A JP13810191 A JP 13810191A JP H04364040 A JPH04364040 A JP H04364040A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- inter
- layer insulating
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011229 interlayer Substances 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 229920005591 polysilicon Polymers 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 4
- 238000010894 electron beam technology Methods 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 239000000203 mixture Substances 0.000 abstract description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract 2
- 229910052757 nitrogen Inorganic materials 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は層間絶縁膜の平坦化方法
に関し、特に凹凸のある半導体基板表面上に堆積した層
間絶縁膜を平坦化する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for planarizing an interlayer insulating film, and more particularly to a method for planarizing an interlayer insulating film deposited on an uneven surface of a semiconductor substrate.
【０００２】0002
【従来の技術】半導体基板上の表面段差を少なくするた
めに、ホウ素およびリンを含有したシリコン酸化膜（Ｂ
ＰＳＧ膜），またはリンを含有したシリコン酸化膜（Ｐ
ＳＧ膜）を層間絶縁膜として用い、熱処理することによ
りリフローさせ、平坦化する方法が従来より用いられて
いる。[Prior Art] In order to reduce the surface level difference on a semiconductor substrate, a silicon oxide film (B) containing boron and phosphorus is used.
PSG film) or phosphorus-containing silicon oxide film (PSG film) or phosphorous-containing silicon oxide film (PSG film)
Conventionally, a method has been used in which a SG film (SG film) is used as an interlayer insulating film and subjected to heat treatment to reflow and planarize the film.
【０００３】0003
【発明が解決しようとする課題】上述した従来の層間絶
縁膜の平坦化方法では以下に述べるような問題点がある
。Problems to be Solved by the Invention The above-described conventional method for planarizing an interlayer insulating film has the following problems.
【０００４】ＢＰＳＧ膜またはＰＳＧ膜のリフロー処理
により半導体基板表面の平坦化を行う場合、段差パター
ンの密度により平坦化後の形状が異なってしまう。つま
り、パターン密度の大きい所では凸部間の狭い溝が埋め
込まれて非常に良い平坦性が得られるが、パターン密度
が低いと凸部間が広いためここを埋め込むことはできず
、凹凸のある急峻な段差はなくなるが、絶対段差は緩和
されない。つまり、凹凸が平滑化されるのみであり、全
面にわたっての平坦化はできない。このため半導体装置
の製造歩留りが低下する。When the surface of a semiconductor substrate is planarized by reflow processing of a BPSG film or a PSG film, the shape after planarization differs depending on the density of the step pattern. In other words, where the pattern density is high, the narrow grooves between the convex parts are filled in and very good flatness can be obtained, but when the pattern density is low, the gaps between the convex parts are wide and it is not possible to fill in these areas, resulting in uneven surfaces. Steep steps will disappear, but absolute steps will not be alleviated. In other words, only the unevenness is smoothed, and the entire surface cannot be flattened. Therefore, the manufacturing yield of semiconductor devices decreases.
【０００５】本発明の目的は、この様な従来の問題点を
解決し、パターン密度依存性のない層間絶縁膜の平坦化
方法を提供することにある。An object of the present invention is to solve these conventional problems and provide a method for planarizing an interlayer insulating film that is independent of pattern density.
【０００６】[0006]
【課題を解決するための手段】本発明の層間絶縁膜の平
坦化方法は、凹凸のある半導体基板表面に層間絶縁膜を
形成する工程と、この層間絶縁膜の表面にエネルギービ
ームの照射を行った後この層間絶縁膜の表面をエッチン
グする工程とを含むものである。[Means for Solving the Problems] The method for planarizing an interlayer insulating film of the present invention includes the steps of forming an interlayer insulating film on the uneven surface of a semiconductor substrate, and irradiating the surface of this interlayer insulating film with an energy beam. After that, the surface of the interlayer insulating film is etched.
【０００７】[0007]
【作用】一般に広く層間絶縁膜として用いられるＣＶＤ
酸化膜等は、熱処理することによりウェットエッチング
に対するエッチングレートが小さくなる。本発明では、
この現象を利用して半導体基板表面の平坦化を行う。[Operation]CVD is generally widely used as an interlayer insulation film.
When an oxide film or the like is heat-treated, the etching rate with respect to wet etching is reduced. In the present invention,
This phenomenon is used to planarize the surface of a semiconductor substrate.
【０００８】半導体基板表面に均一なビーム強度を有す
るエネルギービームの照射を行い加熱処理を行う。一定
時間のビーム照射の後、ビーム照射を中止し、その後、
層間絶縁膜のウェットエッチングを行う。以上の工程に
より半導体表面に形成された凸部は、下層にポリシリコ
ン等の熱伝導の良好な層が存在するため冷却速度が速く
、均一なビーム強度のエネルギービームを照射すると凹
部に比べ温度が低くなる。したがって、層間絶縁膜の凸
部は凹部に比べエッチングレートが大きくなり、膜厚を
最適化することによりエッチングにより半導体基板表面
の平坦化を行うことができる。Heat treatment is performed by irradiating the surface of a semiconductor substrate with an energy beam having a uniform beam intensity. After beam irradiation for a certain period of time, stop beam irradiation, and then
Perform wet etching of the interlayer insulating film. The convex portions formed on the semiconductor surface through the above process have a high cooling rate due to the presence of a layer with good thermal conductivity such as polysilicon underneath, and when irradiated with an energy beam of uniform beam intensity, the temperature is lower than that of the concave portions. It gets lower. Therefore, the etching rate of the convex portions of the interlayer insulating film is higher than that of the concave portions, and by optimizing the film thickness, the surface of the semiconductor substrate can be planarized by etching.
【０００９】[0009]
【実施例】次に本発明について図面を参照して説明する
。図１（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.
【００１０】まず、図１（ａ）に示すように、シリコン
基板１上にシリコン酸化膜２を１μｍの厚さに堆積後、
ポリシリコン膜３の段差を形成し、ＢＰＳＧ膜４を堆積
した構造のものを形成した。段差の形成に用いたポリシ
リコン膜３の膜厚は０．５μｍ、ポリシリコン膜のスト
ライプの幅は１μｍ、ポリシリコンストライプの間隔は
１〜１０μｍとした。また、ここでは層間絶縁膜として
ＢＰＳＧ膜４を用い、その膜厚は１．０μｍとした。First, as shown in FIG. 1(a), after depositing a silicon oxide film 2 to a thickness of 1 μm on a silicon substrate 1,
A structure was formed in which a step of the polysilicon film 3 was formed and a BPSG film 4 was deposited. The thickness of the polysilicon film 3 used to form the steps was 0.5 μm, the width of the polysilicon film stripes was 1 μm, and the interval between the polysilicon stripes was 1 to 10 μm. Further, here, a BPSG film 4 was used as an interlayer insulating film, and its film thickness was set to 1.0 μm.
【００１１】次に図１（ｂ）に示すように、エネルギー
ビームとして均一なビーム強度を有する電子ビーム５を
基板表面全面に照射した。電子ビーム照射条件としては
、例えばビーム径１．０ｍｍ、加速電圧１５ｋＶ、ビー
ム電流１ｍＡ、ビーム走査速度０．１〜１ｃｍ／秒、基
板加熱温度５００℃とした。Next, as shown in FIG. 1(b), the entire surface of the substrate was irradiated with an electron beam 5 having a uniform beam intensity as an energy beam. The electron beam irradiation conditions were, for example, a beam diameter of 1.0 mm, an acceleration voltage of 15 kV, a beam current of 1 mA, a beam scanning speed of 0.1 to 1 cm/sec, and a substrate heating temperature of 500°C.
【００１２】次に図１（ｃ）に示すように、フッ酸と純
水を１：１００の割合で混合したエッチング液中でエッ
チング処理を行い、ＢＰＳＧ膜４の表面を平坦化した。Next, as shown in FIG. 1C, the surface of the BPSG film 4 was planarized by etching in an etching solution containing a mixture of hydrofluoric acid and pure water at a ratio of 1:100.
【００１３】次に図１（ｄ）に示すように窒素中で８５
０℃、３０分の熱処理を行い、ＢＰＳＧ膜の平滑化を行
うとともに、膜質の均一化を行った。Next, as shown in FIG. 1(d), 85
Heat treatment was performed at 0° C. for 30 minutes to smooth the BPSG film and make the film quality uniform.
【００１４】[0014]
【発明の効果】以上説明したように本発明によれば、従
来よりも層間絶縁膜の平坦性を良好にできる。したがっ
て製造上の問題点が減少し、半導体装置の製造歩留まり
の向上が期待できるなどの効果がある。As explained above, according to the present invention, the flatness of the interlayer insulating film can be improved better than in the conventional case. Therefore, manufacturing problems are reduced, and the manufacturing yield of semiconductor devices can be expected to be improved.
【図１】本発明の一実施例を説明するための半導体チッ
プの断面図である。FIG. 1 is a cross-sectional view of a semiconductor chip for explaining one embodiment of the present invention.
１ シリコン基板 ２ シリコン酸化膜 ３ ポリシリコン膜 ４ ＢＰＳＧ膜 ５ 電子ビーム 1 Silicon substrate 2 Silicon oxide film 3 Polysilicon film 4 BPSG film 5 Electron beam
Claims (1)
膜を形成する工程と、この層間絶縁膜の表面にエネルギ
ービームの照射を行った後この層間絶縁膜の表面をエッ
チングする工程とを含むことを特徴とする層間絶縁膜の
平坦化方法。1. A method comprising the steps of forming an interlayer insulating film on the uneven surface of a semiconductor substrate, and etching the surface of the interlayer insulating film after irradiating the surface of the interlayer insulating film with an energy beam. A method for planarizing an interlayer insulating film, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13810191A JPH04364040A (en) | 1991-06-11 | 1991-06-11 | Flattening of inter-layer insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13810191A JPH04364040A (en) | 1991-06-11 | 1991-06-11 | Flattening of inter-layer insulating film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04364040A true JPH04364040A (en) | 1992-12-16 |
Family
ID=15213977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13810191A Pending JPH04364040A (en) | 1991-06-11 | 1991-06-11 | Flattening of inter-layer insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04364040A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998052227A1 (en) * | 1997-05-13 | 1998-11-19 | Mitsubishi Denki Kabushiki Kaisha | Dielectric thin film element and method for manufacturing the same |
-
1991
- 1991-06-11 JP JP13810191A patent/JPH04364040A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998052227A1 (en) * | 1997-05-13 | 1998-11-19 | Mitsubishi Denki Kabushiki Kaisha | Dielectric thin film element and method for manufacturing the same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20011030 |