JPH03190233A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the flatness of a material to be etched by providing a process, in which impurities are introduced selectively to sections except the bottom of a recessed section, and a process in which the surface of the material to be etched is flattened. CONSTITUTION:When an inter-layer insulating layer 4 is formed, stepped sections 10A-10C are formed, and phosphorus ions are driven to the surface of the layer 4 from the four directions so as not to be implanted to the bottoms of recessed sections while turning a wafer at every 90 deg. under the conditions of implantation at an implantation angle theta=40 deg.. The impurity dosage is relatively reduced owing to shadowing effect by the protruding sections of the inter-layer insulating layer 4 on the bottoms of the recessed sections just under 10A-10C though the quantity of the impurity dosage is increased in the protruding sections and the side face sections of the recessed sections at that time. Consequently, the protruding sections and the side face members of the protruding sections can be etched selectively. Accordingly, the surface of the inter-layer insulating layer 4 is flattened easily.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method of flattening a material to be etched having a concave portion on its surface, and to improve the flatness of a material to be etched using a simple process. With the aim of providing a semiconductor device with high reliability, impurity ions are more difficult to be implanted into the bottom of the recess than into the parts other than the bottom of the recess in a material to be etched that has a recess on the surface. A step of selectively introducing impurities into a portion other than the bottom of the recess by irradiating at an angle such that the removal rate of the region of the material to be etched into which the impurity ions have been introduced is such that The method is characterized by comprising the step of flattening the surface of the material to be etched by removing the material under conditions higher than the removal speed of the region.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of planarizing a material to be etched that has a recessed portion on its surface.

With the recent demand for higher integration of semiconductor integrated circuit devices, miniaturization of devices is required. As a result, although the cross-sectional area of the wiring is becoming smaller, the length of the wiring tends to become longer, and the resistance of the wiring inevitably increases. On the other hand, wiring layouts are becoming more complex due to higher integration. Multilayer wiring is a structure that solves these problems, but one of the problems in realizing this multilayer wiring structure is how to insulate between the eyebrows. If a silicon oxide film with a thickness of about 1 μm is used for interlayer insulation, there will be no problem with electrical insulation, but if the insulating film is simply deposited on the first layer wiring, the surface of the insulating film will not match the shape of the first layer wiring. As a result, the irregularities and steps become severe, increasing the risk of wire breakage at the step portion when forming the second layer wiring. Therefore, it is necessary to flatten the surface of the glabella insulating layer.

[Conventional technology]

Next, a conventional method of forming multilayer wiring will be explained using FIG. 2, which is a sectional view of a main part of a semiconductor device for explaining the prior art. 1 in the figure is a semiconductor substrate, for example silicon (S
i) A substrate, 2 is a first glabellar insulating layer made of silicon dioxide (SiOz), 3 is a first wiring layer made of aluminum (A I ), 4 is a second glabellar insulating layer made of a low viscosity insulator, 5 is a second wiring layer made of aluminum. First, a chemical vapor deposition method (CVD) is deposited on a silicon substrate 1.
) or using a thermal oxidation method to form the first glabella insulating layer 2 to a thickness of 50 mm.
The first wiring layer 3 is then formed by 4,000 to 5,000 people using a sputtering method and patterned into a desired shape. In this case, each electrode/wiring is formed about 5,000 people apart. On top of this, a second glabellar insulating layer 4 made of a low-viscosity insulator with a thickness of about 8,000 is formed, and further on top of this, a sputtering method is used to form a second glabellar insulating layer 4 with a thickness of about 6000.
Approximately 0 people formed the second wiring layer 5. However, even with this method, the second glabellar insulating layer 4 inherits the shape of the underlying first wiring layer 3, resulting in approximately 5,000 zero step portions as shown at 10A, IOB, and 10C in the figure, which reduces the step difference. was not sufficient. Therefore, wire breakage is likely to occur at portions with poor step coverage as shown by 11 in the figure, resulting in a loss of reliability of the semiconductor device. For this reason, SOG is applied on the second interlayer insulating layer 4 to planarize it, or SOG
After coating, planarization was achieved by etching back. However, these methods still have problems such as the complexity of the process.

[Problem to be solved by the invention]

As described above, conventional efforts have been made to planarize the layer by using a low-viscosity insulator between the first wiring layer 3 and the second wiring layer 5, or by applying SOG coating or etching back. However, these methods require the addition of a new SOG coating process and an etch-back process, resulting in a problem that the process becomes complicated.

An object of the present invention is to provide a highly reliable semiconductor device by improving the flatness of a material to be etched (an interlayer insulating layer) using a simple process.

[Means for explaining the issue]

The above-mentioned problem is to irradiate impurity ions to a material to be etched which has a recessed portion on its surface at an angle such that it is more difficult to implant impurity ions into the bottom of the recessed portion than into the portion other than the bottom of the recessed portion.
A step of selectively introducing impurities into a portion other than the bottom of the recess, and a removal rate of the region of the material to be etched into which the impurity ions have been introduced is higher than a removal speed of the region where the impurity ions have not been introduced. This problem can be solved by configuring the method to include a step of flattening the surface of the material to be etched by removing the material under the following conditions.

[Effect]

In the present invention, impurity ions are irradiated to a material to be etched having a recess at an angle such that it is more difficult to implant the impurity ions into the bottom of the recess than in other parts.
While impurities are actively introduced into the etched layer other than the bottom of the recess, the bottom of the recess is shielded by the convex part, so impurities are not introduced as much as in the convex part or the sides of the recess. . Therefore, when etching is performed, the protrusions and the side surfaces of the recesses into which a large amount of impurities have been introduced will be etched more quickly than the bottoms of the recesses where relatively little impurities have been introduced. Also, the side surfaces of the recess can be selectively removed, and a glabellar insulating layer with good flatness can be formed.

In addition, since the impurity distribution caused by ion implantation determines the final etched shape, by arbitrarily selecting the impurity type, implantation energy, implantation DO3E amount, and implantation angle during ion implantation, it is possible to change the material of the interlayer insulating layer. Furthermore, even if the width or depth of the recess changes, the above-mentioned ion implantation conditions can be set appropriately. Therefore, the flattening process can be performed with high operability. Further, the present invention does not require 5OGI cloth or etch hacking for flattening as in the conventional method, so that flattening can be realized more easily than in the conventional method. And 5
Since there is no need for OC4 cloth or etchback, surface contamination can be reduced compared to conventional methods. Therefore, the present invention is effective even when the concave portions become finer and the uneven step portions increase as semiconductor devices become more highly integrated and finer.

〔Example〕

Next, the present invention will be explained in detail with reference to FIG. 1, which is a sectional view of the main steps for explaining the present invention in detail. In the following examples, the glabellar insulating film was selected as the layer to be etched. However, the layer to be etched is not limited to an insulating film, but may also be a metal or a semiconductor. Now, an explanation of the embodiment will be given.

See Figure 1(a).

In the figure, the same parts as those shown in FIG. 2 are indicated by the same symbols. When forming up to the glabella insulating layer 4 using the conventional technique, step portions as shown by IOA, IOB, and IOC occur. Phosphorus ions (Po) are added to this surface in an amount of DO3E of 1.3
The wafer was placed at 90° under the implantation conditions of x 1015cfi-2, acceleration voltage 360keV, and implantation angle θ (shown) = 40'.
Rotate all the way and drive from 4 directions so as not to inject into the bottom of the recess.

In addition to phosphorus, the injected impure rice seeds also contain arsenic (As) and boron (
B) is also acceptable. Further, as long as the injection is prevented from being injected into the recessed portion, it is not necessary to use the directions in four directions. However, if the number of directions is increased, such as four directions, better planarization can be expected since ions can be implanted into the entire side surface of the recess than if ions are implanted from one direction.

See Figure 1(b).

In this way, the impurity distribution after ion implantation is
The result will be as shown in figure (b). As can be seen from the figure, the convex portion of the interlayer insulating layer and the side surface portion of the concave member have a large amount of impurity doping, whereas IOA and IOB.

The bottom of the recess directly below the IOC has a relatively small amount of impurity doping due to the shadowing effect caused by the projection. In this manner, by performing ion implantation from an oblique direction, it becomes possible to implant the ions into the convex portions and the side surfaces of the concave portions of the glabella insulating layer 4 by utilizing the shadowing effect.

Here, even if a small amount of impurity ions are implanted into the concave portion, there is a large difference in the amount of implantation from the convex portions and the side surfaces of the concave portions, so that the convex portions and side surfaces of the convex portions can be sufficiently selectively etched.

See Figure 1(c).

Next, for example, if isotropic wet etching is performed for 500 minutes using a N Ha OH/H202 solution, the convex portions and side surfaces of the recesses, which are doped with a large amount of impurities, will be etched more quickly than the bottom portions of the recesses, which are doped with a lower amount of impurities. As etching progresses, it is selectively removed. Note that hydrofluoric acid may be used during wet etching, in which case the above NHa OH/H
The etching speed is faster than 20□, so it only takes about 6 minutes. At this time, the etching rate ratio of the convex portions and the concave portions is 1200/300 per minute, and the convex portions and the side surfaces of the concave portions are selectively removed. This etching flattens the surface of the glabellar insulating layer 4.

See Figure 1(d).

A second wiring layer 5 made of aluminum is formed on the glabellar insulating layer 4 flattened in this way.

Since the underlying glabellar insulating layer 4 is flattened, the portions (11 in FIG. 2) with poor step coverage that conventionally occurred in the step portions 10A, IOB, and IOC of the second wiring layer 5 are eliminated, and disconnection can be prevented. Through the above steps, a semiconductor device having a multilayer wiring structure is completed.

[Description of other embodiments] In the above-mentioned embodiments, the ion implantation conditions were implanted impurity phosphorus ions (Pl, implantation angle θ = 40°). After performing the first ion implantation under these conditions, Ion implantation may be performed in the second implantation using arsenic ions (As) as the impurity species and implantation angle θ = 30°.It is also possible to perform ion implantation multiple times in this way.For example, in the first If the desired flatness cannot be obtained by ion implantation, by lowering the implantation angle θ and performing a second ion implantation, it is possible to eliminate the impurities introduced in the first ion implantation.
Impurities are also introduced into the bottom edge portions of 0A, IOB, and 10C, and if an etching process is performed after this, a base with even better flatness can be expected. In the first implantation, about 5,000 ions are implanted in the thickness direction, but it is easier to implant more ions into the convex part than on the side parts of the recessed part, so if the amount of ion implanted on the side part of the recessed part is insufficient, you can reduce the implantation angle. Since the amount of implantation into the side surfaces of the recess can be increased, better planarization can be expected.

Further, by changing the implanted impurity movement, the impurity distribution in the depth direction of the glabellar insulating layer 4 can be changed, so that operability during planarization can be improved. Further controllability (flattening) can be achieved by arbitrarily selecting the DO3E amount and accelerating voltage during the second ion implantation.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to selectively remove the convex portions and the side surfaces of the concave portions of the layer to be etched, which have concave portions that follow the shape of the underlying layer, with good operability. It can be flattened. Therefore, even if the cross-sectional area of the layer formed on it becomes smaller,
There is no need to worry about disconnection. Therefore, the present invention greatly contributes to improving the reliability of semiconductor devices. Further, since planarization can be achieved without using conventional SOG coating or etchback, it also contributes to simplifying the manufacturing process of semiconductor devices.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a main part of a semiconductor device to explain an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a main part of a semiconductor device to explain a conventional technique. In the figure, 0A 0B indicate semiconductor substrate 2: insulating film 3: first electrode/wiring layer 4: glabella insulating layer 5: second electrode/wiring layer 10C: stepped portion 11. Poor step coverage θ: ion implantation angle 1st sound is: 1l-1fL IIQ side Figure 1 Figure (
τ01) Rod @P1 Saikomamenzu figure (t 2) No. ? figure

Claims (1)

[Claims] A material to be etched having a recessed portion on its surface is irradiated with impurity ions at an angle such that impurity ions are more difficult to be implanted into the bottom of the recessed portion than in a portion other than the bottom of the recessed portion, and the etched material is etched into the recessed portion. a step of selectively introducing impurities into a portion other than the bottom; and a condition that the removal rate of the region of the material to be etched into which the impurity ions are introduced is higher than the removal speed of the region where the impurity ions are not introduced. A method for manufacturing a semiconductor device, comprising the step of flattening the surface of the material to be etched by removing the material.