KR20000041436A - Chemical mechanical polishing method of semiconductor device - Google Patents
Chemical mechanical polishing method of semiconductor device Download PDFInfo
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- KR20000041436A KR20000041436A KR1019980057295A KR19980057295A KR20000041436A KR 20000041436 A KR20000041436 A KR 20000041436A KR 1019980057295 A KR1019980057295 A KR 1019980057295A KR 19980057295 A KR19980057295 A KR 19980057295A KR 20000041436 A KR20000041436 A KR 20000041436A
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000005498 polishing Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000000126 substance Substances 0.000 title claims abstract description 13
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 32
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000008021 deposition Effects 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 13
- 150000002500 ions Chemical class 0.000 abstract description 13
- 230000000149 penetrating effect Effects 0.000 abstract description 3
- 239000005368 silicate glass Substances 0.000 abstract description 3
- 229920001296 polysiloxane Polymers 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000002002 slurry Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 235000011007 phosphoric acid Nutrition 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000003449 preventive effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 235000011149 sulphuric acid Nutrition 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
본 발명은 반도체소자의 화학적 기계적 평탄화방법에 관한 것으로, 층간절연막으로 HDP-USG막을 사용함으로써 우수한 연마 평탄화와 안정적인 소자 특성을 확보하여 반도체소자의 수율 및 생산성을 향상시킬 수 있도록 하는 화학적 기계적 평탄화 방법에 관한 것이다.The present invention relates to a chemical mechanical planarization method of a semiconductor device, and by using an HDP-USG film as an interlayer insulating film, a chemical mechanical planarization method for improving the yield and productivity of a semiconductor device by securing excellent polishing planarization and stable device characteristics. It is about.
DRAM제조시 워드라인간 층간절연막을 평탄화하기 위한 기존의 방법은 BPSG막을 증착하고 CMP(chemical mechanical polishing)공정을 이용하여 층간절연막을 평탄화시키나, 연마후 셀과 주변회로간의 단차를 완전히 제거하기 못하므로 후속 노광공정에 어려움이 많다. 이를 개선시키고자 BPSG막 대신에 HDP-USG (high density plasma undoped silicate glass)막을 층간절연막을 대체시켜 필요한 연마 평탄도를 확보하고 있다. HDP-USG막은 워드라인을 형성하면서 발생한 단차를 증착과정에서 이미 국부적으로 평탄화시키기 때문에 이를 연마했을때 BPSG막보다 우수한 평탄도를 얻을 수 있었다. 그러나 BPSG막의 증착시 얻을 수 있는 장점(갭 매립능력, 게더링)들을 HDP-USG막에서는 얻을 수 없다. 즉, 소자가 점점 고집적화됨에 따라 HDP-USG막의 갭 매립 능력이 떨어져 워드라인을 확실히 절연시키지 못할 뿐아니라 후속 공정이 진행되면서 발생되는 이동성 이온(mobile ion)들을 게더링(gathering)하는 효과가 없어서 소자의 안정적인 전기적 특성을 확보할 수 없는 문제가 있다.The conventional method for planarizing the interlayer insulating film between word lines during DRAM manufacturing is to deposit a BPSG film and planarize the interlayer insulating film by using a chemical mechanical polishing (CMP) process, but it does not completely remove the step between the cell and the peripheral circuit after polishing. There are many difficulties in the subsequent exposure process. In order to improve this, HDP-USG (high density plasma undoped silicate glass) film is substituted for interlayer insulating film instead of BPSG film to secure necessary polishing flatness. Since the HDP-USG film is locally planarized in the deposition process of the step generated during the word line formation, the flatness of the HDP-USG film can be obtained better than that of the BPSG film. However, the advantages (gap filling capability, gathering) obtained in the deposition of the BPSG film cannot be obtained in the HDP-USG film. In other words, as the device becomes increasingly integrated, the gap filling capability of the HDP-USG film is poor, so that the word line cannot be reliably insulated, and there is no effect of gathering mobile ions generated during the subsequent process. There is a problem that can not secure a stable electrical characteristics.
도 1a 및 1b는 층간절연막으로 기존의 BPSG막을 증착하고 CMP를 적용하여 평탄화시키는 공정을 나타낸 단면도로서, 워드라인(2)이 형성된 반도체기판(1)상에 ILD(Inter layer dielectric)막(3)을 증착하고 이위에 층간절연막으로 BPSG막(4)을 형성한 후, CMP공정을 이용하여 BPSG막(4)을 연마하여 표면을 평탄화시킨다. BPSG막을 층간절연막으로 사용할 경우 이동성 이온(7)을 게더링하는 능력이 뛰어나고 갭 매립능력이 우수하여 워드라인 간격이 좁고 깊더라도 보이드없이 갭 매립을 할 수 있다. 또한, 주변회로영역과 셀영역의 초기단차를 그대로 반영하여 증착되기 때문에 CMP공정을 도입하여 셀과 주변회로 영역을 평탄화시킨다. 도 1에 나타낸 소자에 CMP공정을 적용할 경우 연마 초기에는 셀영역의 연마속도가 주변회로영역의 연마속도보다 빠르므로 셀과 주변회로간의 단차가 줄어든다. 그러나 단차가 어느 정도 줄어들면 셀영역의 연마속도가 주변회로영역의 연마속도와 비슷하게 되므로 더 이상 연마하더라도 단차가 줄어들지 않아 완전평탄화가 어렵다. 결론적으로 층간절연막으로 BPSG막을 증착하여 연마하더라도 후속공정에서 요구하는 평탄도를 얻을 수 없으나 BPSG막 표면에 존재하거나 추후 발생되는 이동성 이온이 실리콘기판으로 침투되는 것을 막아주는 방지막 역할을 하여 소자의 전기적 특성을 안정적으로 유지할 수 있다. 도 1에서 t1은 워드라인의 초기단차, t2는 BPSG막 연마후 남은 잔여단차를 나타내며, A-A'는 연마 타겟선을 나타낸다.1A and 1B are cross-sectional views illustrating a process of depositing an existing BPSG film as an interlayer insulating film and planarization by applying CMP. An ILD film 3 is formed on a semiconductor substrate 1 on which a word line 2 is formed. Is deposited and the BPSG film 4 is formed on the interlayer insulating film. Then, the BPSG film 4 is polished using the CMP process to planarize the surface. When the BPSG film is used as an interlayer insulating film, the ability to gather the mobile ions 7 is excellent and the gap filling ability is excellent. Thus, even when the word line is narrow and deep, gap filling can be performed without voids. In addition, since the deposition is performed by reflecting the initial steps of the peripheral circuit region and the cell region, the CMP process is introduced to planarize the cell and the peripheral circuit region. When the CMP process is applied to the device shown in FIG. 1, the polishing speed of the cell region is faster than the polishing speed of the peripheral circuit region at the initial stage of polishing, thereby reducing the step between the cell and the peripheral circuit. However, if the step is reduced to some extent, the polishing speed of the cell area is similar to the polishing speed of the peripheral circuit area. In conclusion, even if the BPSG film is deposited and polished as an interlayer insulating film, the flatness required in the subsequent process cannot be obtained. However, the electrical characteristics of the device serve as a preventive film to prevent the migration of ions on the surface of the BPSG film or later generation into the silicon substrate. Can be kept stable. In FIG. 1, t1 represents an initial step of a word line, t2 represents a remaining step remaining after polishing a BPSG film, and A-A 'represents a polishing target line.
도 2a 및 2b는 층간절연막으로 고밀도 플라즈마 실리케이트 글래스(HDP-USG)막을 증착하고 CMP를 적용하여 평탄화시키는 공정을 나타낸 단면도로서, 워드라인(2)이 형성된 반도체기판(1)상에 ILD막(3)을 증착하고 이위에 층간절연막으로 HDP-USG막(6)을 형성한 후, CMP공정을 이용하여 HDP-USG막(6)을 연마하여 표면을 평탄화시킨다. HDP-USG막은 증착과 식각이 반복되면서 증착되는 특성을 가지고 있으므로 셀지역과 주변회로지역의 초기단차를 최소화시키면서 증착된다. 이를 연마타겟선(A-A')까지 연마할 경우 상단히 우수한 연마 평탄도를 얻을 수 있다. 그러나 HDP-USG막은 갭 매립 능력이 BPSG막보다 떨어져 간격이 좁고 깊은 곳까지 증착되지 않아 보이드(5)가 생기며 HDP-USG막 표면에 존재하거나 후속공정에서 발생되는 이동성 이온(7)을 게더링하는 능력이 떨어져 이런 이온들이 실리콘기판으로 침투하는 것을 막아주지 못하여 소자의 전기적 특성을 저하시킨다.2A and 2B are cross-sectional views illustrating a process of depositing a high density plasma silicate glass (HDP-USG) film as an interlayer insulating film and planarization by applying CMP, wherein the ILD film 3 is formed on the semiconductor substrate 1 on which the word line 2 is formed. ) And the HDP-USG film 6 is formed as an interlayer insulating film thereon, and then the surface of the HDP-USG film 6 is polished using a CMP process. The HDP-USG film is deposited with repeated deposition and etching, so that the initial step difference between the cell region and the peripheral circuit region is minimized. When this is polished to the polishing target line A-A ', excellent polishing flatness can be obtained. However, the HDP-USG film has a gap filling capability that is lower than that of the BPSG film and is not deposited to a deeper and deeper space, resulting in voids 5 and gathering of mobile ions 7 present on the surface of the HDP-USG film or generated in a subsequent process. This separation prevents these ions from penetrating the silicon substrate and degrades the electrical properties of the device.
본 발명은 상술한 문제점을 해결하기 위한 것으로, 워드라인 상부에 BPSG막을 얇게 증착하여 깊은 갭을 매립하고 이동성 이온들이 워드라인 또는 실리콘기판으로 침투하는 것을 방지하는 막으로 사용하고 이위에 HDP-USG막을 증착하고 연마함으로써 우수한 연마 평탄도를 확보하여 소자의 수율 및 생산성을 향상시킬 수 있도록 하는 반도체소자의 화학적 기계적 평탄화방법을 제공하는 것을 그 목적으로 한다.The present invention is to solve the above-mentioned problems, by depositing a thin BPSG film on the word line to fill a deep gap and to prevent the mobile ions from penetrating into the word line or silicon substrate, and use the HDP-USG film on the It is an object of the present invention to provide a chemical mechanical planarization method of a semiconductor device which can improve the yield and productivity of the device by securing excellent polishing flatness by depositing and polishing.
상기 목적을 달성하기 위한 본 발명의 반도체소자의 화학적 기계적 평탄화방법은 워드라인이 형성된 반도체기판상에 BPSG막과 HDP-USG막을 차례로 형성하여 이중구조의 층간절연막을 형성하는 단계와, CMP공정을 이용하여 상기 HDP-USG막을 연마하여 표면을 평탄화시키는 단계를 포함하여 구성된다.The chemical mechanical planarization method of the semiconductor device of the present invention for achieving the above object is to form a double layer interlayer insulating film by sequentially forming a BPSG film and HDP-USG film on a semiconductor substrate on which a word line is formed, and using a CMP process And polishing the HDP-USG film to planarize the surface thereof.
도 1a 및 1b는 종래의 BPSG막을 층간절연막으로 사용한 CMP공정을 나타낸 도면,1A and 1B show a CMP process using a conventional BPSG film as an interlayer insulating film;
도 2a 및 2b는 종래의 HDP-USG막을 층간절연막으로 사용한 CMP공정을 나타낸 도면,2A and 2B show a CMP process using a conventional HDP-USG film as an interlayer insulating film;
도 3a 및 3b는 본 발명에 의한 BPSG막과 HDP-USG막을 층간절연막으로 사용한 CMP공정을 나타낸 도면.3A and 3B show a CMP process using a BPSG film and an HDP-USG film as interlayer insulating films according to the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1.반도체기판 2.워드라인1. Semiconductor Board 2. Word Line
3.IDL막 4.BPSG막3.IDL film 4.BPSG film
6.HDP-USG막 7.이동성 이온6.HDP-USG membrane 7.Mobile ion
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 3a 및 3b는 본 발명에 의한 반도체소자의 화학적 기계적 평탄화방법에 관한 것으로, 층간절연막으로 BPSG막과 HDP-USG막의 이중막을 증착하고 CMP를 적용하여 평탄화시키는 공정을 나타낸 단면도이다. 먼저, 도 3a에 나타낸 바와 같이 워드라인(2)이 형성된 반도체기판(1)상에 ILD(Inter layer dielectric)막(3)으로서, 예컨대 MTO, SiN을 100-500Å 증착하고 이위에 층간절연막으로 BPSG막(4)과 HDP-USG막(6)을 차례로 형성한다. 즉, 층간절연막으로 먼저, 이동성 이온에 대한 방지하고 갭 매립특성을 확보하기 위하여 BPSG막(4)을 100-500Å정도로 얇게 증착하고 700-850℃의 온도에서 로(furnace) 또는 RTP장비를 이용하여 열공정을 행한다. 이때 BPSG막에 함유된 보론의 농도는 15-20wt%, 포스포러스의 농도는 4-9wt%가 바람직하다. 상기 공정에 의하면 BPSG막 자체의 플로우 특성상 워드라인 간격이 좁고 깊은 곳에 약간 두껍게 증착되면서 갭 매립이 행해지게 된다. 또한 연마가 완료된 후에 층간절연막 상부에 남아 있거나 추후 발생되는 이동성이온이 실리콘기판으로 침투되는 것을 방지하는 역할을 담당한다. 이어서 BPSG막(4)위에 워드라인의 단차와 연마량을 고려하여 HDP-USG막(6)을 5000-10000Å 증착한다. HDP-USG막은 증착과 식각이 반복되는 증착 특성을 가지고 있으므로 셀영역과 주변회로영역간의 초기단차를 최소화시키면서 증착되어 양호한 평탄화 특성이 얻어지게 된다. 다음에 도 3b에 나타낸 바와 같이 CMP공정을 이용하여 HDP-USG막(6)을 연마하여 표면을 평탄화시킨다. 이때, 산화막 연마시 압력은 1-10psi로 하고, 연마시 사용되는 슬러리의 연마제 농도는 1-30wt%로 하며, 슬러리 연마제 용액의 pH는 2-13의 범위로 하는 것이 바람직하다. 슬러리 안정제는 HCl, H2SO4, NH4OH, HNO3, HF 또는 H3PO4를 각각 사용하거나 순수( DI water)와 섞어서 사용하는 것이 바람직하다. 도면에서 A-A'는 연마 타겟선을 나타낸다.3A and 3B illustrate a chemical mechanical planarization method of a semiconductor device according to the present invention, which is a cross-sectional view illustrating a process of depositing a double layer of a BPSG film and an HDP-USG film as an interlayer insulating film and applying a CMP to planarize it. First, as shown in FIG. 3A, as an interlayer dielectric (ILD) film 3 on the semiconductor substrate 1 on which the word lines 2 are formed, for example, 100-500 Å of MTO and SiN are deposited thereon and BPSG as an interlayer insulating film thereon. The film 4 and the HDP-USG film 6 are sequentially formed. That is, as an interlayer insulating film, first, a thin BPSG film 4 is deposited to a thickness of about 100 to 500 mW in order to prevent mobile ions and to secure a gap filling property, and using a furnace or RTP equipment at a temperature of 700 to 850 ° C. Thermal process is performed. At this time, the concentration of boron contained in the BPSG film is preferably 15-20wt%, the concentration of phosphorus is 4-9wt%. According to the above process, the gap filling is performed while the word line spacing is narrow and a little thick is deposited due to the flow characteristics of the BPSG film itself. It also plays a role of preventing penetration of the mobile ions remaining on the interlayer insulating film after the polishing is completed or generated later to the silicon substrate. Subsequently, the HDP-USG film 6 is deposited 5000-10000 Pa on the BPSG film 4 in consideration of the level of the word line and the polishing amount. Since the HDP-USG film has a deposition characteristic in which deposition and etching are repeated, a good planarization characteristic is obtained by minimizing an initial step between the cell region and the peripheral circuit region. Next, as shown in FIG. 3B, the HDP-USG film 6 is polished using a CMP process to planarize the surface. At this time, the pressure of polishing the oxide film is 1-10psi, the slurry concentration of the slurry used during polishing is 1-30wt%, the pH of the slurry polishing solution is preferably in the range of 2-13. Slurry stabilizers are preferably used with HCl, H2SO4, NH4OH, HNO3, HF or H3PO4, or mixed with DI water. A-A 'in the figure represents the polishing target line.
상기한 바와 같은 본 발명의 평탄화방법에 의하면 층간절연막으로 BPSG막을 증착할 경우의 장점과 HDP-USG막을 증착할 경우의 장점을 살려 우수한 이동성 이온(7)의 게더링효과와 갭 매립능력과 연마평탄도를 확보하여 소자의 수율을 증대시킬 수 있다.According to the planarization method of the present invention as described above, taking advantage of the advantages of depositing a BPSG film as an interlayer insulating film and the advantages of depositing HDP-USG film, the excellent gathering effect of the mobile ions (7), gap filling capability and polishing flatness It is possible to increase the yield of the device to secure.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
본 발명에 의하면, 층간절연막으로 BPSG막과 HDP-USG막의 이중막을 이용함으로써 이동성 이온의 게더링효과와 갭 매립 및 우수한 평탄도를 확보할 수 있다. 이에 따라 화학적 기계적 평탄화공정과 사진식각공정 마진을 극대화하고 안정적인 소자 특성을 유지하여 수율과 생산성을 향상시킬 수 있게 된다.According to the present invention, by using the double film of the BPSG film and the HDP-USG film as the interlayer insulating film, the gathering effect of the mobile ions, gap filling and excellent flatness can be ensured. Accordingly, the chemical mechanical planarization process and the photolithography process margins can be maximized and stable device characteristics can be maintained to improve yield and productivity.
Claims (4)
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| KR1019980057295A KR20000041436A (en) | 1998-12-22 | 1998-12-22 | Chemical mechanical polishing method of semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100444721B1 (en) * | 2001-12-20 | 2004-08-16 | 동부전자 주식회사 | Method of planarization for pre-metal dielectric layer |
| KR100506054B1 (en) * | 2000-12-28 | 2005-08-05 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| CN109300784A (en) * | 2018-09-30 | 2019-02-01 | 上海华力集成电路制造有限公司 | The dielectric layer chemical and mechanical grinding method of semiconductor devices |
-
1998
- 1998-12-22 KR KR1019980057295A patent/KR20000041436A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100506054B1 (en) * | 2000-12-28 | 2005-08-05 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| KR100444721B1 (en) * | 2001-12-20 | 2004-08-16 | 동부전자 주식회사 | Method of planarization for pre-metal dielectric layer |
| CN109300784A (en) * | 2018-09-30 | 2019-02-01 | 上海华力集成电路制造有限公司 | The dielectric layer chemical and mechanical grinding method of semiconductor devices |
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