KR19980040624A - Voidless interlayer insulating film formation method - Google Patents

Abstract

A method of forming an interlayer insulating film that improves and maximizes the gap-fill capability of HDP-CVD in a wiring having any slope is disclosed.

In forming an interlayer insulating film of a semiconductor device,

Depositing and patterning a metal line on a first insulating film for insulating a semiconductor substrate having a predetermined substructure and depositing a second insulating film thereon; and forming an spacer by anisotropically etching the second insulating film. And depositing a third insulating film by HDP-CVD on the resultant, secondly depositing a fourth insulating film by HDP-CVD, and planarizing the fourth insulating film by a chemical mechanical polishing method. It provides a method for forming an interlayer insulating film comprising a.

Therefore, according to the present invention, it is possible to form an interlayer insulating film which can be maximized by improving the gap-fill capability of the HDP-CVD in the wiring having any inclination.

Description

Method of forming void free interlayer insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to a method of forming a void free interlayer insulating film during deposition of an interlayer insulating film after metal wiring.

Due to the high integration of devices according to the development of semiconductor manufacturing technology, metal wirings on a circuit are gradually formed with fine line widths, and the spacing between the wirings is also miniaturized. Currently, in the manufacture of multilayer metal wiring in memory devices and logic devices, a method of forming an interlayer insulating film is a silicon oxide film by chemical vapor deposition (CVD), in particular, plasma enhanced CVD (PECVD). on-the spin to change with a silicon oxide film (SiO ₂₎ to heat treatment after coating the silicon compound of a method of depositing a (SiO ₂₎ and the liquid glass (spin-on glass: less than SOG) method are generally used. However, due to the miniaturization of the wiring gap, the gap (gap-fill) of filling the insulating film between the wiring is gradually reaching the limit with conventional methods and materials. That is, in the conventional method, there is a high possibility that voids and voids may occur without the insulating film being completely filled between fine wirings. In addition, when using SOG etch back to obtain a good flatness, there is a disadvantage that the process is complicated, such as the need to form an additional CVD insulating film. Accordingly, a simpler and newer interlayer insulating film forming process has been developed, and one of them is a method of depositing a silicon oxide film (SiO ₂ ) using high density plasma CVD (HDP CVD).

HDP CVD is a CVD method in which plasma ions of high density are formed by applying an electric field and a magnetic field to have higher ionization efficiency than conventional PECVD, and decomposing and depositing a source gas. In addition, the deposition and the sputter etching can be carried out in-situ by applying a DC bias during the deposition process simultaneously with a high plasma ion density.

1A to 1C are cross-sectional views illustrating characteristics of in-situ deposition and etching of an insulating film using HDP-CVD. It is shown that metal lines are deposited and patterned 14 on any underlying film 12 on the semiconductor substrate 10 to allow deposition and sputter etching to proceed in-situ by HDP-CVD.

Therefore, using this deposition / etch co-progression characteristic, void-free gap-fill of 0.25 μm or less can be achieved more easily than conventional methods. In addition, the insulating film is deposited by HDP-CVD and then planarized by chemical mechanical polishing (CMP), which is easy to apply to multilayer wiring.

However, despite the excellent gap-fill capability of HDP CVD, if the gap shape between the micro-wires has a negative slope, even if the deposition and etch characteristics of the insulating film by HDP CVD are used, voids become difficult to gap-fill. Thus, the gap-filling ability is reduced.

2A to 2B are cross-sectional views for explaining characteristics of in-situ deposition and etching of an insulating film by HDP-CVD when a gap shape has a negative slope between fine wires. The reference figure shows that when the metal line 24 has a negative slope on an arbitrary base film 22 on the semiconductor substrate 20, the void 28 is formed even though the characteristics of depositing and etching the insulating film by HDP CVD are used. Peel becomes difficult, and thus gap-fill ability is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an interlayer insulating film forming method capable of maximizing and improving the gap-fill capability of HDP-CVD in an interconnect having an arbitrary slope.

1A to 1C are cross-sectional views illustrating characteristics of in-situ deposition and etching of an insulating film using HDP-CVD.

2A to 2B are cross-sectional views for explaining characteristics of in-situ deposition and etching of an insulating film by HDP-CVD when the gap shape has a negative slope between fine wirings;

3A to 3F are cross-sectional views showing a method for forming an interlayer dielectric film having improved gap-fill capability of HDP-CVD according to the present invention.

Explanation of symbols for the main parts of the drawings

40 ... silicon substrate 42 ... base film 44 ... metal line

46 a ... spacer 48 ... HDP-CVD insulating film

The present invention for achieving the above object in forming an interlayer insulating film of a semiconductor device,

Depositing and patterning a metal line on a first insulating film for insulating a semiconductor substrate having a predetermined substructure and depositing a second insulating film thereon; and forming an spacer by anisotropically etching the second insulating film. And depositing a third insulating film by HDP-CVD on the resultant, secondly depositing a fourth insulating film by HDP-CVD, and planarizing the fourth insulating film by a chemical mechanical polishing method. It provides a method for forming an interlayer insulating film comprising a.

The metal line may have a positive or negative any slope at the side.

After forming the spacer by the second insulating film, it is preferable to have a positive slope between the gaps.

The thickness of the second insulating film is preferably 10% or less of the gap width so that the opening of the gap is 80% or more of the metal wiring gap.

The second insulating film is made of a material such as SiO ₂ , SiN, or fluorine-doped SiO ₂ .

The third insulating film by HDP-CVD proceeds to in-situ deposition / etch to be gap-filled without voids.

As the third insulating film by HDP-CVD, any one of a material such as a silicon oxide film containing SiH ₄ as a source gas and a fluorine-doped silicon oxide film having SiF ₄ , C ₂ F _6, etc. as a dopant is used.

The fourth insulating film CVD, and spin-use of any of materials such as glass or the like on the silicon oxide film deposited by the method of (SiO ₂₎ or fluorine-doped silicon oxide film (SiO _2).

Therefore, according to the present invention, it is possible to form an interlayer insulating film which can be maximized by improving the gap-fill capability of the HDP-CVD in the wiring having any inclination.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3A to 3F are cross-sectional views illustrating a method of forming an interlayer dielectric film having improved gap-fill capability of HDP-CVD according to the present invention.

First, as shown in FIG. 3A, a metal line is patterned 44 on an arbitrary base film 42 on the silicon substrate 40 by lithography or the like, and then an insulating film 46 for forming a spacer is deposited. In this case, the thickness of the insulating layer 46 is about 10% of the gap width, and a material such as SiO ₂ , SiN, or fluorine-doped SiO ₂ may be used.

Next, the insulating film 46 deposited by an anisotropic etch method having a vertical directionality is etched so that the insulating material does not remain on the upper metal lines but remains only as shown in FIG. 2B to form the spacers 46a. In this manner, as shown in FIG. 3B, even if the metal line has any slope at the side, the spacer may be used to have a positive slope.

When the HDP-CVD insulating film 48 is first deposited by the in-situ deposition / etch process as shown in FIG. 3C, since the gap has a positive slope by the spacer, the gap-fill is easily facilitated. 48a) is grown to allow gap-fill without voids as shown in FIG. 3d.

Here, as shown in FIG. 3E, a second insulating film 50 for planarization is deposited by CVD or the like, and the thickness of the insulating film is thick enough to smooth out unevenness of the surface formed by the HDP-CVD insulating film 48a.

If the secondary insulating film 50 is polished and planarized by CMP, the process of forming a planarized interlayer insulating film (IMD) having a final cross section as shown in FIG. 3F is completed.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

Therefore, according to the present invention, it is possible to form an interlayer insulating film which can be maximized by improving the gap-fill capability of the HDP-CVD in the wiring having any inclination.

Claims (8)

In forming an interlayer insulating film of a semiconductor device, Depositing and patterning a metal line on a first insulating film for insulating a semiconductor substrate having a predetermined substructure and depositing a second insulating film thereon; and forming an spacer by anisotropically etching the second insulating film. And depositing a third insulating film by HDP-CVD on the resultant, secondly depositing a fourth insulating film by HDP-CVD, and planarizing the fourth insulating film by a chemical mechanical polishing method. An interlayer insulating film forming method comprising a. The method of claim 1, wherein the metal line may have a positive or negative any slope at the side. The method of forming an interlayer insulating film according to claim 1, wherein after forming the spacer by said second insulating film, a gap is provided between the gaps. The method of claim 1, wherein the thickness of the second insulating film is 10% or less of the gap width so that the opening of the gap is 80% or more of the metal wiring gap. The method of claim 1, wherein the second insulating film is formed of a material such as SiO ₂ , SiN, or fluorine-doped SiO ₂ . The method of claim 1, wherein the third insulating film by HDP-CVD is subjected to in-situ deposition / etch so that gap-filling is performed without voids. The method of claim 1, wherein the third insulating film by HDP-CVD is any one of a material such as a silicon oxide film containing SiH ₄ as a source gas, and a fluorine-doped silicon oxide film containing SiF ₄ , C ₂ F _6, etc. An interlayer insulating film formation method characterized by using one. The method of claim 1, wherein the fourth insulating film CVD, and spin-the use of any of the materials, such as on glass, such as a silicon oxide film deposited by the method of (SiO ₂₎ or fluorine-doped silicon oxide film (SiO ₂₎ An interlayer insulating film forming method.