KR20010010919A - A method for forming interlayer dielectric layer - Google Patents
A method for forming interlayer dielectric layer Download PDFInfo
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- KR20010010919A KR20010010919A KR1019990030050A KR19990030050A KR20010010919A KR 20010010919 A KR20010010919 A KR 20010010919A KR 1019990030050 A KR1019990030050 A KR 1019990030050A KR 19990030050 A KR19990030050 A KR 19990030050A KR 20010010919 A KR20010010919 A KR 20010010919A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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Abstract
Description
본 발명은 반도체 기술에 관한 것으로, 특히 반도체 소자의 층간절연막 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly to a process for forming an interlayer insulating film of a semiconductor device.
반도체 소자의 고집적화에 따라 고단차의 좁은 간격의 패턴 간극을 내부 공공(void) 없이 절연막으로 채우는 평탄화 기술은 반도체 소자 제조에 있어 중요한 기술 중 하나로 대두되고 있다. 일반적으로 고단차의 좁은 패턴 간극을 매립하기 위하여 기존의 BPSG(borophospho sillicate glass)막을 사용하는 경우 막 안정성 및 갭필(gap-fill) 특성의 한계와 고온 열처리에 의한 결함 발생 등이 유려된다.As the semiconductor devices are highly integrated, planarization technology for filling pattern gaps having high gaps with insulating layers without internal voids has emerged as one of the important technologies in the manufacture of semiconductor devices. In general, when a conventional borophospho sillicate glass (BPSG) film is used to fill a narrow pattern gap of a high step, limitations of film stability and gap-fill characteristics and defects caused by high temperature heat treatment are considered.
또한, 고밀도 플라즈마 화학기상증착법(HDP CVD) 방법에 의하여 좁은 패턴 사이를 매립하고 화학·기계적 평탄화(CMP) 공정으로 연마하여 평탄화 시키는 방법이 있으나, 이 역시 패턴 매립 특성의 한계, 플라즈마에 의한 기판 손상, 패턴 모서리가 깍이는 현상 등으로 그 적용에 한계가 있다.In addition, there is a method of filling between narrow patterns by high-density plasma chemical vapor deposition (HDP CVD) method and polishing and planarizing by chemical and mechanical planarization (CMP) process. In this case, there is a limit to the application due to the sharpening of pattern edges.
최근에는 SiH4, H2O2, H2O 반응소스를 이용하여 -10℃∼100℃ 사이의 저온에서 비도핑(undoped) SiOxHy절연막을 형성하는 기술이 제시되었다. 이러한 반응소스를 이용한 절연막 형성시 수분의 과다 보유로 큰 부피 수축을 가지기 때문에 후속 산화막 증착이 필수적으로 들어가게 된다. 이때, 좁은 패턴 사이를 매립한 산화막에 포함된 수분이 빠져나가면서 마이크로 보이드(microvoid)와 과도한 수축에 의한 응력 집중으로 좁은 패턴 간극의 막질이 매우 취약한 문제점으로 소자 적용에 많은 제약이 있다.Recently, a technique of forming an undoped SiO x H y insulating film at a low temperature between -10 ° C and 100 ° C using a SiH 4 , H 2 O 2 , H 2 O reaction source has been proposed. Since the formation of the insulating film using such a reaction source has a large volume shrinkage due to excessive retention of moisture, subsequent oxide film deposition is essential. At this time, as the moisture contained in the oxide film embedded between the narrow patterns escapes, the film quality of the narrow pattern gap is very weak due to the concentration of stress due to microvoid and excessive shrinkage, and thus there are many limitations in the device application.
첨부된 도면 도 1은 종래기술에 따라 층간절연막이 형성된 소자의 투과전자현미경(TEM) 단면 사진으로써, 미세 전도층 패턴 간극에 존재하는 SiOxHy절연막이 다공질(porous) 상태를 나타내고 있음을 확인할 수 있다.By transmission electron microscope (TEM) cross-section image of the element the interlayer insulating film formed in accordance with the prior art is that the appended drawings Figure 1 technologies, the SiO x H y insulating film existing in the fine conductive layer pattern gap seen that indicates a porous (porous) state Can be.
본 발명은 평탄화 절연막인 SiOxHy절연막 내에 포함된 수분이 후속 공정에서 탈기되는데 따른 마이크로 보이드 발생을 방지할 수 있는 반도체 소자의 층간절연막 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming an interlayer insulating film of a semiconductor device capable of preventing micro voids caused by moisture contained in the SiO x H y insulating film, which is a planarization insulating film, degassed in a subsequent process.
도 1은 종래기술에 따라 층간절연막이 형성된 소자의 투과전자현미경(TEM) 단면 사진.1 is a transmission electron microscope (TEM) cross-sectional photograph of a device in which an interlayer insulating film is formed according to the prior art.
도 2는 본 발명의 일 실시예에 따라 층간절연막이 형성된 반도체 소자의 단면도.2 is a cross-sectional view of a semiconductor device in which an interlayer insulating film is formed in accordance with an embodiment of the present invention.
도 3은 본 발명의 일 실시예에 따라 형성된 SiOxHy절연막 내에 존재하는 수분의 정도를 나타낸 그래프.3 is a graph showing the degree of moisture present in the SiO x H y insulating film formed according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 실리콘 기판10: silicon substrate
11 : 도전층11: conductive layer
12 : 제1 보호절연막12: first protective insulating film
13 : SiOxHy절연막13: SiO x H y insulating film
14 : 제2 보호절연막14: second protective insulating film
A : 플라즈마 처리A: plasma treatment
B : 열처리B: heat treatment
상기의 기술적 과제를 해결하기 위한 본 발명의 특징적인 반도체 소자의 층간절연막 형성방법은, 소정의 전도층이 형성된 기판 전체구조 상부에 제1 보호절연막을 형성하는 제1 단계; 상기 제1 보호절연막 상에 SiOxHy절연막(1≤x≤2, 0.001≤y≤1)을 형성하는 제2 단계; 열처리를 실시하여 상기 SiOxHy절연막의 막질을 치밀화하는 제3 단계; 및 상기 SiOxHy절연막 상에 제2 보호절연막을 형성하는 제4 단계를 포함하여 이루어진다.In order to solve the above technical problem, a method of forming an interlayer insulating film of a semiconductor device according to the present invention may include: a first step of forming a first protective insulating film on an entire substrate structure on which a predetermined conductive layer is formed; Forming a SiO x H y insulating film (1 ≦ x ≦ 2, 0.001 ≦ y ≦ 1) on the first protective insulating film; Performing a heat treatment to densify the film of the SiO x H y insulating film; And a fourth step of forming a second protective insulating film on the SiO x H y insulating film.
즉, 본 발명은 SiOxHy절연막(1≤x≤2, 0.001≤y≤1) 증착 직후, 막 표면에 열처리(또는 플라즈마 처리)를 실시하여 막 표면 부분을 치밀화시켜 수분의 탈기를 억제함으로써 막 내에 수분이 잔류되도록 하여 마이크로 보이드를 방지한다.In other words, immediately after deposition of an SiO x H y insulating film (1≤x≤2, 0.001≤y≤1), heat treatment (or plasma treatment) is performed on the surface of the film to densify the surface of the film to suppress degassing of moisture. Water remains in the film to prevent microvoids.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 2는 본 발명의 일 실시예에 따라 층간절연막이 형성된 반도체 소자의 단면을 도시한 것으로, 이하 이를 참조하여 설명한다.2 is a cross-sectional view of a semiconductor device having an interlayer insulating film formed thereon according to an exemplary embodiment of the present invention.
본 실시예에 따른 공정은 우선, 실리콘 기판(10) 상에 다수의 패턴화된 도전층(11)을 형성하고, 전체구조 상부에 후속 공정시 층간절연막 내의 수분 및 불순물이 도전층(11)으로 확산되는 것을 방지하기 위한 제1 보호절연막(12)을 증착한다. 이때, 제1 보호절연막(12)은 온도 0℃∼800℃, 압력 0.1mtorr∼800torr의 조건으로 SiH4,TEOS(tetraethylotho silicate), O2, O3, N2O 등의 반응 가스를 사용하여 100Å 이상의 산화막으로 형성하거나, SiH4, N2, N2O, NH3가스를 사용하여 질화막, 질화산화막을 형성하거나, 다층 구조로 형성할 수 있다.In the process according to the present embodiment, first, a plurality of patterned conductive layers 11 are formed on the silicon substrate 10, and moisture and impurities in the interlayer insulating film are transferred to the conductive layers 11 during subsequent processing on the entire structure. A first protective insulating film 12 is deposited to prevent diffusion. At this time, the first protective insulating film 12 is reacted with a reaction gas such as SiH 4 , tetraethylotho silicate (TEOS), O 2 , O 3 , or N 2 O under conditions of a temperature of 0 ° C. to 800 ° C. and a pressure of 0.1 mtorr to 800 tor. The oxide film may be formed of an oxide film of 100 Pa or more, or a nitride film, a nitride oxide film may be formed using SiH 4 , N 2 , N 2 O, or NH 3 gas, or may be formed in a multilayer structure.
다음으로, 자연산화막이나 불순물을 제거하기 위한 세정 공정을 실시한다. 세정 공정은 50:1 이상의 BOE(Buffered Oxide Etchant) 용액이나, H2SO4와 H2O2수용액을 2;1∼5:1 부피 비율로 섞어 상온∼150℃ 온도에서 세정할 수 있으며, 불산 용액을 사용할 수도 있다.Next, a washing step for removing the native oxide film or impurities is performed. The cleaning process is a BOE (Buffered Oxide Etchant) solution of 50: 1 or more, or H 2 SO 4 and H 2 O 2 aqueous solution by mixing in a volume ratio of 2: 1 to 5: 1 can be washed at room temperature to 150 ℃ temperature, hydrofluoric acid Solutions may also be used.
이어서, 제1 보호절연막(12) 표면에 플라즈마 처리(A)를 실시한다. 플라즈마 처리(A)는 후속 SiOxHy절연막(13)의 접착력 및 평탄화 특성 향상을 위하여 실시되며, SiOxHy절연막(13) 증착 직전에 동일 장비에서 인-시츄(in-siyu)로 Ar, He, N2, N2O, H2O, H2O2, NH3, O2가스 등을 사용하여 100W 이상의 파워로 10초 이상으로 200∼500℃에서 실시한다. 이때, 플라즈마 처리는 상기 가스들을 둘 이상 동시에 또는 순차적으로 사용하여 실시할 수 있다.Subsequently, plasma treatment A is performed on the surface of the first protective insulating film 12. Plasma treatment (A) is carried out to improve the adhesion and planarization characteristics of the subsequent SiO x H y insulating film 13, and Ar in-siyu in the same equipment immediately before deposition of the SiO x H y insulating film 13 , carried out in He, N 2, N 2 O, H 2 O, H 2 O 2, NH 3, O 200~500 ℃ to more than 10 seconds to more than 100W power using a second gas. In this case, the plasma treatment may be performed using two or more of the above gases simultaneously or sequentially.
다음으로, SiH4/H2O2/H2O 반응소스를 이용하여 -10℃∼100℃ 사이의 저온, 100Torr 이하의 저압하에서 초미세 도전층(11) 패턴 사이를 매립하는 SiOxHy절연막(1≤x≤2, 0.001≤y≤1)(13)을 자체 평탄화 되도록 500Å 이상으로 두껍게 증착한후, 동일 장비에서 연속적으로 열처리(B)를 실시한다. 이때, SiOxHy절연막(13)의 열처리는 막속에 과다하게 포함된 수분이 후속 열공정시 빠져나가면서 패턴 사이에 발생하는 마이크로 보이드를 줄이기 위해 실시되며, 동일 장비 내에서 100 torr 이하의 압력에서 Ar, He, N2, N2O, NH3가스를 사용한 플라즈마로 10초 이상 열처리를 실시하거나, 200℃∼500℃ 온도로 저압에서 10초 이상 열처리를 하여 SiOxHy절연막(13)의 표면 부분을 치밀화한다.Next, using the SiH 4 / H 2 O 2 / H 2 O reaction source, SiO x H y to fill between the ultra-fine conductive layer (11) pattern at a low temperature of -10 ℃ to 100 ℃, low pressure below 100 Torr After the insulating film (1 ≦ x ≦ 2, 0.001 ≦ y ≦ 1) 13 is deposited to a thickness of 500 kV or more so as to be self-planarized, heat treatment (B) is performed continuously in the same equipment. At this time, the heat treatment of the SiO x H y insulating film 13 is carried out to reduce the micro voids generated between the patterns as the moisture contained in the film is released during the subsequent thermal process, at a pressure of 100 torr or less in the same equipment Ar, He, N 2, N 2 O, subjected to heat treatment for 10 seconds or more to the plasma using the NH 3 gas, or for at least 10 seconds heat treatment at a low pressure to a temperature of 200 ℃ ~500 ℃ x H y SiO insulating film 13 Densify the surface part.
다음으로, SiOxHy절연막(13) 상에 SiOxHy절연막(13)에 균열(crack)이 발생하는 것을 방지하기 위한 제2 보호절연막(14)을 증착하고 열처리를 실시한다. 이때, 제2 보호절연막(14)은 TEOS, SiH4, N2O, NH3, O2가스 등을 사용하여 200∼500℃에서 플라즈마 화학기상증착법으로 500Å 이상의 산화막 또는 질화막으로 형성하며, 열처리는 막질의 치밀화 목적으로 O2, N2, O3, N2O, H2+O2등의 가스 분위기에서 5분 이상 열처리를 실시하거나, 300∼1150℃의 온도에서 급속열처리(RTP) 방식으로 열처리를 실시한다.Next, the deposition of the second protective insulating film 14 for preventing the generation SiO x H y insulating film 13 cracks (crack), the SiO x H y insulating film 13 and on a heat treatment. At this time, the second protective insulating film 14 is formed of an oxide film or a nitride film of 500 Å or more by plasma chemical vapor deposition at 200 to 500 ° C. using TEOS, SiH 4 , N 2 O, NH 3 , and O 2 gas. For densification of the film quality, heat treatment is performed for at least 5 minutes in a gas atmosphere such as O 2 , N 2 , O 3 , N 2 O, H 2 + O 2 , or by rapid thermal treatment (RTP) at a temperature of 300 to 1150 ° C. Heat treatment is performed.
첨부된 도면 도 3은 본 발명의 일 실시예에 따라 형성된 SiOxHy절연막 내에 존재하는 수분의 정도를 나타낸 그래프로서, 종래와 같이 열처리(또는 플라즈마 처리) 없이 SiOxHy절연막 상에 곧바로 제2 보호막을 증착한 경우와, 본 발명의 일 실시예에 따라 플라즈마 처리를 실시한 후 제2 보호막을 증착한 경우 각각의 Si-OH 피크(peak)를 나타내고 있다. 3500㎝-1전후에 나타나는 피크가 수분의 정도를 나타낸 것으로, 그래프 상에서 본 발명의 일 실시예에 따른 경우, 종래에 비해 SiOxHy절연막 내에 수분이 많이 함유하고 있음을, 즉 수분의 탈기(outghassing)가 적음을 알 수 가 있다.Figure 3 is a graph showing the degree of moisture present in the SiO x H y insulating film formed according to an embodiment of the present invention, as shown in the prior art directly on the SiO x H y insulating film without heat treatment (or plasma treatment) 2 shows the Si-OH peaks when the protective film is deposited and when the second protective film is deposited after the plasma treatment according to an embodiment of the present invention. The peak appearing before and after 3500 cm -1 indicates the degree of moisture, and according to the exemplary embodiment of the present invention on the graph, it is known that the SiO x H y insulating film contains more moisture than that of the prior art, that is, the degassing of moisture ( It can be seen that there is less outghassing.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
전술한 본 발명은 SiOxHy절연막의 사용으로 종래의 BPSG막이나 HDP 산화막이 가지는 문제점을 해결함은 물론, 후속 공정시 SiOxHy절연막 내의 수분이 탈기하는 것을 억제함으로써 마이크로 보이드를 방지하는 효과가 있으며, 이로 인하여 반도체 소자의 신뢰도를 향상시키는 효과가 있다.The above-described present invention is to prevent micro voids by preventing that the water in the box, as well as the subsequent steps when SiO x H y insulating solve the problem that conventional BPSG film and the HDP oxide film with the use of SiO x H y insulation stripping There is an effect, thereby improving the reliability of the semiconductor device.
Claims (11)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100464862B1 (en) * | 2002-08-02 | 2005-01-06 | 삼성전자주식회사 | Method of Manufacturing of a Semiconductor Device |
| KR100547243B1 (en) * | 1999-12-17 | 2006-02-01 | 주식회사 하이닉스반도체 | Method for manufacturing inter-dielectric layer in semiconductor device |
| KR100832701B1 (en) * | 2002-12-28 | 2008-05-28 | 동부일렉트로닉스 주식회사 | Method For Manufacturing Semiconductor Devices |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100547243B1 (en) * | 1999-12-17 | 2006-02-01 | 주식회사 하이닉스반도체 | Method for manufacturing inter-dielectric layer in semiconductor device |
| KR100464862B1 (en) * | 2002-08-02 | 2005-01-06 | 삼성전자주식회사 | Method of Manufacturing of a Semiconductor Device |
| KR100832701B1 (en) * | 2002-12-28 | 2008-05-28 | 동부일렉트로닉스 주식회사 | Method For Manufacturing Semiconductor Devices |
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