KR20010045429A - Method for forming inter-dielectric layer in semiconductor device - Google Patents
Method for forming inter-dielectric layer in semiconductor device Download PDFInfo
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- KR20010045429A KR20010045429A KR1019990048718A KR19990048718A KR20010045429A KR 20010045429 A KR20010045429 A KR 20010045429A KR 1019990048718 A KR1019990048718 A KR 1019990048718A KR 19990048718 A KR19990048718 A KR 19990048718A KR 20010045429 A KR20010045429 A KR 20010045429A
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 저온에서 패턴사이의 매립특성이 우수한 도핑된 절연막을 적용하여 평탄화된 층간절연막을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a planarized interlayer insulating film by applying a doped insulating film having excellent embedding properties between patterns at a low temperature.
일반적으로 반도체 소자의 고집적화에 따라 고단차의 좁은 간격의 패턴사이를 내부 공공없이 절연막으로 채우는 평탄화는 반도체 소자의 제조에 있어서 중요한 기술로서, 고단차의 좁은 패턴사이를 매립하기 위하여 고농도의 붕소(B) 및 인 (P)을 첨가한 BPSG(Boron Phospho Silicate Glass)막을 사용하여 고온 열처리로 매립, 평탄화한다.In general, the planarization of filling the gap between the narrow gap patterns with high gaps without internal cavities with the high integration of the semiconductor devices is an important technique in the fabrication of semiconductor devices. ) And BPG (Boron Phospho Silicate Glass) added with phosphorus (P) were embedded and planarized by high temperature heat treatment.
그러나, BPSG를 이용하는 방법은 막 안정성 악화 및 BPO4형성에 따른 결정 결함이 발생되는 문제점이 있다.However, the method using the BPSG has a problem that crystal defects due to deterioration of film stability and formation of BPO 4 occurs.
또한 고온의 열처리에 의한 얕은 접합(shallow junction)이 파괴되고, 메탈 전극으로 이용되는 티타늄 실리사이드(TiSi2)의 경우 고온 열공정에 따라 저항이 증가되는등 열처리 온도에 제약을 받게 된다.In addition, the shallow junction is destroyed by the high temperature heat treatment, the titanium silicide (TiSi 2 ) used as a metal electrode is limited by the heat treatment temperature, such as the resistance is increased by the high temperature thermal process.
또한 최근에 고밀도 플라즈마 화학 기상 증착법(High Density Plasma Chemical Vapor Deposition;HDP CVD)방법에 의하여 좁은 패턴사이를 매립하고 화학적 기계적 연마(Chemical Mechanical Polishing;CMP)공정으로 연마하여 평탄화시키는 기술이 제시되었다.Recently, a technique for filling and flattening by narrowing between narrow patterns by a high density plasma chemical vapor deposition (HDP CVD) method and by chemical mechanical polishing (CMP) process has been proposed.
그리고 SiH4+H2O2반응 소오스를 이용하여 -10℃ ~ 50℃ 범위의 저온에서 좁은 패턴사이를 매립하는 비도핑된(updoped) 층간절연막을 형성하는 방법이 제시되었다.In addition, a method of forming an undoped interlayer insulating film which fills in narrow patterns at low temperatures ranging from -10 ° C to 50 ° C using a SiH 4 + H 2 O 2 reaction source has been proposed.
그러나 고밀도 플라즈마 화학 기상 증착(HDP CVD) 방법은 패턴 매립 특성의 한계성, 플라즈마 손실, 패턴 모서리 깍임등 여러가지 문제점이 발생되어 패턴 매립의 적용에는 한계점이 있다.However, the high density plasma chemical vapor deposition (HDP CVD) method has limitations in the application of the pattern embedding due to various problems such as the limitation of the pattern embedding characteristics, the plasma loss, and the cutting of the pattern edges.
또한 SiH4+H2O2반응 소오스를 이용한 비도핑 저온 층간절연막 형성은 이동성 이온을 포획할 수 없고, 층간 절연막중 수분의 과다 보유로 열처리시 패턴사이 매립된 절연막에 포함된 수분이 탈리되고 빠져나간 공간이 그대로 잔류하여, 후에 콘택 형성후 습식식각 용액에 의한 세정시 식각 속도 증가에 의한 과도한 식각으로 인접 콘택이 붙게 되어 배선의 합성을 유발한다.In addition, the formation of the undoped low-temperature interlayer insulating film using the SiH 4 + H 2 O 2 reaction source cannot capture mobile ions, and due to the excessive retention of moisture in the interlayer insulating film, the moisture contained in the insulating film buried between the patterns during heat treatment is desorbed and dropped The space left is left as it is, and after the contact is formed, the adjacent contact is attached by excessive etching due to the increase of the etching rate during the cleaning by the wet etching solution, causing the synthesis of the wiring.
그리고 막 형성 및 치밀화 과정에서 막에 인가되는 과도한 인장응력으로 인하여 후속 열공정 및 배선 형성 공정에서 응력 집중에 의해 막의 깨짐 현상이 나타난다.In addition, due to excessive tensile stress applied to the film during film formation and densification, cracking of the film may occur due to stress concentration in subsequent thermal processes and wiring formation processes.
이하 첨부도면을 참조하여 종래기술에 따른 반도체 소자의 층간절연막의 형성 방법을 설명하기로 한다.Hereinafter, a method of forming an interlayer insulating film of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1b 는 종래기술에 따른 반도체 소자의 층간절연막의 형성 방법을 나타낸 도면이다.1A to 1B illustrate a method of forming an interlayer insulating film of a semiconductor device according to the prior art.
도 1a 에 도시된 바와 같이, 반도체 기판(1)상에 도전층을 증착하고 상기 도전층을 선택적으로 패터닝하여 일정 간격을 갖는 다수개의 배선(2)을 형성한다.As shown in FIG. 1A, a conductive layer is deposited on the semiconductor substrate 1 and the conductive layer is selectively patterned to form a plurality of wirings 2 having a predetermined interval.
이어 상기 다수개의 배선(2)을 포함한 전면에 절연막(3)을 증착한 후, 상기 절연막 상부에 플라즈마 처리를 실시한다.Subsequently, an insulating film 3 is deposited on the entire surface including the plurality of wirings 2, and then plasma processing is performed on the insulating film.
이어 SiH4+H2O2반응 소오스를 이용하여 -10~50℃ 범위의 저온,저압하에서 초미세 패턴사이를 매립하는 비도핑 층간절연막(4)을 형성하고, 자체 평탄화한다.Subsequently, an undoped interlayer insulating film 4 is formed using a SiH 4 + H 2 O 2 reaction source to fill an ultrafine pattern at low temperature and low pressure in the range of −10 to 50 ° C., and planarizes itself.
상기 층간 절연막(4)상에 플라즈마 화학 기상 증착 방법으로 일정 두께의 플라즈마 산화막(5)을 증착하고, 350~800℃에서 열처리한다.A plasma oxide film 5 having a predetermined thickness is deposited on the interlayer insulating film 4 by a plasma chemical vapor deposition method, and heat-treated at 350 to 800 ° C.
그런데 이러한 종래기술은 도 1b 에 도시된 바와 같이, 상기 평탄화된 산화막에 콘택홀을 형성하고 습식식각 용액을 이용하여 세정을 실시하면 초미세 패턴 사이의 절연막 콘택 측벽이 과도하게 손상되게 된다.However, in the related art, as shown in FIG. 1B, when the contact hole is formed in the planarized oxide film and the cleaning is performed using a wet etching solution, sidewalls of the insulating layer contact between the ultrafine patterns are excessively damaged.
본 발명은 상술한 바와 같은 문제점을 해결하기 위해 안출한 것으로서, 패턴사이의 막질을 치밀화함과 동시에 얕은 접합의 파괴를 방지하도록 하는데 적합한 반도체 소자의 평탄화된 층간절연막의 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a method of forming a planarized interlayer insulating film of a semiconductor device suitable for densifying the film quality between patterns and at the same time preventing breakage of shallow junctions. have.
도 1a 내지 도 1b 은 종래기술에 따른 반도체 소자의 층간절연막의 형성 방법을 나타낸 도면,1A to 1B illustrate a method of forming an interlayer insulating film of a semiconductor device according to the prior art;
도 2 는 본 발명의 일실시예에 따른 반도체 소자의 층간절연막의 형성 방법을 나타낸 도면,2 is a view showing a method of forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention;
도 3 은 본 발명의 다른 실시예에 따른 반도체 소자의 층간절연막의 형성 방법을 나타낸 도면,3 is a view showing a method of forming an interlayer insulating film of a semiconductor device according to another embodiment of the present invention;
도 4 는 도 3 의 플라즈마 산화막이 형성된 후 열처리 공정에서의 층간절연막들의 반응을 나타낸 도면.4 is a view illustrating a reaction of interlayer insulating films in a heat treatment process after the plasma oxide film of FIG. 3 is formed;
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
21 : 반도체 기판 22 : 도전층21 semiconductor substrate 22 conductive layer
23 : 보호막 24 : 질화산화막23: protective film 24: nitrided oxide film
25 : 도핑 층간절연막 26 : 플라즈마 산화막25 doped interlayer insulating film 26 plasma oxide film
상기의 목적을 달성하기 위한 본 발명의 일실시예에 따른 반도체 소자의 층간절연막의 형성 방법은 다수의 도전층이 형성된 반도체 기판의 전체 표면을 따라 제 1 절연막을 형성하는 제 1 단계, 상기 제 1 절연막 상부에 후속 절연막의 접착력을 증가시키기 위한 처리를 실시하는 제 2 단계, 상기 제 2 단계가 완료된 결과물 상에 -10℃∼50℃의 온도에서 SiH4+ H2O2반응 소오스와 5A 족 원소를 함유한 도핑 소오스를 사용하여 도핑된 제 2 절연막을 형성하는 제 3 단계, 상기 제 2 절연막상에 플라즈마 산화막을 형성하는 제 4 단계를 포함하여 이루어짐을 특징으로 하고, 본 발명의 다른 실시예에 따른 반도체 소자의 층간절연막의 형성 방법은 다수의 도전층이 형성된 기판의 전체 표면을 따라 제 1 절연막을 형성하는 제 1 단계, 상기 제 1 절연막상에 후속 절연막의 접착력을 증가시키기 위한 처리를 하는 제 2 단계, 상기 제 2 단계가 완료된 결과물 상에 SiH4+ H2O2반응소오스를 이용하여 비도핑된 제 2 절연막을 형성하는 단계, 상기 제 2 절연막 상에 -10℃∼50℃의 온도에서 SiH4+ H2O2반응 소오스와 5A 족 원소를 함유한 도핑 소오스를 사용하여 도핑된 제 3 절연막을 형성하는 제 3 단계, 상기 제 3 절연막상에 플라즈마 산화막을 형성하는 제 4 단계, 상기 결과물 전면에 열처리 공정을 실시하여 상기 비도핑된 제 2 절연막을 도핑된 제 4 절연막으로 전환하는 제 5 단계 포함하여 이루어짐을 특징으로 한다.A method of forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention for achieving the above object is a first step of forming a first insulating film along the entire surface of a semiconductor substrate having a plurality of conductive layers, the first A second step of performing a treatment to increase the adhesion of the subsequent insulating film on the insulating film, the SiH 4 + H 2 O 2 reaction source and a group 5A element at a temperature of -10 ℃ to 50 ℃ on the resultant And a fourth step of forming a doped second insulating film by using a doping source containing a fourth step, and forming a plasma oxide film on the second insulating film, in another embodiment of the present invention. A method of forming an interlayer insulating film of a semiconductor device according to the present invention includes a first step of forming a first insulating film along an entire surface of a substrate on which a plurality of conductive layers are formed, and subsequent steps on the first insulating film. A second step of the process for increasing the film adhesion, the method comprising: using an SiH 4 + H 2 O 2 reaction source on the result that the second stage is completed to form a second insulating film of non-doped, wherein the second insulating film A third step of forming a doped third insulating film using a SiH 4 + H 2 O 2 reaction source and a doping source containing a Group 5A element at a temperature of -10 ° C. to 50 ° C., and plasma on the third insulating film And a fourth step of forming an oxide film and a fifth step of converting the undoped second insulating film into a doped fourth insulating film by performing a heat treatment process on the entire surface of the resultant product.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2 는 본 발명의 일시예에 따른 반도체 소자의 층간절연막의 형성 방법을 나타낸 도면이다.2 is a view showing a method of forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.
도 2 에 도시된 바와 같이, 반도체 기판(21)상에 도전층을 증착한 후, 상기 도전층상에 감광막을 도포하고 노광 및 현상 공정으로 선택적으로 패터닝한다. 이어 패터닝된 감광막을 식각 마스크로 이용하여 도전층을 선택적으로 제거하여 다수개의 배선(22)을 형성한다.As shown in FIG. 2, after depositing a conductive layer on the semiconductor substrate 21, a photosensitive film is coated on the conductive layer and selectively patterned by an exposure and development process. Next, the conductive layer is selectively removed using the patterned photoresist as an etching mask to form a plurality of wirings 22.
이어 550℃∼800℃의 온도와 1mtorr∼760torr 의 압력을 유지하는 CVD 장비에서 SiH4, TEOS, O2,O3,N2O 등의 반응 가스를 이용하여 상기 배선(22)을 포함한 전면에 보호막(23)으로서 산화막을 형성하거나, 또는 NH3가스를 이용하여 질화막 또는 질화 산화막을 형성한다. 여기서 상기 보호막(23)은 100Å이상의 두께로 형성된다.Subsequently, in a CVD apparatus maintaining a temperature of 550 ° C. to 800 ° C. and a pressure of 1 mtorr to 760 tor, a reaction gas such as SiH 4 , TEOS, O 2 , O 3 , or N 2 O may be used on the entire surface including the wiring 22. An oxide film is formed as the protective film 23, or a nitride film or a nitride oxide film is formed using NH 3 gas. In this case, the protective film 23 is formed to a thickness of 100 kPa or more.
이어 후속 절연막 형성 공정의 접착력을 향상시키도록 일정 두께의 질화 산화막(24)을 증착하거나, 산소(O2)를 함유한 플라즈마 처리를 실시한다. 여기서 상기 질화 산화막(24)은 300℃∼400℃의 온도를 유지하는 반응로내에 SiH4, N2O 반응 가스를 도입하여 상기 반응가스로 인해 발생되는 플라즈마를 이용하여 형성된다. 그리고 플라즈마 처리만을 이용할 경우, N2O 또는 O2반응 가스를 이용하여 300W 이상의 파워로 20초 이상 실시한다.Subsequently, a nitride oxide film 24 having a predetermined thickness is deposited or a plasma treatment containing oxygen (O 2 ) is performed to improve the adhesion of the subsequent insulating film forming process. In this case, the nitride oxide film 24 is formed by introducing a SiH 4 , N 2 O reaction gas into the reactor maintaining a temperature of 300 ℃ to 400 ℃ using a plasma generated by the reaction gas. When only the plasma treatment is used, 20 seconds or more is performed at a power of 300 W or more using N 2 O or O 2 reaction gas.
이어 동일 장비에서 SiH4+H2O2반응 소오스와 주기율표상의 5A 족 원소, 예를 들면 P, As, Sb, Bi를 함유하는 소오스를 함께 반응로에 도입하여 -10℃ ∼ 50℃ 범위의 온도와 100torr의 저압을 유지한 상태에서 상기 배선(22) 사이를 매립하는 도핑 층간 절연막(25)을 형성한다. 이 때 상기 도핑 층간절연막(25)은 하부 단차가 평탄화되도록 1000Å이상의 두께로 형성된다.Then, in the same equipment, a SiH 4 + H 2 O 2 reaction source and a source containing group 5A elements on the periodic table, such as P, As, Sb, and Bi, are introduced together into the reactor, and the temperature is in the range of -10 ° C to 50 ° C. And a doped interlayer insulating film 25 which is buried between the wirings 22 while maintaining a low voltage of 100 torr. At this time, the doped interlayer insulating film 25 is formed to a thickness of 1000 Å or more so that the lower step is flattened.
이어 동일 장비에서 상기 도핑 층간절연막(25)상에 산소에 대한 실리콘의 조성비율이 0.5이상인 플라즈마 산화막(26)을 증착하고 열처리하여 평탄화한다. 이 때 상기 플라즈마 산화막(26)은 300℃∼400℃의 온도를 유지하는 반응로에 SiH4, N2O 반응 가스를 도입하여, 반응 가스들의 플라즈마를 이용하여 500Å이상의 두께로 형성된다.Subsequently, a plasma oxide layer 26 having a composition ratio of silicon to oxygen of 0.5 or more is deposited on the doped interlayer insulating layer 25 and heat treated to be planarized. At this time, the plasma oxide film 26 is formed into a thickness of 500 kPa or more by introducing SiH 4 , N 2 O reaction gas into the reactor to maintain a temperature of 300 ℃ to 400 ℃.
그리고 플라즈마 산화막(26)이 형성된 후 열처리는 O2,N2,O3,N2O 또는 H2+O2의 혼합가스 분위기에서 350℃∼800℃의 온도에서 5분이상 실시한다.After the plasma oxide film 26 is formed, heat treatment is performed for 5 minutes or more at a temperature of 350 ° C. to 800 ° C. in a mixed gas atmosphere of O 2 , N 2 , O 3 , N 2 O, or H 2 + O 2 .
도 3 은 본 발명의 다른 실시예에 따른 반도체 소자의 층간절연막의 형성 방법을 나타낸 도면이다.3 is a view illustrating a method of forming an interlayer insulating film of a semiconductor device according to another embodiment of the present invention.
도 3 에 도시된 바와 같이, 반도체 기판(31)상에 도전층을 증착한 후, 상기 도전층상에 감광막을 도포하고 노광 및 현상 공정으로 선택적으로 패터닝한다. 이어 패터닝된 감광막을 식각 마스크로 이용하여 도전층을 선택적으로 제거하여 다수개의 배선(32)을 형성한다.As shown in FIG. 3, after depositing a conductive layer on the semiconductor substrate 31, a photosensitive film is coated on the conductive layer and selectively patterned by an exposure and development process. Next, the conductive layer is selectively removed using the patterned photoresist as an etching mask to form a plurality of wirings 32.
이어 보호막으로서 550℃∼800℃의 온도와 1mtorr∼760torr 범위의 압력을 유지하는 CVD 장비에서 SiH4, TEOS, O2,O3,N2O 등의 반응 가스를 이용하여 상기 배선(32)을 포함한 전면에 산화막(33)을 형성하거나, 또는 NH3가스를 이용하여 질화막 또는 질화 산화막을 형성한다. 여기서 상기 산화막(33)은 100Å이상의 두께로 형성된다.Subsequently, the wiring 32 was formed using a reaction gas such as SiH 4 , TEOS, O 2 , O 3 , or N 2 O in a CVD apparatus maintaining a temperature of 550 ° C. to 800 ° C. and a pressure ranging from 1 mtorr to 760 tor as a protective film. An oxide film 33 is formed on the entire surface thereof, or a nitride film or a nitride oxide film is formed using NH 3 gas. In this case, the oxide film 33 is formed to a thickness of 100 kPa or more.
이어 후속 절연막 형성 공정의 접착력을 향상시키도록 일정 두께의 질화 산화막(34)을 증착하거나, 산소(O2)를 함유한 플라즈마 처리를 실시한다. 상기 질화 산화막(34)은 300℃∼400℃의 온도를 유지하는 반응로내에 SiH4, N2O 반응 가스를 도입하여 상기 반응가스로 인해 발생되는 플라즈마를 이용하여 형성된다. 이러한 플라즈마 처리만을 이용할 경우, N2O 또는 O2반응 가스를 300W 이상의 파워로 20초 이상 실시한다.Subsequently, a nitride oxide film 34 having a predetermined thickness is deposited or a plasma treatment containing oxygen (O 2 ) is performed to improve the adhesion of the subsequent insulating film forming process. The nitride oxide film 34 is formed using a plasma generated by the reaction gas by introducing a SiH 4 , N 2 O reaction gas into the reactor to maintain a temperature of 300 ℃ to 400 ℃. When only such a plasma treatment is used, N 2 O or O 2 reaction gas is performed for 20 seconds or more with a power of 300 W or more.
이어 동일 장비에서 SiH4+H2O2반응 소오스를 반응로에 도입하여 -10℃ ∼ 50℃ 범위의 온도와 100torr의 저압을 유지한 상태에서 상기 배선(32) 사이를 매립할만큼만 비도핑 층간절연막(35)을 형성한다. 이 때 상기 비도핑 층간절연막(35)은 1000Å이하의 두께로 형성된다.Then, in the same equipment, the SiH 4 + H 2 O 2 reaction source was introduced into the reactor, and the undoped interlayer was formed so as to fill the space between the wiring 32 while maintaining a temperature in the range of -10 ° C to 50 ° C and a low pressure of 100torr. The insulating film 35 is formed. At this time, the undoped interlayer insulating film 35 is formed to a thickness of 1000 Å or less.
이어 동일 장비에서 SiH4+H2O2반응 소오스와 주기율표상의 5A 족 원소, 예를 들면 P, As, Sb, Bi를 함유하는 도핑 소오스를 함께 반응로에 도입하여, -10℃ ∼ 50℃ 범위의 온도와 100torr의 저압을 유지한 상태에서 상기 비도핑 층간절연막 (35)상에 제 1 도핑 층간절연막(36)을 1000Å이상의 두께로 형성한다. 이 때 반응소오스의 유량을 조절하여 형성된 제 1 도핑 층간절연막(36)이 산소 결핍의 불완전 산화물(DXO)의 조성을 갖도록 형성한다. 상기 산소 결핍의 불완전 산화물은 도핑원소(DX)들의 산화물이다.Subsequently, SiH 4 + H 2 O 2 reaction source and a doping source containing Group 5A elements on the periodic table, such as P, As, Sb, and Bi, in the same equipment are introduced together into the reactor, and ranges from -10 ° C to 50 ° C. A first doped interlayer insulating film 36 is formed on the undoped interlayer insulating film 35 to a thickness of 1000 kPa or more while maintaining a temperature of 100torr and a low pressure of 100torr. At this time, the first doped interlayer insulating film 36 formed by adjusting the flow rate of the reaction source is formed to have a composition of oxygen-deficient incomplete oxide (D X O). The oxygen deficient incomplete oxide is an oxide of doping elements (D X ).
이어 동일 장비에서 상기 제 1 도핑 층간절연막(36)상에 산소에 대한 실리콘의 조성비율이 0.5이상의 플라즈마 산화막(37)을 증착하고 열처리하여 평탄화한다. 이 때 상기 플라즈마 산화막(37)은 300℃∼400℃의 온도를 유지하는 반응로에 SiH4, N2O 반응 가스를 도입하여, 반응 가스들의 플라즈마를 이용하여 500Å이상으로 형성되며 층간절연막의 평탄도를 증가시키기 위해 증착된다.Subsequently, a plasma oxide film 37 having a composition ratio of oxygen to oxygen of 0.5 or more is deposited on the first doped interlayer insulating film 36 and heat treated to be planarized. At this time, the plasma oxide film 37 is formed by introducing SiH 4 , N 2 O reaction gas into a reaction furnace maintaining a temperature of 300 ° C. to 400 ° C., using a plasma of the reaction gases, to be formed at 500 kV or more, and to planarize the interlayer insulating film. Deposited to increase the degree.
그리고 플라즈마 산화막(37)이 형성된 후 열처리는 O2,N2,O3,N2O 또는 H2+O2의 혼합가스 분위기에서 350℃∼800℃의 온도에서 5분이상 실시한다.After the plasma oxide film 37 is formed, heat treatment is performed for 5 minutes or more at a temperature of 350 ° C. to 800 ° C. in a mixed gas atmosphere of O 2 , N 2 , O 3 , N 2 O or H 2 + O 2 .
도 4 는 플라즈마 산화막(37)이 형성된 후 열처리 공정에서의 층간절연막들 (35,36)의 반응을 나타낸 도면이다.4 shows the reaction of the interlayer insulating films 35 and 36 in the heat treatment process after the plasma oxide film 37 is formed.
이와 같은 열처리중 하층의 얇은 비도핑 층간절연막(35)에서는 수분(H2O)을 방출시키며, 상층의 제 1 도핑 층간절연막(36)에서는 불완전 산소 결핍의 도핑 원소(D+) 또는 산화물(DXO)이 방출된 상기 비도핑 층간절연막(35)의 방출된 수분의 자리로 빠르게 확산된다.During this heat treatment, the lower layer of undoped interlayer insulating film 35 releases water (H 2 O), and the upper layer of first doped interlayer insulating film 36 contains incomplete oxygen deficient doping element (D + ) or oxide (D). X O) diffuses quickly to the site of the released moisture of the undoped interlayer insulating film 35.
또한 방출되는 수분(H2O)과 도핑 원소(D+)들이 반응하여 추가로 산화(D++ O_)되고, 그 산화물(DXO)이 확산되므로써 부피가 큰 도핑산화물(DXO)을 형성하여 후에 형성되는 좁은 도전층(32) 사이의 제 2 도핑 층간절연막(38)을 치밀화한다.In addition, the released water (H 2 O) and the doping element (D + ) reacts to further oxidize (D + + O _ ), and the oxide (D X O) is diffused so that the bulky doping oxide (D X O ) To densify the second doped interlayer insulating film 38 between the narrow conductive layers 32 formed later.
이처럼 상하층간 층간절연막들(35,36)이 서로 반응하여 좁은 도전층(32) 사이의 매립 특성이 우수한 제 2 도핑 층간 절연막(38)을 형성한다. 즉 상기 비도핑 층간 절연막(35)이 열처리후 치밀한 제 2 도핑 층간 절연막(38)으로 전환된다.As such, the upper and lower interlayer insulating films 35 and 36 react with each other to form a second doped interlayer insulating film 38 having excellent buried characteristics between the narrow conductive layers 32. That is, the undoped interlayer insulating film 35 is converted into a dense second doped interlayer insulating film 38 after the heat treatment.
또한 수분이 빠진 자리로 확산되는 산화물(DXO)은 얕은 접합의 파괴를 방지한다.In addition, the oxide (D X O) that diffuses to the site where moisture is lost prevents the breakage of the shallow junction.
이 때 상기 제 1 도핑 층간절연막(36) 상부에 플라즈마 산화막(37)을 증착하지 않고 열처리 공정을 진행한 후, 화학적 기계적 연마(Chemical Mechanical Polishing) 공정으로 연마하여 평탄화하는 방법을 적용할 수 있다.In this case, a heat treatment process may be performed without depositing the plasma oxide layer 37 on the first doped interlayer insulating layer 36, and then may be applied by a chemical mechanical polishing process to planarize the same.
본 발명의 기술적 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명의 층간절연막의 형성 방법은 우수한 매립특성과 자체 유동 특성을 나타내는 SiH4+ H2O 반응 소오스와 주기율표상에서 5A 족 원소를 함유하는 소오스를 함께 반응로에 도입하여 저온에서 패턴들 사이를 매립할 수 있으므로 초미세 패턴에 적용할 수 있다.The method of forming the interlayer insulating film of the present invention described above is performed by introducing a SiH 4 + H 2 O reaction source exhibiting excellent buried characteristics and self-flow characteristics and a source containing a Group 5A element on the periodic table together into a reactor at low temperatures. It can be applied to ultra fine patterns because it can be buried.
그리고 비도핑 층간절연막과 도핑 층간절연막을 적층한 후 열처리하므로써, 비도핑 층간절연막에서 방출하는 수분의 자리로 도핑 층간절연막에서 도핑원소가 확산되므로써 얕은 접합의 파괴를 방지할 수 있다.By stacking and heat-treating the undoped interlayer dielectric film and the doped interlayer dielectric film, doping elements are diffused in the doped interlayer dielectric film to prevent moisture from being emitted from the undoped interlayer dielectric film, thereby preventing the breakage of the shallow junction.
또한 도핑소오스가 함유된 층간절연막을 열처리하여 부피가 큰 도핑산화물을 형성하므로써 치밀한 층간절연막으로 전환시키고, 열처리시 막 수축을 억제하여 안정한 층간절연막을 형성할 수 있다.In addition, by forming a bulky doping oxide by heat-treating the interlayer insulating film containing the doping source, it can be converted into a dense interlayer insulating film, and a stable interlayer insulating film can be formed by suppressing film shrinkage during the heat treatment.
그리고 형성된 도핑 층간절연막중의 도핑이온이 이동성 이온을 포획하므로 소자의 신뢰성을 향상시킬 수 있는 효과가 있다.In addition, since the doping ions in the formed doped interlayer insulating film trap the mobile ions, there is an effect of improving the reliability of the device.
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| KR20030095630A (en) * | 2002-06-12 | 2003-12-24 | 삼성전자주식회사 | Method Of Forming Silicon Dioxide With Superior Gap-Filling Characteristics |
| KR100431741B1 (en) * | 2001-12-29 | 2004-05-17 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device |
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| JPH09116011A (en) * | 1995-10-23 | 1997-05-02 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| KR970052338A (en) * | 1995-12-23 | 1997-07-29 | 김주용 | Manufacturing method of semiconductor device |
| JP3456391B2 (en) * | 1997-07-03 | 2003-10-14 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
| KR19990056330A (en) * | 1997-12-29 | 1999-07-15 | 윤종용 | Gap Filling Method for Semiconductor Devices |
| KR19990062229A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Planarization method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030057606A (en) * | 2001-12-29 | 2003-07-07 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR100431741B1 (en) * | 2001-12-29 | 2004-05-17 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device |
| KR20030095630A (en) * | 2002-06-12 | 2003-12-24 | 삼성전자주식회사 | Method Of Forming Silicon Dioxide With Superior Gap-Filling Characteristics |
| KR100713314B1 (en) * | 2005-12-28 | 2007-05-04 | 동부일렉트로닉스 주식회사 | Method for fabricating pmd in a semiconductor devices |
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| Publication number | Publication date |
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| KR100531467B1 (en) | 2005-11-28 |
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