JPH04359521A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize a low resistance in a source region for a MOS transistor and to make the performance of the title device high by a method wherein one part of a sidewall on the source region is removed and an opening is formed so that impurity ions can be implanted. CONSTITUTION:A sidewall 9 is formed by an etching-back method; after that, impurity ions 10 are implanted into a semiconductor substrate 1; and a diffusion layer which is composed of a low-concentration region 7 and a high- concentration region 11 is formed by a proper heat treatment. Then, a photoresist 12 is formed; after that, an opening is formed only in the upper part of the source regions 7, 11 in the photoresist 12. In addition, one part of the sidewall 9 is removed by a dry etching operation. Then, impurity ions 13 are implanted; a heat treatment is executed. A high-concentration region 14 is formed; it is used as a source for a MOS transistor.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device that can improve reliability even if the distance between gate electrodes of adjacent MOS transistors is narrow.

0002

2. Description of the Related Art FIG. 2 shows a conventional method for manufacturing a semiconductor device, and in particular, FIGS. 2(a) to 2(e) are cross-sectional views of each manufacturing process of the semiconductor device. In the figure, 1 is a semiconductor substrate, 2, 3, and 4 are a gate oxide film, a semiconductor film, and an oxide film that are sequentially covered over the entire surface of the semiconductor substrate 1, and 5 are
8 is a gate electrode formed by photolithography and dry etching; 6 is an impurity ion implantation; 7 is a source low concentration diffusion layer formed by implanting impurity ions 6;
numeral 9 is an oxide film having excellent step coverage, which is entirely covered by CVD technology; numeral 9 is a side wall formed by an etch-back method; numeral 10 is an implanted impurity ion; and numeral 11 is a high concentration diffusion layer of the source.

Next, a method for manufacturing a semiconductor device having the above structure will be explained. First, as shown in Figure 2(a),
A gate oxide film 2, a semiconductor film 3, and an oxide film 4 are sequentially coated on a semiconductor substrate 1 over the entire surface of the substrate. Next, as shown in FIG. 2(b), the gate electrode 5 is formed by photolithography and dry etching to finish into a predetermined pattern. Impurity ions 6 are then obliquely implanted into the semiconductor substrate 1 using an ion implantation technique to form a low concentration diffusion layer 7. Next, as shown in Fig. 2(c), CV
The entire surface is covered with an oxide film 8 using D technique or the like. next,
As shown in FIG. 2(d), sidewalls 9 are formed by an etch-back method. Next, as shown in FIG. 2(e),
Impurity ions 10 are implanted into the semiconductor substrate 1 using ion implantation technology, and a diffusion layer consisting of the low concentration region 7 and the high concentration region 11 of the MOS transistor can be formed by appropriate heat treatment.

0004

[Problems to be Solved by the Invention] Since the conventional semiconductor device manufacturing method is configured as described above,
In a pattern in which the spacing between the gate electrodes 5 of the S transistor is narrow, the impurity ions 10 are not sufficiently implanted, resulting in a problem that the formed diffusion layer has a low concentration and a high resistance.

This invention was made to solve the above problems, and it implants impurity ions into the source region of the diffusion layer to enlarge the high concentration region and lower the resistance of the source of the MOS transistor. The purpose is to

[0006]

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes a step of removing a part of a sidewall that covers a source region of a MOS transistor to form a hole, and a step of forming a hole through the hole. The method includes a step of sufficiently implanting impurity ions into the region.

[0007]

[Operation] The method for manufacturing a semiconductor device according to the present invention is to remove a part of the sidewall above the source region in a pattern in which the distance between the gate electrodes of adjacent MOS transistors is narrow and therefore sufficient impurity ions cannot be implanted. By removing and opening holes and making it possible to implant impurity ions, it is possible to lower the resistance of the source region of the MOS transistor.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a method for manufacturing a semiconductor device according to the present invention, and in particular, FIGS. 1(a) to 1(c) are sectional views showing each manufacturing process of the semiconductor device. In the figure, 12 is a photoresist, 13 is an impurity ion implantation, and 14 is a high concentration, low resistance source region formed by implanting sufficient impurity ions. Next, the manufacturing process of the semiconductor device with the above configuration will be explained. First, Figure 2 (a
) to FIG. 2(e), after forming the sidewall 9 by the etch-back method, the semiconductor substrate 1 is further formed.
Impurity ions 10 are implanted into the region, and by appropriate heat treatment, a low concentration region 7 and a high concentration region 11 are formed as shown in FIG. 1(a).
A diffusion layer is formed. Next, as shown in FIG. 1B, after a photoresist 12 is provided, holes are opened only in the upper portions of the source regions 7 and 11 of the photoresist 12. Furthermore, a portion of the sidewall 9 is removed by dry etching technology. Next, as shown in FIG. 1C, by implanting impurity ions 13 and performing appropriate heat treatment, a high concentration region 14 can be formed and used as a source of a MOS transistor.

[0009]

As described above, according to the present invention, since the distance between the gate electrodes of adjacent MOS transistors is narrow, the source region has a pattern in which sufficient impurity ions cannot be implanted due to the shadow of the sidewall. Furthermore, sufficient impurity ions can be implanted, the resistance of the source region can be reduced, and a high-performance MOS transistor can be obtained.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 Semiconductor substrate 2 Gate oxide film 5 Gate electrode 7 Source low concentration diffusion layer 9 Sidewall 10 Implanted impurity ions 11 High concentration diffusion layer of source 12 Photoresist 13 Implanted impurity ions 14 Low resistance source region

Claims (1)

[Claims] 1. A step of removing and opening a part of a sidewall between gate electrodes of adjacent MOS transistors in a semiconductor integrated circuit device and covering a source region, and implanting impurity ions into the source region. 1. A method for manufacturing a semiconductor device, comprising the steps of: