JPH04357829A - Method and apparatus for dry etching - Google Patents

Abstract

PURPOSE:To prevent an insulation breakdown of a gate oxide film in a dry etching. CONSTITUTION:A dry etching apparatus having a chamber 1 including an etching gas supply port 2 and an etching gas discharge port 3, comprises an anode 4 and a cathode 5 provided in the chamber 1 in such a manner that the anode 4 is grounded, a low pass filter 10 and a DC variable power source 11 connected as a negative bias in parallel with a blocking capacitor 7 and an RF power source 8 in the cathode 5. Flow of an electron current to the cathode is suppressed by the negative bias of the cathode by the DC variable power source, and an insulation breakdown of a gate oxide film is prevented.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method and dry etching apparatus using a DC variable power source.

0002

2. Description of the Related Art In increasing the density of semiconductor integrated circuits, the dimensional width of transistors, wiring, etc. plays a major role. Due to size reduction, fine patterns of 1 μm or less are being put into practical use, but in order to realize such fine patterns, two techniques are required: photolithography technology and dry etching technology.
This is largely due to advances in technology.

The dry etching method utilizes the phenomenon that the material to be etched is etched when placed in reactive plasma or radicals generated by applying radio frequency (RF) power to a suitable gas. To form the pattern, a photoresist pattern is usually used as a mask material. FIG. 5 is a configuration diagram showing a conventional dry etching apparatus (RIE). Reference numeral 1 denotes a metal chamber into which a reactive gas is supplied through a supply port 2. In addition, since the gas is exhausted through the exhaust port 3, the inside of the chamber is maintained at an appropriate pressure (several 100 mTorr).
r). An anode (anode) 4 and a cathode (cathode) 5 are located at the top and bottom of the chamber, respectively.
There is. A material to be etched 6 with a resist pattern is placed on the cathode 5 . Further, an RF power source 8 is connected to the cathode 5 via a blocking capacitor 7, and power is supplied to the gas. The operation of the dry etching apparatus configured as above will be described below.

When an RF power source is applied to the reactive gas in the chamber, a glow discharge occurs between the anode 4 and the cathode 5, as shown in FIG. 6(a), and electrons and ions are generated to generate plasma. At that time, the electrode area in contact with the glow discharge is the anode 4 because the sample is placed on the cathode 5.
becomes larger, and at the same time, the mobility of the former electrons and ions in the plasma is overwhelmingly greater than that of the latter, so electrons flow into the cathode 5, and the blocking capacitor 7 biases the cathode 5 negatively. This bias is called a self-bias voltage Vdc. The potential distribution in the plasma in this state is shown in FIG. 6(b). As shown in FIG. 6(b), the plasma is divided into a bulk region where the potential is constant and a sheath region where the potential changes rapidly near the electrode, and ions are mainly generated in the bulk region. The ions generated in the bulk region enter the sheath region from the bulk-sheath boundary 9, are accelerated by the negative voltage in the sheath region, and impact the material to be etched 6 to cause an etching reaction, resulting in an etching reaction with strong directionality, so-called heterogeneity. Directional etching is obtained.

The manner in which a negative self-bias voltage is applied to the cathode 5 will be explained. As mentioned above, the mobility of electrons and ions generated by discharge is large, so the current-voltage characteristics generally resemble those of a rectifier with a large leakage current. Therefore, when an RF signal is first applied to the cathode 5,
During the positive half cycle of the RF signal, electrons with high mobility flow largely toward the cathode 5, which has a positive potential, but on the other hand, in the next half cycle, only a few ions with low mobility flow into the cathode 5, which has a negative potential. There is no flow, and the number of electrons and ions becomes non-equilibrium. Therefore, a space charge of electrons is generated in the cathode 5 to bounce the electrons, and a negative self-bias voltage is generated in the cathode 5 to reduce excess electrons. In this way, after several cycles, the cathode 5 reaches a negative bias potential so that only a number of electrons equal to the initial number of ions are produced, and the time averaged net current becomes zero, and a steady state is reached. This potential is called self-bias. On the other hand, in the plasma, electrons diffuse outward, resulting in a shortage, resulting in a slightly positive potential. This potential is called a plasma potential (Vp). The time change of the cathode potential in this state is as shown in FIG. As shown in FIG. 7, electrons flow in a period more positive than the ground potential +Vp, and ions flow in a period more negative than that. Since there is a long period of time in which only ions flow, a sheath consisting almost exclusively of ions is formed on the cathode 5, and a dark region is observed relative to the bulk of the plasma.

[0006]

[Problems to be Solved by the Invention] Recently, as the degree of integration of semiconductors has increased, fine processing technology has become necessary. However, as the gate oxide film of the transistor becomes thinner as the dimensions are reduced, dielectric breakdown of the gate oxide film that occurs during dry etching has become a problem. This is thought to be because the voltage applied to the gate oxide film increases during etching, and the gate oxide film of the chip around the wafer is particularly likely to be destroyed.

The effect of electron current is considered to be the cause of the increase in the voltage applied to the gate oxide film. As described above, when the potential of the cathode shown in FIG. 7 becomes positive with respect to the plasma potential, a large amount of electron current instantly flows into the substrate. When a large amount of electron current flows into the substrate and gate electrode, the amount of charging of the gate electrode increases and the MO
A high voltage is applied to the S capacitor, resulting in dielectric breakdown of the gate oxide film.

As described above, dielectric breakdown of the gate oxide film is concentrated around the wafer. To explain the cause of this, FIG. 8 shows the distribution of the plasma potential and the potential of the substrate electrode when the plasma reaches a steady state in dry etching. At the periphery of the substrate, the electron density is low because the plasma is in contact with the side wall of the chamber, so the plasma potential is not constant; it is high at the center of the substrate and conversely at the periphery, as shown in Figure 8. It's getting lower. As a result, as shown in FIG. 9, the substrate potential at the center of the substrate is not much higher than the plasma potential, so the electron current is smaller than the ionic current. Therefore, as shown in (Equation 1), at the center of the substrate, the ionic current is only slightly larger than the electron current in the current flowing into the substrate during one period, so the overall current flowing into the gate oxide film is The voltage is not very high,
The gate oxide film is not easily destroyed.

[0009]

[Math 1]

On the other hand, as shown in FIG. 10, the substrate potential around the substrate takes a long time to rise higher than the plasma potential, and therefore, as shown in equation (2), the substrate potential increases during one period. The electronic current flowing into the substrate is overwhelmingly larger than the ionic current, and a high voltage is applied to the MOS capacitor, which easily destroys the gate oxide film.

[0011]

[Math 2]

[0012] As described above, as the degree of integration of semiconductors increases, the reliability of the semiconductors decreases and the yield rate deteriorates due to dielectric breakdown of the chips around the wafer, into which a large amount of electron current flows. Therefore, it is necessary to prevent a large amount of electron current from flowing locally around the substrate.

The present invention has been made in view of the above-mentioned problems, and aims to provide a dry etching method and a dry etching apparatus that suppress the electron current flowing into the substrate and realize dry etching that does not cause dielectric breakdown of the gate oxide film. purpose.

[0014]

[Means for Solving the Problems] In the dry etching method of the present invention, in etching using plasma generated by RF glow discharge, electrons flowing into the substrate are biased negatively with respect to the plasma potential of the substrate electrode. Characterized by suppressed current.

[0015] Furthermore, the dry etching apparatus of the present invention includes:
An anode and a cathode are provided in a chamber equipped with an etching gas supply and discharge port, the anode is grounded, the cathode is used as a sample stage, and an RF power source is connected via a blocking capacitor, and the blocking capacitor The present invention is characterized in that a voltage source or a current source is connected in parallel to the RF power source as a DC variable power source via a low-pass filter.

[0016]

[Operation] In the dry etching method of the present invention, when the substrate electrode is negatively biased with respect to the plasma potential, the substrate potential is lowered overall, and as a result, the substrate potential around the substrate becomes positive with respect to the plasma potential. There will be no more,
A large amount of electron current flowing locally around the substrate is suppressed, and dielectric breakdown of the gate oxide film around the substrate can be prevented.

The dry etching apparatus of the present invention forcibly biases the substrate electrode negatively by connecting a DC variable power source in parallel with the blocking capacitor and the RF power source through a low-pass filter, thereby causing localized damage to the substrate. The inflow of electron current can be suppressed, and the occurrence of dielectric breakdown of the gate oxide film can be suppressed.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a dry etching apparatus equipped with a DC variable power supply according to an embodiment of the present invention. The feature of this embodiment is that the electron current flowing into the substrate is suppressed by biasing the substrate electrode negatively with respect to the plasma potential. Components having the same functions as those in FIG. 5 are given the same numbers, and detailed explanations will be omitted. Reference numeral 10 denotes a low-pass filter, which cuts off the high frequency waves of the RF power source to prevent them from escaping, and has a high impedance 10 times higher than the plasma impedance for the high frequency waves of the RF power source. Reference numeral 11 denotes a DC variable power supply, which applies a negative bias to the substrate electrode by setting the voltage value to an appropriate value to prevent electron current from flowing into the substrate. This dry etching apparatus includes an anode 4 and a cathode 5 in a chamber 1 equipped with an etching gas supply port 2 and an etching gas discharge port 3. The anode 4 is grounded, and the cathode 5 is connected to a blocking capacitor 7 and an RF power source. This is a device in which a low-pass filter 10 and a DC variable power supply 11 are connected in parallel to 8 for negative bias.

FIG. 3 shows temporal changes in plasma potential and substrate electrode potential when a negative bias is applied to the substrate electrode. As shown in Figure 3, when a negative bias is applied, the substrate potential decreases overall, and as a result, the substrate potential on the opposite side of the substrate is no longer positive with respect to the plasma potential, and the electron current flows to the substrate. Inflow can be suppressed.

In the experiment, two wafers were prepared, one wafer (wafer 1) was dry etched without applying a voltage to the substrate electrode as before, and the other wafer (wafer 2) was dry etched with no voltage applied to the substrate electrode. Etching was performed by applying a voltage of 20V to the . The etching conditions are as follows:
CHF3+O2 is used as the gas system, and the gas pressure is 500m
The oxide film was etched with Torr and RF power of 300 W to form a contact hole for an Al electrode.

Regarding these two wafers, the number of chips where the gate oxide film causes dielectric breakdown is determined by FDDB (Fi
eld Dependent Dielectric
Breakdown). FIG. 2 shows the FDDB results of wafer 1 in which no voltage was applied to the substrate electrode. The x mark indicates a chip with dielectric breakdown of the gate oxide film. Further, FIG. 4(a) shows the ratio of chips with dielectric breakdown in the radial direction of the wafer 1. As shown in FIGS. 2 and 4(a), it can be seen that the dielectrically broken chips are concentrated around the wafer.

On the other hand, in the case of the wafer 2 in which a voltage is applied to the substrate electrode, the ratio of chips that have dielectric breakdown in the radial direction is as shown in FIG. 4(b). Figure 4(a), (
Comparing b), it was confirmed that by applying a voltage to the substrate electrode and performing dry etching, the number of chips with dielectric breakdown was reduced.

This is because applying a negative bias to the substrate electrode during dry etching prevents electron current from flowing into the substrate, suppresses the voltage applied to the gate oxide film, and reduces stress. It is thought that.

Note that the present invention can also be applied to other processes that use plasma, such as plasma CVD. Furthermore, the same effect can be obtained by using not only a voltage source as the DC variable power source but also a current source and setting the current value to an appropriate value.

[0025]

[Effects of the Invention] As explained above, according to the present invention,
By setting the voltage of the DC variable power supply to an appropriate value, it is possible to suppress the flow of electron current into the substrate, and it is possible to suppress the occurrence of dielectric breakdown of the gate oxide film, which has a great practical effect.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a dry etching apparatus equipped with a DC variable power supply according to an embodiment of the present invention.

FIG. 2 is a diagram showing the results of FDDB of a wafer subjected to dry etching without applying a bias to the substrate electrode.

FIG. 3 is a diagram showing temporal changes in substrate potential when a negative bias is applied to the substrate electrode.

FIG. 4(a) is a radial distribution characteristic diagram of gate oxide film breakdown of a wafer subjected to dry etching without applying bias to the substrate electrode. (b) is a distribution characteristic diagram in the radial direction of gate oxide film breakdown of a wafer subjected to dry etching while applying a bias to the substrate electrode.

FIG. 5 is a configuration diagram of a conventional dry etching apparatus (RIE).

FIG. 6(a) is a conceptual diagram of RF plasma. (b) is a diagram showing the potential distribution in plasma.

FIG. 7 is a diagram showing temporal changes in cathode potential.

FIG. 8 is a diagram showing the plasma potential and the potential distribution of the substrate electrode when the plasma is in a steady state.

FIG. 9 is a diagram showing temporal changes in substrate potential at the center of the substrate.

FIG. 10 is a diagram showing temporal changes in substrate potential around the substrate.

[Explanation of symbols]

1 Metallic chamber 4 Anode (anode) 5 Cathode (cathode) 6 Sample 7 Blocking capacitor 8 RF power supply 10 Low pass filter 11　DC variable power supply

Claims (3)

[Claims] 1. A dry etching method characterized in that, in etching using plasma generated by RF glow discharge, electron current flowing into the substrate is suppressed by biasing the substrate electrode negatively with respect to the plasma potential. . 2. The dry etching method according to claim 1, wherein the bias voltage is such that the substrate potential does not become positive with respect to the plasma potential at any time when the plasma reaches a steady state. 3. An anode and a cathode are provided in a chamber equipped with an etching gas supply and discharge port, the anode is grounded, the cathode is used as a sample stage, and an RF power source is connected via a blocking capacitor. . A dry etching apparatus further comprising: a voltage source or a current source as a DC variable power source connected in parallel to the blocking capacitor and the RF power source via a low-pass filter.